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authorDinh Nguyen <dinguyen@kernel.org>2019-06-05 10:05:50 -0500
committerDavid S. Miller <davem@davemloft.net>2019-06-06 14:21:06 -0700
commitb637e0856a6248230e53b5465ab0751f27fdf320 (patch)
tree82b71cb2e5e623c99f7c627654b5b207fc812890 /net/ieee802154/nl-phy.c
parent020aa5c7d42bf9cba171d1e6b4a0196226e4e03d (diff)
downloadlinux-b637e0856a6248230e53b5465ab0751f27fdf320.tar.bz2
dt-bindings: socfpga-dwmac: add "altr, socfpga-stmmac-a10-s10" binding
Add the "altr,socfpga-stmmac-a10-s10" binding for Arria10/Agilex/Stratix10 implementation of the stmmac ethernet controller. On the Arria10, Agilex, and Stratix10 SoCs, there are a few differences from the Cyclone5 and Arria5: - The emac PHY setup bits are in separate registers. - The PTP reference clock select mask is different. - The register to enable the emac signal from FPGA is different. Because of these differences, the dwmac-socfpga glue logic driver will use this new binding to set the appropriate bits for PHY, PTP reference clock, and signal from FPGA. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
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