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| author | David S. Miller <davem@davemloft.net> | 2020-05-04 12:02:03 -0700 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2020-05-04 12:02:03 -0700 |
| commit | ea84c842900872f5b8d6d4754cf0fa37d6672011 (patch) | |
| tree | f2549eebc174b700c1af82de5e5911bb1c3e7239 /net/8021q | |
| parent | 1248dc00fb62bd4dc42b091aa8b245b1b54547ca (diff) | |
| parent | 461d6d058cff60a0fa82c47bf963646418a34d62 (diff) | |
| download | linux-ea84c842900872f5b8d6d4754cf0fa37d6672011.tar.bz2 | |
Merge branch 'net-ethernet-ti-k3-introduce-common-platform-time-sync-driver-cpts'
Grygorii Strashko says:
====================
net: ethernet: ti: k3: introduce common platform time sync driver - cpts
This series introduced support for significantly upgraded TI A65x/J721E Common
platform time sync (CPTS) modules which are part of AM65xx Time Synchronization
Architecture [1].
The TI A65x/J721E now contain more than one CPTS instance:
- MCU CPSW CPTS (IEEE 1588 compliant)
- Main NAVSS CPTS (central)
- PCIe CPTS(s) (PTM compliant)
- J721E: Main CPSW9g CPTS (IEEE 1588 compliant)
which can work as separately as interact to each other through Time Sync Router
(TSR) and Compare Event Router (CER). In addition there are also ICSS-G IEP
blocks which can perform similar timsync functions, but require FW support.
More info also available in TRM [2][3]. Not all above modules are available
to the Linux by as of now as some of them are reserved for RTOS/FW purposes.
The scope of this submission is TI A65x/J721E CPSW CPTS and Main NAVSS CPTS,
and TSR was used for testing purposes.
+---------------------------+
| MCU CPSW |
+-------------------+ +------------------------+ | TS |
| Main Navss CPTS | | Time Sync Router (TSR) | | +-------------+ |
| | | | | | | |
| HW1_TS +<----------+ | | +--------v-----+ +--+--+
| | | | | | CPTS | |Port |
| ... | | | X+-->HW1_TS | | |
| HW8_TS <------------<---------+ | X|-->HW2_TS | +--^--+
| | | | +--------------->HW3_TS | | |
| | | | +--------------->HW4_TS | | |
| | | | | | | | | |
| | | | | | | | | |
| Genf0 +-----------> (A)---------+ +<--------------+Genf0 | | |
| | | | | | | | | |
| ... | | +-----------> <---------------+Genf1 ESTf+-------+ |
| | | | | | | |
| | | | | +--------------+ |
| Genf8 +---------->+ | | |
| | | SYNC0 ... SYNC3 | | |
+-------------------+ +------+------------+----+ +---------------------------+
+ +
X X
(A) shows possible routing path for MCU CPSW CPTS Genf0 signal as an example.
Main features of the new TI A65x/J721E CPTS modules are:
- 64-bit timestamp/counter mode support in ns by using add_val
- implemented in HW PPM and nudge adjustment.
- control of time sync events via interrupt or polling
- selection of multiple external reference clock sources
- hardware timestamp of ext. inputs events (HWx_TS_PUSH)
- periodic generator function outputs (TS_GENFx)
- (CPSW only) Ethernet Enhanced Scheduled Traffic Operations (CPTS_ESTFn),
which drives TSN schedule
- timestamping of all RX packets bypassing CPTS FIFO
Patch 1 - DT bindings
Patch 2 - the AM65x/J721E driver
Patch 3 - enables packet timestamping support in TI AM65x/J721E MCU CPSW driver.
Patches 4-7 - DT updates.
=== PTP Testing:
phc2sys -s CLOCK_REALTIME -c eth0 -m -O 0 -u30
phc2sys[627.331]: eth0 rms 409912446712787392 max 1587584079521858304 freq -6665 +/- 35040 delay 832 +/- 27
phc2sys[657.335]: eth0 rms 33 max 66 freq -0 +/- 28 delay 820 +/- 30
phc2sys[687.339]: eth0 rms 37 max 70 freq -1 +/- 32 delay 830 +/- 29
phc2sys[717.343]: eth0 rms 33 max 71 freq -0 +/- 29 delay 828 +/- 23
phc2sys[747.346]: eth0 rms 35 max 75 freq -0 +/- 31 delay 829 +/- 26
phc2sys[777.350]: eth0 rms 37 max 68 freq -1 +/- 32 delay 825 +/- 25
phc2sys[807.354]: eth0 rms 28 max 57 freq -1 +/- 25 delay 824 +/- 21
phc2sys[837.358]: eth0 rms 43 max 81 freq -1 +/- 37 delay 836 +/- 23
phc2sys[867.361]: eth0 rms 33 max 74 freq +0 +/- 29 delay 828 +/- 24
phc2sys[897.365]: eth0 rms 35 max 77 freq -2 +/- 30 delay 824 +/- 25
phc2sys[927.369]: eth0 rms 28 max 50 freq +0 +/- 25 delay 825 +/- 25
ptp4l -P -2 -H -i eth0 -l 6 -m -q -p /dev/ptp1 -f ptp.cfg -s
ptp4l[22095.754]: port 1: MASTER to UNCALIBRATED on RS_SLAVE
ptp4l[22097.754]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED
ptp4l[22159.757]: rms 317 max 1418 freq +79 +/- 186 delay 410 +/- 1
ptp4l[22223.760]: rms 9 max 24 freq +42 +/- 12 delay 409 +/- 1
ptp4l[22287.763]: rms 10 max 28 freq +41 +/- 11 delay 410 +/- 1
ptp4l[22351.767]: rms 10 max 26 freq +34 +/- 12 delay 410 +/- 1
ptp4l[22415.770]: rms 10 max 26 freq +49 +/- 14 delay 410 +/- 1
=== Ext. HW_TS and Genf testing:
For testing purposes Time Sync Router (TSR) can be modeled in DT as pin controller
+ timesync_router: timesync_router@A40000 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0xA40000 0x0 0x800>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x800007ff>;
+ };
then signals routing can be done in board file, for example:
+#define TS_OFFSET(pa, val) (0x4+(pa)*4) (0x80000000 | val)
+
+×ync_router {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_cpts>;
+
+ /* Example of the timesync routing */
+ mcu_cpts: mcu_cpts {
+ pinctrl-single,pins = <
+ /* [cpts genf1] in13 -> out25 [cpts hw4_push] */
+ TS_OFFSET(25, 13)
+ /* [cpts genf1] in13 -> out0 [main cpts hw1_push] */
+ TS_OFFSET(0, 13)
+ /* [main cpts genf0] in4 -> out1 [main cpts hw2_push] */
+ TS_OFFSET(1, 4)
+ /* [main cpts genf0] in4 -> out24 [cpts hw3_push] */
+ TS_OFFSET(24, 4)
+ >;
+ };
+};
will create link:
cpsw cpts Genf1 -> main cpts hw1_push
-> cpsw cpts hw4_push
main cpts Genf0 -> main cpts hw2_push
-> cpsw cpts hw3_push
testptp -d /dev/ptp0 -i 0 -p 1000000000
periodic output request okay
testptp -d /dev/ptp0 -i 1 -e 5
external time stamp request okay
event index 1 at 22583.000000025
event index 1 at 22584.000000025
event index 1 at 22585.000000025
event index 1 at 22586.000000025
event index 1 at 22587.000000025
testptp -d /dev/ptp1 -i 2 -e 5
external time stamp request okay
event index 2 at 1587606764.249304554
event index 2 at 1587606765.249304467
event index 2 at 1587606766.249304380
event index 2 at 1587606767.249304293
event index 2 at 1587606768.249304206
[1] https://www.ti.com/lit/pdf/spracp7
[2] https://www.ti.com/lit/pdf/sprz452
[3] https://www.ti.com/lit/pdf/spruil1
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'net/8021q')
0 files changed, 0 insertions, 0 deletions