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| author | Akash Goel <akash.goel@intel.com> | 2016-10-12 21:54:30 +0530 |
|---|---|---|
| committer | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2016-10-25 09:34:06 +0100 |
| commit | f4e9af4f5af5dab9aee632f3aff0bd8040f1b2c5 (patch) | |
| tree | 1b480f5b214f0c86de482af60352235de19c6654 /init | |
| parent | d6b40b4b179d5c3f57d1191052d4527af7321ad6 (diff) | |
| download | linux-f4e9af4f5af5dab9aee632f3aff0bd8040f1b2c5.tar.bz2 | |
drm/i915: Add low level set of routines for programming PM IER/IIR/IMR register set
So far PM IER/IIR/IMR registers were being used only for Turbo related
interrupts. But interrupts coming from GuC also use the same set.
As a precursor to supporting GuC interrupts, added new low level routines
so as to allow sharing the programming of PM IER/IIR/IMR registers between
Turbo & GuC.
Also similar to PM IMR, maintaining a bitmask for PM IER register, to allow
easy sharing of it between Turbo & GuC without involving a rmw operation.
v2:
- For appropriateness & avoid any ambiguity, rename old functions
enable/disable pm_irq to mask/unmask pm_irq and rename new functions
enable/disable pm_interrupts to enable/disable pm_irq. (Tvrtko)
- Use u32 in place of uint32_t. (Tvrtko)
v3:
- Rename the fields pm_irq_mask & pm_ier_mask and do some cleanup. (Chris)
- Rebase.
v4: Fix the inadvertent disabling of User interrupt for VECS ring causing
failure for certain IGTs.
v5: Use dev_priv with HAS_VEBOX macro. (Tvrtko)
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Diffstat (limited to 'init')
0 files changed, 0 insertions, 0 deletions