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authorStephen Boyd <sboyd@kernel.org>2020-04-03 15:09:32 -0700
committerStephen Boyd <sboyd@kernel.org>2020-04-03 15:09:32 -0700
commit2d11e9a1fd2abe784b334442b36f7d83ff914287 (patch)
tree7d16189365c73b24fcf001f52f17948d6f03da36 /include
parentea0a1fb716c111a76c371ee94aefacc594d72282 (diff)
parentd894992502474a6e84644012deb14a0280acbf96 (diff)
parentdfbfee870234383bd37e4912350f472cdadda3ae (diff)
parentf58272b6f6ed1222f4c41c401d76f51341826a23 (diff)
parent8ca1f3c06f1a21df86cc2cf26edecfdc49a64fae (diff)
downloadlinux-2d11e9a1fd2abe784b334442b36f7d83ff914287.tar.bz2
Merge branches 'clk-phase-errors', 'clk-amlogic', 'clk-renesas' and 'clk-allwinner' into clk-next
- Don't show clk phase when it is invalid * clk-phase-errors: clk: rockchip: fix mmc get phase clk: Fix phase init check clk: Bail out when calculating phase fails during clk registration clk: Move rate and accuracy recalc to mostly consumer APIs clk: Use 'parent' to shorten lines in __clk_core_init() clk: Don't cache errors from clk_ops::get_phase() * clk-amlogic: clk: meson: meson8b: set audio output clock hierarchy clk: meson: g12a: add support for the SPICC SCLK Source clocks dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs clk: meson: gxbb: set audio output clock hierarchy clk: meson: gxbb: add the gxl internal dac gate dt-bindings: clk: meson: add the gxl internal dac gate * clk-renesas: dt-bindings: clock: renesas: cpg-mssr: Convert to json-schema clk: renesas: rcar-usb2-clock-sel: Add reset_control clk: renesas: rcar-usb2-clock-sel: Add multiple clocks management dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add power-domains and resets properties dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix clock[-name]s properties clk: renesas: Remove use of ARCH_R8A7795 clk: renesas: r8a77965: Add RPC clocks clk: renesas: r8a7796: Add RPC clocks clk: renesas: r8a7795: Add RPC clocks clk: renesas: rcar-gen3: Add CCREE clocks * clk-allwinner: clk: sunxi-ng: sun8i-de2: Sort structures clk: sunxi-ng: sun8i-de2: Add R40 specific quirks clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A83T clk: sunxi-ng: sun8i-de2: Don't reuse A83T resets clk: sunxi-ng: sun8i-de2: H6 doesn't have rotate core clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A64 clk: sunxi-ng: sun8i-de2: Split out H5 definitions clk: sunxi-ng: a64: Export MBUS clock