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authorOlof Johansson <olof@lixom.net>2016-11-18 18:42:33 -0800
committerOlof Johansson <olof@lixom.net>2016-11-18 18:42:33 -0800
commitb029ffe00c2886dedbf17b31744f064ba0e4b3c3 (patch)
tree4d9339288ad808d7884b88f6f7a02dce38e6fdd1 /include
parent84f1f0c199fdbdf11eddb8da07d8cd9dcfdaeeb4 (diff)
parent4522112069a976908e32e5dd3231c9272d19794a (diff)
downloadlinux-b029ffe00c2886dedbf17b31744f064ba0e4b3c3.tar.bz2
Merge tag 'tegra-for-4.10-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers
soc: tegra: Core SoC changes for v4.10-rc1 This contains mostly cleanup and new feature work on the power management controller as well as the addition of a Kconfig symbol for the new Tegra186 (Parker) SoC generation. * tag 'tegra-for-4.10-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: pmc: Use consistent naming for PM domains soc/tegra: pmc: Remove genpd when adding provider fails soc/tegra: pmc: Check return code for pm_genpd_init() soc/tegra: pmc: Clean-up I/O rail error messages soc/tegra: pmc: Simplify IO rail bit handling soc/tegra: pmc: Guard against uninitialised PMC clock soc/tegra: pmc: Add I/O pad voltage support soc/tegra: pmc: Use consistent ordering of bit definitions soc/tegra: pmc: Correct type of variable for tegra_pmc_readl() soc/tegra: pmc: Use BIT macro for register field definition Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'include')
-rw-r--r--include/soc/tegra/pmc.h126
1 files changed, 95 insertions, 31 deletions
diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h
index e9e53473a63e..2f271d1b9cea 100644
--- a/include/soc/tegra/pmc.h
+++ b/include/soc/tegra/pmc.h
@@ -76,37 +76,73 @@ int tegra_pmc_cpu_remove_clamping(unsigned int cpuid);
#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
-#define TEGRA_IO_RAIL_CSIA 0
-#define TEGRA_IO_RAIL_CSIB 1
-#define TEGRA_IO_RAIL_DSI 2
-#define TEGRA_IO_RAIL_MIPI_BIAS 3
-#define TEGRA_IO_RAIL_PEX_BIAS 4
-#define TEGRA_IO_RAIL_PEX_CLK1 5
-#define TEGRA_IO_RAIL_PEX_CLK2 6
-#define TEGRA_IO_RAIL_USB0 9
-#define TEGRA_IO_RAIL_USB1 10
-#define TEGRA_IO_RAIL_USB2 11
-#define TEGRA_IO_RAIL_USB_BIAS 12
-#define TEGRA_IO_RAIL_NAND 13
-#define TEGRA_IO_RAIL_UART 14
-#define TEGRA_IO_RAIL_BB 15
-#define TEGRA_IO_RAIL_AUDIO 17
-#define TEGRA_IO_RAIL_HSIC 19
-#define TEGRA_IO_RAIL_COMP 22
-#define TEGRA_IO_RAIL_HDMI 28
-#define TEGRA_IO_RAIL_PEX_CNTRL 32
-#define TEGRA_IO_RAIL_SDMMC1 33
-#define TEGRA_IO_RAIL_SDMMC3 34
-#define TEGRA_IO_RAIL_SDMMC4 35
-#define TEGRA_IO_RAIL_CAM 36
-#define TEGRA_IO_RAIL_RES 37
-#define TEGRA_IO_RAIL_HV 38
-#define TEGRA_IO_RAIL_DSIB 39
-#define TEGRA_IO_RAIL_DSIC 40
-#define TEGRA_IO_RAIL_DSID 41
-#define TEGRA_IO_RAIL_CSIE 44
-#define TEGRA_IO_RAIL_LVDS 57
-#define TEGRA_IO_RAIL_SYS_DDC 58
+/**
+ * enum tegra_io_pad - I/O pad group identifier
+ *
+ * I/O pins on Tegra SoCs are grouped into so-called I/O pads. Each such pad
+ * can be used to control the common voltage signal level and power state of
+ * the pins of the given pad.
+ */
+enum tegra_io_pad {
+ TEGRA_IO_PAD_AUDIO,
+ TEGRA_IO_PAD_AUDIO_HV,
+ TEGRA_IO_PAD_BB,
+ TEGRA_IO_PAD_CAM,
+ TEGRA_IO_PAD_COMP,
+ TEGRA_IO_PAD_CSIA,
+ TEGRA_IO_PAD_CSIB,
+ TEGRA_IO_PAD_CSIC,
+ TEGRA_IO_PAD_CSID,
+ TEGRA_IO_PAD_CSIE,
+ TEGRA_IO_PAD_CSIF,
+ TEGRA_IO_PAD_DBG,
+ TEGRA_IO_PAD_DEBUG_NONAO,
+ TEGRA_IO_PAD_DMIC,
+ TEGRA_IO_PAD_DP,
+ TEGRA_IO_PAD_DSI,
+ TEGRA_IO_PAD_DSIB,
+ TEGRA_IO_PAD_DSIC,
+ TEGRA_IO_PAD_DSID,
+ TEGRA_IO_PAD_EMMC,
+ TEGRA_IO_PAD_EMMC2,
+ TEGRA_IO_PAD_GPIO,
+ TEGRA_IO_PAD_HDMI,
+ TEGRA_IO_PAD_HSIC,
+ TEGRA_IO_PAD_HV,
+ TEGRA_IO_PAD_LVDS,
+ TEGRA_IO_PAD_MIPI_BIAS,
+ TEGRA_IO_PAD_NAND,
+ TEGRA_IO_PAD_PEX_BIAS,
+ TEGRA_IO_PAD_PEX_CLK1,
+ TEGRA_IO_PAD_PEX_CLK2,
+ TEGRA_IO_PAD_PEX_CNTRL,
+ TEGRA_IO_PAD_SDMMC1,
+ TEGRA_IO_PAD_SDMMC3,
+ TEGRA_IO_PAD_SDMMC4,
+ TEGRA_IO_PAD_SPI,
+ TEGRA_IO_PAD_SPI_HV,
+ TEGRA_IO_PAD_SYS_DDC,
+ TEGRA_IO_PAD_UART,
+ TEGRA_IO_PAD_USB0,
+ TEGRA_IO_PAD_USB1,
+ TEGRA_IO_PAD_USB2,
+ TEGRA_IO_PAD_USB3,
+ TEGRA_IO_PAD_USB_BIAS,
+};
+
+/* deprecated, use TEGRA_IO_PAD_{HDMI,LVDS} instead */
+#define TEGRA_IO_RAIL_HDMI TEGRA_IO_PAD_HDMI
+#define TEGRA_IO_RAIL_LVDS TEGRA_IO_PAD_LVDS
+
+/**
+ * enum tegra_io_pad_voltage - voltage level of the I/O pad's source rail
+ * @TEGRA_IO_PAD_1800000UV: 1.8 V
+ * @TEGRA_IO_PAD_3300000UV: 3.3 V
+ */
+enum tegra_io_pad_voltage {
+ TEGRA_IO_PAD_1800000UV,
+ TEGRA_IO_PAD_3300000UV,
+};
#ifdef CONFIG_ARCH_TEGRA
int tegra_powergate_is_powered(unsigned int id);
@@ -118,6 +154,13 @@ int tegra_powergate_remove_clamping(unsigned int id);
int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
struct reset_control *rst);
+int tegra_io_pad_power_enable(enum tegra_io_pad id);
+int tegra_io_pad_power_disable(enum tegra_io_pad id);
+int tegra_io_pad_set_voltage(enum tegra_io_pad id,
+ enum tegra_io_pad_voltage voltage);
+int tegra_io_pad_get_voltage(enum tegra_io_pad id);
+
+/* deprecated, use tegra_io_pad_power_{enable,disable}() instead */
int tegra_io_rail_power_on(unsigned int id);
int tegra_io_rail_power_off(unsigned int id);
#else
@@ -148,6 +191,27 @@ static inline int tegra_powergate_sequence_power_up(unsigned int id,
return -ENOSYS;
}
+static inline int tegra_io_pad_power_enable(enum tegra_io_pad id)
+{
+ return -ENOSYS;
+}
+
+static inline int tegra_io_pad_power_disable(enum tegra_io_pad id)
+{
+ return -ENOSYS;
+}
+
+static inline int tegra_io_pad_set_voltage(enum tegra_io_pad id,
+ enum tegra_io_pad_voltage voltage)
+{
+ return -ENOSYS;
+}
+
+static inline int tegra_io_pad_get_voltage(enum tegra_io_pad id)
+{
+ return -ENOSYS;
+}
+
static inline int tegra_io_rail_power_on(unsigned int id)
{
return -ENOSYS;