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authorLinus Torvalds <torvalds@linux-foundation.org>2019-01-31 23:22:57 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2019-01-31 23:22:57 -0800
commit5b4746a031992d3b788b7e5280d949b8ab6d32d0 (patch)
tree4c41a438f8ebf80e4c12d60c8be213a2c55dd1b5 /include
parent52107c545de1ef684963146d34f3c4ef6922dd99 (diff)
parent9ff1a3b4912528f853048ccd9757ba6a2cc75557 (diff)
downloadlinux-5b4746a031992d3b788b7e5280d949b8ab6d32d0.tar.bz2
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd: "Mostly driver fixes, but there's a core framework fix in here too: - Revert the commits that introduce clk management for the SP clk on MMP2 SoCs (used for OLPC). Turns out it wasn't a good idea and there isn't any need to manage this clk, it just causes more headaches. - A performance regression that went unnoticed for many years where we would traverse the entire clk tree looking for a clk by name when we already have the pointer to said clk that we're looking for - A parent linkage fix for the qcom SDM845 clk driver - An i.MX clk driver rate miscalculation fix where order of operations were messed up - One error handling fix from the static checkers" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: qcom: gcc: Use active only source for CPUSS clocks clk: ti: Fix error handling in ti_clk_parse_divider_data() clk: imx: Fix fractional clock set rate computation clk: Remove global clk traversal on fetch parent index Revert "dt-bindings: marvell,mmp2: Add clock id for the SP clock" Revert "clk: mmp2: add SP clock" Revert "Input: olpc_apsp - enable the SP clock"
Diffstat (limited to 'include')
-rw-r--r--include/dt-bindings/clock/marvell,mmp2.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/marvell,mmp2.h b/include/dt-bindings/clock/marvell,mmp2.h
index 7b24fc791146..228a5e234af0 100644
--- a/include/dt-bindings/clock/marvell,mmp2.h
+++ b/include/dt-bindings/clock/marvell,mmp2.h
@@ -71,7 +71,6 @@
#define MMP2_CLK_CCIC1_MIX 117
#define MMP2_CLK_CCIC1_PHY 118
#define MMP2_CLK_CCIC1_SPHY 119
-#define MMP2_CLK_SP 120
#define MMP2_NR_CLKS 200
#endif