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authorRafael J. Wysocki <rafael.j.wysocki@intel.com>2014-06-03 23:11:59 +0200
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2014-06-03 23:11:59 +0200
commit6ad29246e3053085fdf28b5aa2a248ec787b3446 (patch)
tree0cc4d2d16b445b81b476af7f1799570464059a08 /include
parent2770b8b1fdf03c4dad6fc8f7e38101a9c4082f7b (diff)
parente2d0e90fae82809667f1dcf4d0d9baa421691c7a (diff)
downloadlinux-6ad29246e3053085fdf28b5aa2a248ec787b3446.tar.bz2
Merge branch 'pm-clk'
* pm-clk: clk: new basic clk type for fractional divider
Diffstat (limited to 'include')
-rw-r--r--include/linux/clk-provider.h31
1 files changed, 31 insertions, 0 deletions
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 511917416fb0..fb4eca6907cd 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -413,6 +413,37 @@ struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
unsigned int mult, unsigned int div);
+/**
+ * struct clk_fractional_divider - adjustable fractional divider clock
+ *
+ * @hw: handle between common and hardware-specific interfaces
+ * @reg: register containing the divider
+ * @mshift: shift to the numerator bit field
+ * @mwidth: width of the numerator bit field
+ * @nshift: shift to the denominator bit field
+ * @nwidth: width of the denominator bit field
+ * @lock: register lock
+ *
+ * Clock with adjustable fractional divider affecting its output frequency.
+ */
+
+struct clk_fractional_divider {
+ struct clk_hw hw;
+ void __iomem *reg;
+ u8 mshift;
+ u32 mmask;
+ u8 nshift;
+ u32 nmask;
+ u8 flags;
+ spinlock_t *lock;
+};
+
+extern const struct clk_ops clk_fractional_divider_ops;
+struct clk *clk_register_fractional_divider(struct device *dev,
+ const char *name, const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
+ u8 clk_divider_flags, spinlock_t *lock);
+
/***
* struct clk_composite - aggregate clock of mux, divider and gate clocks
*