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authorAya Levin <ayal@nvidia.com>2021-04-04 10:50:50 +0300
committerSaeed Mahameed <saeedm@nvidia.com>2021-04-06 21:04:35 -0700
commitce28f0fd670ddffcd564ce7119bdefbaf08f02d3 (patch)
treee55fef57d76d63422e0b8abbea6cd80ab43bc760 /include
parenta14587dfc5ad2312dabdd42a610d80ecd0dc8bea (diff)
downloadlinux-ce28f0fd670ddffcd564ce7119bdefbaf08f02d3.tar.bz2
net/mlx5: Fix PPLM register mapping
Add reserved mapping to cover all the register in order to avoid setting arbitrary values to newer FW which implements the reserved fields. Fixes: a58837f52d43 ("net/mlx5e: Expose FEC feilds and related capability bit") Signed-off-by: Aya Levin <ayal@nvidia.com> Reviewed-by: Moshe Shemesh <moshe@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r--include/linux/mlx5/mlx5_ifc.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 1ccedb7816d0..9940070cda8f 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -8835,6 +8835,8 @@ struct mlx5_ifc_pplm_reg_bits {
u8 fec_override_admin_100g_2x[0x10];
u8 fec_override_admin_50g_1x[0x10];
+
+ u8 reserved_at_140[0x140];
};
struct mlx5_ifc_ppcnt_reg_bits {