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| author | Dylan Reid <dgreid@chromium.org> | 2014-11-03 10:28:56 -0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2014-11-04 19:58:02 +0000 |
| commit | ece509c10985ba93ccc8c68f808a9e767250041c (patch) | |
| tree | 6d724e9e40fde130752d1f0cd1278e888a27e085 /include | |
| parent | f114040e3ea6e07372334ade75d1ee0775c355e1 (diff) | |
| download | linux-ece509c10985ba93ccc8c68f808a9e767250041c.tar.bz2 | |
ASoC: max98090: Correct pclk divisor settings
The Baytrail-based chromebooks have a 20MHz mclk, the code was setting
the divisor incorrectly in this case. According to the 98090
datasheet, the divisor should be set to DIV1 for 10 <= mclk <= 20.
Correct this and the surrounding clock ranges as well to match the
datasheet.
Signed-off-by: Dylan Reid <dgreid@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions