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authorEugene Surovegin <ebs@ebshome.net>2005-09-03 15:55:53 -0700
committerLinus Torvalds <torvalds@evo.osdl.org>2005-09-05 00:06:00 -0700
commit3a0a401b40abe31b34673a190c57697e7eced149 (patch)
tree06f90cb48509877d6a162c63acfd452ab350abe4 /include
parent28fa031e765b808520173f750bafbade832ba909 (diff)
downloadlinux-3a0a401b40abe31b34673a190c57697e7eced149.tar.bz2
[PATCH] ppc32: add dcr_base field to ocp_func_mal_data
Add dcr_base field to ocp_func_mal_data. This is preparation step for the new EMAC driver. Signed-off-by: Eugene Surovegin <ebs@ebshome.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-ppc/ibm_ocp.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/asm-ppc/ibm_ocp.h b/include/asm-ppc/ibm_ocp.h
index 7fd4b6ce327a..bd7656fa2026 100644
--- a/include/asm-ppc/ibm_ocp.h
+++ b/include/asm-ppc/ibm_ocp.h
@@ -147,6 +147,7 @@ struct ocp_func_mal_data {
int txde_irq; /* TX Descriptor Error IRQ */
int rxde_irq; /* RX Descriptor Error IRQ */
int serr_irq; /* MAL System Error IRQ */
+ int dcr_base; /* MALx_CFG DCR number */
};
#define OCP_SYSFS_MAL_DATA() \
@@ -157,6 +158,7 @@ OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxeob_irq) \
OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txde_irq) \
OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxde_irq) \
OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, serr_irq) \
+OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, dcr_base) \
\
void ocp_show_mal_data(struct device *dev) \
{ \
@@ -167,6 +169,7 @@ void ocp_show_mal_data(struct device *dev) \
device_create_file(dev, &dev_attr_mal_txde_irq); \
device_create_file(dev, &dev_attr_mal_rxde_irq); \
device_create_file(dev, &dev_attr_mal_serr_irq); \
+ device_create_file(dev, &dev_attr_mal_dcr_base); \
}
/*