diff options
author | Zang Roy-r61911 <tie-fei.zang@freescale.com> | 2006-08-25 14:16:30 +1000 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2006-08-30 14:29:42 +1000 |
commit | 7233593b7844c2db930594ee9c0c872a6900bfcc (patch) | |
tree | afd6d3011feec3d2a2b1d80afd0e4ee9ef5fa3e4 /include | |
parent | 3efbdd136e52ee4028b5bb5b848a6043cf61cd6e (diff) | |
download | linux-7233593b7844c2db930594ee9c0c872a6900bfcc.tar.bz2 |
[POWERPC] Support for "weird" MPICs and fixup mpc7448_hpc2
This adds a new hardware information table for mpic. This enables
the mpic code to deal with mpic controllers with different register
layouts and hardware behaviours.
This introduces CONFIG_MPIC_WEIRD. For boards with non standard mpic
controllers, select CONFIG_MPIC_WEIRD and add its hardware information
in the mpic_infos[] array.
TSI108/109 PIC takes the first index of weird hardware information
table. :) The table can be extended. The Tsi108/109 PIC looks like
standard OpenPIC but, in fact, is different in register mapping and
behavior.
The patch does not affect the behavior of standard mpic. If
CONFIG_MPIC_WEIRD is not defined, the code is essentially identical to
the current code.
[benh@kernel.crashing.org:
This patch is a slightly cleaned up version of Zang Roy's support for
the TSI108 MPIC variant. It also fixes up MPC7448_hpc2 to use the new
version of the type macros and changes the way MPIC is selected in
Kconfig to better match what is done for other system devices.
]
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include')
-rw-r--r-- | include/asm-powerpc/mpic.h | 125 |
1 files changed, 125 insertions, 0 deletions
diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h index eb241c99c457..a9f9604b9eff 100644 --- a/include/asm-powerpc/mpic.h +++ b/include/asm-powerpc/mpic.h @@ -41,6 +41,7 @@ #define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0 #define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0 #define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0 +#define MPIC_GREG_IPI_STRIDE 0x10 #define MPIC_GREG_SPURIOUS 0x000e0 #define MPIC_GREG_TIMER_FREQ 0x000f0 @@ -68,6 +69,7 @@ #define MPIC_CPU_IPI_DISPATCH_1 0x00050 #define MPIC_CPU_IPI_DISPATCH_2 0x00060 #define MPIC_CPU_IPI_DISPATCH_3 0x00070 +#define MPIC_CPU_IPI_DISPATCH_STRIDE 0x00010 #define MPIC_CPU_CURRENT_TASK_PRI 0x00080 #define MPIC_CPU_TASKPRI_MASK 0x0000000f #define MPIC_CPU_WHOAMI 0x00090 @@ -114,6 +116,103 @@ #define MPIC_VEC_TIMER_1 248 #define MPIC_VEC_TIMER_0 247 +/* + * Tsi108 implementation of MPIC has many differences from the original one + */ + +/* + * Global registers + */ + +#define TSI108_GREG_BASE 0x00000 +#define TSI108_GREG_FEATURE_0 0x00000 +#define TSI108_GREG_GLOBAL_CONF_0 0x00004 +#define TSI108_GREG_VENDOR_ID 0x0000c +#define TSI108_GREG_IPI_VECTOR_PRI_0 0x00204 /* Doorbell 0 */ +#define TSI108_GREG_IPI_STRIDE 0x0c +#define TSI108_GREG_SPURIOUS 0x00010 +#define TSI108_GREG_TIMER_FREQ 0x00014 + +/* + * Timer registers + */ +#define TSI108_TIMER_BASE 0x0030 +#define TSI108_TIMER_STRIDE 0x10 +#define TSI108_TIMER_CURRENT_CNT 0x00000 +#define TSI108_TIMER_BASE_CNT 0x00004 +#define TSI108_TIMER_VECTOR_PRI 0x00008 +#define TSI108_TIMER_DESTINATION 0x0000c + +/* + * Per-Processor registers + */ +#define TSI108_CPU_BASE 0x00300 +#define TSI108_CPU_STRIDE 0x00040 +#define TSI108_CPU_IPI_DISPATCH_0 0x00200 +#define TSI108_CPU_IPI_DISPATCH_STRIDE 0x00000 +#define TSI108_CPU_CURRENT_TASK_PRI 0x00000 +#define TSI108_CPU_WHOAMI 0xffffffff +#define TSI108_CPU_INTACK 0x00004 +#define TSI108_CPU_EOI 0x00008 + +/* + * Per-source registers + */ +#define TSI108_IRQ_BASE 0x00100 +#define TSI108_IRQ_STRIDE 0x00008 +#define TSI108_IRQ_VECTOR_PRI 0x00000 +#define TSI108_VECPRI_VECTOR_MASK 0x000000ff +#define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000 +#define TSI108_VECPRI_POLARITY_NEGATIVE 0x00000000 +#define TSI108_VECPRI_SENSE_LEVEL 0x02000000 +#define TSI108_VECPRI_SENSE_EDGE 0x00000000 +#define TSI108_VECPRI_POLARITY_MASK 0x01000000 +#define TSI108_VECPRI_SENSE_MASK 0x02000000 +#define TSI108_IRQ_DESTINATION 0x00004 + +/* weird mpic register indices and mask bits in the HW info array */ +enum { + MPIC_IDX_GREG_BASE = 0, + MPIC_IDX_GREG_FEATURE_0, + MPIC_IDX_GREG_GLOBAL_CONF_0, + MPIC_IDX_GREG_VENDOR_ID, + MPIC_IDX_GREG_IPI_VECTOR_PRI_0, + MPIC_IDX_GREG_IPI_STRIDE, + MPIC_IDX_GREG_SPURIOUS, + MPIC_IDX_GREG_TIMER_FREQ, + + MPIC_IDX_TIMER_BASE, + MPIC_IDX_TIMER_STRIDE, + MPIC_IDX_TIMER_CURRENT_CNT, + MPIC_IDX_TIMER_BASE_CNT, + MPIC_IDX_TIMER_VECTOR_PRI, + MPIC_IDX_TIMER_DESTINATION, + + MPIC_IDX_CPU_BASE, + MPIC_IDX_CPU_STRIDE, + MPIC_IDX_CPU_IPI_DISPATCH_0, + MPIC_IDX_CPU_IPI_DISPATCH_STRIDE, + MPIC_IDX_CPU_CURRENT_TASK_PRI, + MPIC_IDX_CPU_WHOAMI, + MPIC_IDX_CPU_INTACK, + MPIC_IDX_CPU_EOI, + + MPIC_IDX_IRQ_BASE, + MPIC_IDX_IRQ_STRIDE, + MPIC_IDX_IRQ_VECTOR_PRI, + + MPIC_IDX_VECPRI_VECTOR_MASK, + MPIC_IDX_VECPRI_POLARITY_POSITIVE, + MPIC_IDX_VECPRI_POLARITY_NEGATIVE, + MPIC_IDX_VECPRI_SENSE_LEVEL, + MPIC_IDX_VECPRI_SENSE_EDGE, + MPIC_IDX_VECPRI_POLARITY_MASK, + MPIC_IDX_VECPRI_SENSE_MASK, + MPIC_IDX_IRQ_DESTINATION, + MPIC_IDX_END +}; + + #ifdef CONFIG_MPIC_BROKEN_U3 /* Fixup table entry */ struct mpic_irq_fixup @@ -171,15 +270,29 @@ struct mpic volatile u32 __iomem *cpuregs[MPIC_MAX_CPUS]; volatile u32 __iomem *isus[MPIC_MAX_ISU]; +#ifdef CONFIG_MPIC_WEIRD + /* Pointer to HW info array */ + u32 *hw_set; +#endif + /* link */ struct mpic *next; }; +/* + * MPIC flags (passed to mpic_alloc) + * + * The top 4 bits contain an MPIC bhw id that is used to index the + * register offsets and some masks when CONFIG_MPIC_WEIRD is set. + * Note setting any ID (leaving those bits to 0) means standard MPIC + */ + /* This is the primary controller, only that one has IPIs and * has afinity control. A non-primary MPIC always uses CPU0 * registers only */ #define MPIC_PRIMARY 0x00000001 + /* Set this for a big-endian MPIC */ #define MPIC_BIG_ENDIAN 0x00000002 /* Broken U3 MPIC */ @@ -188,6 +301,18 @@ struct mpic #define MPIC_BROKEN_IPI 0x00000008 /* MPIC wants a reset */ #define MPIC_WANTS_RESET 0x00000010 +/* Spurious vector requires EOI */ +#define MPIC_SPV_EOI 0x00000020 +/* No passthrough disable */ +#define MPIC_NO_PTHROU_DIS 0x00000040 + +/* MPIC HW modification ID */ +#define MPIC_REGSET_MASK 0xf0000000 +#define MPIC_REGSET(val) (((val) & 0xf ) << 28) +#define MPIC_GET_REGSET(flags) (((flags) >> 28) & 0xf) + +#define MPIC_REGSET_STANDARD MPIC_REGSET(0) /* Original MPIC */ +#define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109 PIC */ /* Allocate the controller structure and setup the linux irq descs * for the range if interrupts passed in. No HW initialization is |