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| author | Bjorn Helgaas <bhelgaas@google.com> | 2020-01-29 17:00:04 -0600 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2020-01-29 17:00:04 -0600 |
| commit | 4c6a8fe3aaa5ea5508207e062fdd67014fbdd2f7 (patch) | |
| tree | bef380633692d43571d15fb544fbc88a950cdff7 /include/uapi | |
| parent | 61d02c37fcd0b7d3adc8a51160b9335a7b24638f (diff) | |
| parent | 6fd622c226e6d8387bc5340bfb2f2ca7ef28da07 (diff) | |
| download | linux-4c6a8fe3aaa5ea5508207e062fdd67014fbdd2f7.tar.bz2 | |
Merge branch 'remotes/lorenzo/pci/dwc'
- Add intel-gw driver for PCIe host controller on Intel Gateway SoC
(Dilip Kota)
- Use shared DesignWare helpers to configure Fast Training Sequence (FTS)
in artpec6 (Dilip Kota)
* remotes/lorenzo/pci/dwc:
PCI: artpec6: Configure FTS with dwc helper function
PCI: dwc: intel: PCIe RC controller driver
dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller
Diffstat (limited to 'include/uapi')
| -rw-r--r-- | include/uapi/linux/pci_regs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index acb7d2bdb419..5437690483cd 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -676,6 +676,7 @@ #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ +#define PCI_EXP_LNKCTL2_HASD 0x0020 /* HW Autonomous Speed Disable */ #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */ #define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */ |