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authorYong Wu <yong.wu@mediatek.com>2017-08-21 19:00:16 +0800
committerJoerg Roedel <jroedel@suse.de>2017-08-22 16:37:58 +0200
commite6dec92308628cff5f1f8bd1bcdf87581c9dc676 (patch)
treed17007990ff95de3df378b2d6625f25e8b815b54 /include/soc
parenta9467d954226f1a513cfe789a3a39d8fc73b5d16 (diff)
downloadlinux-e6dec92308628cff5f1f8bd1bcdf87581c9dc676.tar.bz2
iommu/mediatek: Add mt2712 IOMMU support
The M4U IP blocks in mt2712 is MTK's generation2 M4U which use the ARM Short-descriptor like mt8173, and most of the HW registers are the same. The difference is that there are 2 M4U HWs in mt2712 while there's only one in mt8173. The purpose of 2 M4U HWs is for balance the bandwidth. Normally if there are 2 M4U HWs, there should be 2 iommu domains, each M4U has a iommu domain. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'include/soc')
-rw-r--r--include/soc/mediatek/smi.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/soc/mediatek/smi.h b/include/soc/mediatek/smi.h
index 8893c5eacd07..5201e9022c86 100644
--- a/include/soc/mediatek/smi.h
+++ b/include/soc/mediatek/smi.h
@@ -19,7 +19,7 @@
#ifdef CONFIG_MTK_SMI
-#define MTK_LARB_NR_MAX 8
+#define MTK_LARB_NR_MAX 16
#define MTK_SMI_MMU_EN(port) BIT(port)