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authorClaudiu Beznea <claudiu.beznea@microchip.com>2022-01-13 16:48:52 +0200
committerNicolas Ferre <nicolas.ferre@microchip.com>2022-02-25 12:36:25 +0100
commit55614e682a2c9fac12a0f121b43b93ff4915d0e6 (patch)
treec7aa9d4afd23aea189b91655b6307258e14c0d42 /include/soc
parentdc3005703f8cd893d325081c20b400e08377d9bb (diff)
downloadlinux-55614e682a2c9fac12a0f121b43b93ff4915d0e6.tar.bz2
ARM: at91: ddr: align macro definitions
Align all macro definitions. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220113144900.906370-3-claudiu.beznea@microchip.com
Diffstat (limited to 'include/soc')
-rw-r--r--include/soc/at91/sama7-ddr.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/include/soc/at91/sama7-ddr.h b/include/soc/at91/sama7-ddr.h
index 13b47e26cdbe..817b360efbb8 100644
--- a/include/soc/at91/sama7-ddr.h
+++ b/include/soc/at91/sama7-ddr.h
@@ -13,11 +13,11 @@
/* DDR3PHY */
#define DDR3PHY_PIR (0x04) /* DDR3PHY PHY Initialization Register */
-#define DDR3PHY_PIR_DLLBYP (1 << 17) /* DLL Bypass */
+#define DDR3PHY_PIR_DLLBYP (1 << 17) /* DLL Bypass */
#define DDR3PHY_PIR_ITMSRST (1 << 4) /* Interface Timing Module Soft Reset */
-#define DDR3PHY_PIR_DLLLOCK (1 << 2) /* DLL Lock */
+#define DDR3PHY_PIR_DLLLOCK (1 << 2) /* DLL Lock */
#define DDR3PHY_PIR_DLLSRST (1 << 1) /* DLL Soft Rest */
-#define DDR3PHY_PIR_INIT (1 << 0) /* Initialization Trigger */
+#define DDR3PHY_PIR_INIT (1 << 0) /* Initialization Trigger */
#define DDR3PHY_PGCR (0x08) /* DDR3PHY PHY General Configuration Register */
#define DDR3PHY_PGCR_CKDV1 (1 << 13) /* CK# Disable Value */
@@ -65,7 +65,7 @@
#define UDDRC_SWSTAT_SW_DONE_ACK (1 << 0) /* Register programming done */
#define UDDRC_PSTAT (0x3FC) /* UDDRC Port Status Register */
-#define UDDRC_PSTAT_ALL_PORTS (0x1F001F) /* Read + writes outstanding transactions on all ports */
+#define UDDRC_PSTAT_ALL_PORTS (0x1F001F) /* Read + writes outstanding transactions on all ports */
#define UDDRC_PCTRL_0 (0x490) /* UDDRC Port 0 Control Register */
#define UDDRC_PCTRL_1 (0x540) /* UDDRC Port 1 Control Register */