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author | Ashish Mhetre <amhetre@nvidia.com> | 2022-05-06 15:23:11 +0200 |
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committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2022-05-09 10:46:11 +0200 |
commit | a7cffa11fa9232eabf0c4f441dc53002978ab526 (patch) | |
tree | 4ccdc2a99c2875162eb8ec1dfe14afca5273bc93 /include/soc/tegra/mc.h | |
parent | cc3d696c01d83dfb2009a2d7ffbb330d2b506ac9 (diff) | |
download | linux-a7cffa11fa9232eabf0c4f441dc53002978ab526.tar.bz2 |
memory: tegra: Add memory controller channels support
From Tegra186 onwards, the memory controller supports multiple channels.
Add support for mapping the address spaces of these channels and specify
the number of channels supported by Tegra186, Tegra194 and Tegra234.
In case of old bindings, channels won't be present. If channels are not
present then print a warning and continue so that backward compatibility
will be preserved in driver.
During error interrupts from memory controller, appropriate registers
from these channels need to be accessed for logging error info.
Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20220506132312.3910637-4-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'include/soc/tegra/mc.h')
-rw-r--r-- | include/soc/tegra/mc.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 1066b1194a5a..40f1d02a1358 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -194,6 +194,7 @@ struct tegra_mc_soc { unsigned int atom_size; u8 client_id_mask; + u8 num_channels; const struct tegra_smmu_soc *smmu; @@ -212,6 +213,8 @@ struct tegra_mc { struct tegra_smmu *smmu; struct gart_device *gart; void __iomem *regs; + void __iomem *bcast_ch_regs; + void __iomem **ch_regs; struct clk *clk; int irq; |