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author | Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> | 2018-07-02 18:18:03 +0900 |
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committer | Vinod Koul <vkoul@kernel.org> | 2018-07-10 20:49:46 +0530 |
commit | 538603c6026ce769eec633bb79349f5f287519c7 (patch) | |
tree | fb908a88e463a1890f9fb4e410c5d04bf7d87b49 /include/keys | |
parent | e919417bd6468b7f1b2899200a78f1ad078757d3 (diff) | |
download | linux-538603c6026ce769eec633bb79349f5f287519c7.tar.bz2 |
dmaengine: sh: rcar-dmac: avoid to write CHCR.TE to 1 if TCR is set to 0
This patch fixes an issue that unexpected retransfering happens
if TCR is set to 0 before rcar_dmac_sync_tcr() writes DE bit to
the CHCR register. For example, sh-sci driver can reproduce this
issue like below:
In rx_timer_fn(): /* CHCR DE bit may be set to 1 */
dmaengine_tx_status()
rcar_dmac_tx_status()
rcar_dmac_chan_get_residue()
rcar_dmac_sync_tcr() /* TCR is possible to be set to 0 */
According to the description of commit 73a47bd0da66 ("dmaengine:
rcar-dmac: use TCRB instead of TCR for residue"), "this buffered data
will be transferred if CHCR::DE bit was cleared". So, this patch
doesn't need to check TCRB register.
Fixes: 73a47bd0da66 ("dmaengine: rcar-dmac: use TCRB instead of TCR for residue")
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'include/keys')
0 files changed, 0 insertions, 0 deletions