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authorGeert Uytterhoeven <geert+renesas@glider.be>2019-11-01 14:25:38 +0100
committerGeert Uytterhoeven <geert+renesas@glider.be>2019-11-01 14:25:38 +0100
commit16208387bbdd7f6503d24ee7826fbd850795a52b (patch)
treedf0053d7a3c7921b73b6771d8bc9c97b4c199b8a /include/dt-bindings
parent4194b583c104922c6141d6610bfbce26847959df (diff)
parent0b05ad22a27998f842cbbc3f285bac05e2c30f4c (diff)
downloadlinux-16208387bbdd7f6503d24ee7826fbd850795a52b.tar.bz2
Merge tag 'renesas-r8a77961-dt-binding-defs-tag' into renesas-drivers-for-v5.5
Renesas R-Car M3-W+ DT Binding Definitions Clock and Power Domain definitions for the Renesas R-Car M3-W+ (R8A77961) SoC, shared by driver and DT source files.
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/clock/r8a77961-cpg-mssr.h65
-rw-r--r--include/dt-bindings/power/r8a77961-sysc.h32
2 files changed, 97 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/r8a77961-cpg-mssr.h b/include/dt-bindings/clock/r8a77961-cpg-mssr.h
new file mode 100644
index 000000000000..7921d785546d
--- /dev/null
+++ b/include/dt-bindings/clock/r8a77961-cpg-mssr.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (C) 2019 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77961 CPG Core Clocks */
+#define R8A77961_CLK_Z 0
+#define R8A77961_CLK_Z2 1
+#define R8A77961_CLK_ZR 2
+#define R8A77961_CLK_ZG 3
+#define R8A77961_CLK_ZTR 4
+#define R8A77961_CLK_ZTRD2 5
+#define R8A77961_CLK_ZT 6
+#define R8A77961_CLK_ZX 7
+#define R8A77961_CLK_S0D1 8
+#define R8A77961_CLK_S0D2 9
+#define R8A77961_CLK_S0D3 10
+#define R8A77961_CLK_S0D4 11
+#define R8A77961_CLK_S0D6 12
+#define R8A77961_CLK_S0D8 13
+#define R8A77961_CLK_S0D12 14
+#define R8A77961_CLK_S1D1 15
+#define R8A77961_CLK_S1D2 16
+#define R8A77961_CLK_S1D4 17
+#define R8A77961_CLK_S2D1 18
+#define R8A77961_CLK_S2D2 19
+#define R8A77961_CLK_S2D4 20
+#define R8A77961_CLK_S3D1 21
+#define R8A77961_CLK_S3D2 22
+#define R8A77961_CLK_S3D4 23
+#define R8A77961_CLK_LB 24
+#define R8A77961_CLK_CL 25
+#define R8A77961_CLK_ZB3 26
+#define R8A77961_CLK_ZB3D2 27
+#define R8A77961_CLK_ZB3D4 28
+#define R8A77961_CLK_CR 29
+#define R8A77961_CLK_CRD2 30
+#define R8A77961_CLK_SD0H 31
+#define R8A77961_CLK_SD0 32
+#define R8A77961_CLK_SD1H 33
+#define R8A77961_CLK_SD1 34
+#define R8A77961_CLK_SD2H 35
+#define R8A77961_CLK_SD2 36
+#define R8A77961_CLK_SD3H 37
+#define R8A77961_CLK_SD3 38
+#define R8A77961_CLK_SSP2 39
+#define R8A77961_CLK_SSP1 40
+#define R8A77961_CLK_SSPRS 41
+#define R8A77961_CLK_RPC 42
+#define R8A77961_CLK_RPCD2 43
+#define R8A77961_CLK_MSO 44
+#define R8A77961_CLK_CANFD 45
+#define R8A77961_CLK_HDMI 46
+#define R8A77961_CLK_CSI0 47
+/* CLK_CSIREF was removed */
+#define R8A77961_CLK_CP 49
+#define R8A77961_CLK_CPEX 50
+#define R8A77961_CLK_R 51
+#define R8A77961_CLK_OSC 52
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/power/r8a77961-sysc.h b/include/dt-bindings/power/r8a77961-sysc.h
new file mode 100644
index 000000000000..7a3800996f7c
--- /dev/null
+++ b/include/dt-bindings/power/r8a77961-sysc.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2019 Glider bvba
+ */
+#ifndef __DT_BINDINGS_POWER_R8A77961_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A77961_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A77961_PD_CA57_CPU0 0
+#define R8A77961_PD_CA57_CPU1 1
+#define R8A77961_PD_CA53_CPU0 5
+#define R8A77961_PD_CA53_CPU1 6
+#define R8A77961_PD_CA53_CPU2 7
+#define R8A77961_PD_CA53_CPU3 8
+#define R8A77961_PD_CA57_SCU 12
+#define R8A77961_PD_CR7 13
+#define R8A77961_PD_A3VC 14
+#define R8A77961_PD_3DG_A 17
+#define R8A77961_PD_3DG_B 18
+#define R8A77961_PD_CA53_SCU 21
+#define R8A77961_PD_A3IR 24
+#define R8A77961_PD_A2VC1 26
+
+/* Always-on power area */
+#define R8A77961_PD_ALWAYS_ON 32
+
+#endif /* __DT_BINDINGS_POWER_R8A77961_SYSC_H__ */