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| author | Mark Brown <broonie@kernel.org> | 2014-11-26 20:37:57 +0000 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2014-11-26 20:37:57 +0000 |
| commit | cf2394f70cf7774a107fbaa1ef5010db4bd69baa (patch) | |
| tree | e79e3e479d04213a67ecd47b31c7db648b0313c2 /include/dt-bindings | |
| parent | 45fc84c668ba6cc08cbae74042be838bf9283d98 (diff) | |
| parent | 206c5f60a3d902bc4b56dab2de3e88de5eb06108 (diff) | |
| download | linux-cf2394f70cf7774a107fbaa1ef5010db4bd69baa.tar.bz2 | |
Merge tag 'v3.18-rc4' into regulator-max77802
Linux 3.18-rc4
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/imx6qdl-clock.h | 8 | ||||
| -rw-r--r-- | include/dt-bindings/clock/vf610-clock.h | 39 |
2 files changed, 35 insertions, 12 deletions
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h index ddaef8620b2c..b690cdba163b 100644 --- a/include/dt-bindings/clock/imx6qdl-clock.h +++ b/include/dt-bindings/clock/imx6qdl-clock.h @@ -62,8 +62,8 @@ #define IMX6QDL_CLK_USDHC3_SEL 50 #define IMX6QDL_CLK_USDHC4_SEL 51 #define IMX6QDL_CLK_ENFC_SEL 52 -#define IMX6QDL_CLK_EMI_SEL 53 -#define IMX6QDL_CLK_EMI_SLOW_SEL 54 +#define IMX6QDL_CLK_EIM_SEL 53 +#define IMX6QDL_CLK_EIM_SLOW_SEL 54 #define IMX6QDL_CLK_VDO_AXI_SEL 55 #define IMX6QDL_CLK_VPU_AXI_SEL 56 #define IMX6QDL_CLK_CKO1_SEL 57 @@ -106,8 +106,8 @@ #define IMX6QDL_CLK_USDHC4_PODF 94 #define IMX6QDL_CLK_ENFC_PRED 95 #define IMX6QDL_CLK_ENFC_PODF 96 -#define IMX6QDL_CLK_EMI_PODF 97 -#define IMX6QDL_CLK_EMI_SLOW_PODF 98 +#define IMX6QDL_CLK_EIM_PODF 97 +#define IMX6QDL_CLK_EIM_SLOW_PODF 98 #define IMX6QDL_CLK_VPU_AXI_PODF 99 #define IMX6QDL_CLK_CKO1_PODF 100 #define IMX6QDL_CLK_AXI 101 diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h index d6b56b21539b..801c0ac50c47 100644 --- a/include/dt-bindings/clock/vf610-clock.h +++ b/include/dt-bindings/clock/vf610-clock.h @@ -21,24 +21,24 @@ #define VF610_CLK_FASK_CLK_SEL 8 #define VF610_CLK_AUDIO_EXT 9 #define VF610_CLK_ENET_EXT 10 -#define VF610_CLK_PLL1_MAIN 11 +#define VF610_CLK_PLL1_SYS 11 #define VF610_CLK_PLL1_PFD1 12 #define VF610_CLK_PLL1_PFD2 13 #define VF610_CLK_PLL1_PFD3 14 #define VF610_CLK_PLL1_PFD4 15 -#define VF610_CLK_PLL2_MAIN 16 +#define VF610_CLK_PLL2_BUS 16 #define VF610_CLK_PLL2_PFD1 17 #define VF610_CLK_PLL2_PFD2 18 #define VF610_CLK_PLL2_PFD3 19 #define VF610_CLK_PLL2_PFD4 20 -#define VF610_CLK_PLL3_MAIN 21 +#define VF610_CLK_PLL3_USB_OTG 21 #define VF610_CLK_PLL3_PFD1 22 #define VF610_CLK_PLL3_PFD2 23 #define VF610_CLK_PLL3_PFD3 24 #define VF610_CLK_PLL3_PFD4 25 -#define VF610_CLK_PLL4_MAIN 26 -#define VF610_CLK_PLL5_MAIN 27 -#define VF610_CLK_PLL6_MAIN 28 +#define VF610_CLK_PLL4_AUDIO 26 +#define VF610_CLK_PLL5_ENET 27 +#define VF610_CLK_PLL6_VIDEO 28 #define VF610_CLK_PLL3_MAIN_DIV 29 #define VF610_CLK_PLL4_MAIN_DIV 30 #define VF610_CLK_PLL6_MAIN_DIV 31 @@ -166,9 +166,32 @@ #define VF610_CLK_DMAMUX3 153 #define VF610_CLK_FLEXCAN0_EN 154 #define VF610_CLK_FLEXCAN1_EN 155 -#define VF610_CLK_PLL7_MAIN 156 +#define VF610_CLK_PLL7_USB_HOST 156 #define VF610_CLK_USBPHY0 157 #define VF610_CLK_USBPHY1 158 -#define VF610_CLK_END 159 +#define VF610_CLK_LVDS1_IN 159 +#define VF610_CLK_ANACLK1 160 +#define VF610_CLK_PLL1_BYPASS_SRC 161 +#define VF610_CLK_PLL2_BYPASS_SRC 162 +#define VF610_CLK_PLL3_BYPASS_SRC 163 +#define VF610_CLK_PLL4_BYPASS_SRC 164 +#define VF610_CLK_PLL5_BYPASS_SRC 165 +#define VF610_CLK_PLL6_BYPASS_SRC 166 +#define VF610_CLK_PLL7_BYPASS_SRC 167 +#define VF610_CLK_PLL1 168 +#define VF610_CLK_PLL2 169 +#define VF610_CLK_PLL3 170 +#define VF610_CLK_PLL4 171 +#define VF610_CLK_PLL5 172 +#define VF610_CLK_PLL6 173 +#define VF610_CLK_PLL7 174 +#define VF610_PLL1_BYPASS 175 +#define VF610_PLL2_BYPASS 176 +#define VF610_PLL3_BYPASS 177 +#define VF610_PLL4_BYPASS 178 +#define VF610_PLL5_BYPASS 179 +#define VF610_PLL6_BYPASS 180 +#define VF610_PLL7_BYPASS 181 +#define VF610_CLK_END 182 #endif /* __DT_BINDINGS_CLOCK_VF610_H */ |