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| author | Jonghwa Lee <jonghwa3.lee@samsung.com> | 2014-05-27 20:27:08 +0900 |
|---|---|---|
| committer | Tomasz Figa <t.figa@samsung.com> | 2014-06-30 15:07:56 +0200 |
| commit | 17d3f1d27ce2fd377ddb03531b87dd9e96e01b34 (patch) | |
| tree | 5e337db7eaa68d4a17eca7c5ba3aee0b939e9e8f /include/dt-bindings | |
| parent | d5e136a21b2028fb1f45143ea7112d5869bfc6c7 (diff) | |
| download | linux-17d3f1d27ce2fd377ddb03531b87dd9e96e01b34.tar.bz2 | |
clk: exynos4: Add PPMU IP block source clocks.
Exynos4 has saveral PPMUs and each of them has operation clock which
can be gated through CMU's SFR control.
New clocks are listed below. All clocks are added as a gate-typed clock.
CLK_PPMULEFT, CLK_PPMURIGHT, CLK_PPMUCAMIF, CLK_PPMUTV, CLK_PPMUMFC_L,
CLK_PPMUMFC_R, CLK_G3D, CLK_PPMUIMAGE, CLK_PPMULCD0, CLK_PPMULCD1,
CLK_PPMUFILE, CLK_PPMUGPS, CLK_PPMUDMC0, CLK_PPMUDMC1, CLK_PPMUCPU,
CLK_PPMUACP,
Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Myungjoo Ham <myungjoo.ham@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/exynos4.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h index 1106ca540a96..60fadfc8d6ba 100644 --- a/include/dt-bindings/clock/exynos4.h +++ b/include/dt-bindings/clock/exynos4.h @@ -230,6 +230,24 @@ #define CLK_MOUT_G3D 394 #define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */ +/* gate clocks - ppmu */ +#define CLK_PPMULEFT 400 +#define CLK_PPMURIGHT 401 +#define CLK_PPMUCAMIF 402 +#define CLK_PPMUTV 403 +#define CLK_PPMUMFC_L 404 +#define CLK_PPMUMFC_R 405 +#define CLK_PPMUG3D 406 +#define CLK_PPMUIMAGE 407 +#define CLK_PPMULCD0 408 +#define CLK_PPMULCD1 409 /* Exynos4210 only */ +#define CLK_PPMUFILE 410 +#define CLK_PPMUGPS 411 +#define CLK_PPMUDMC0 412 +#define CLK_PPMUDMC1 413 +#define CLK_PPMUCPU 414 +#define CLK_PPMUACP 415 + /* div clocks */ #define CLK_DIV_ISP0 450 /* Exynos4x12 only */ #define CLK_DIV_ISP1 451 /* Exynos4x12 only */ |