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| author | Tao Zhou <tao.zhou1@amd.com> | 2020-10-02 11:21:47 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-10-12 14:00:01 -0400 |
| commit | a2468e043ae48fbeabdc966847a6675da47a7dc4 (patch) | |
| tree | dc3b2895b84c4e7da1e803e8e5d3becf19d93719 /include/drm | |
| parent | cd294f9a645f254bb4f5e15c64eb8aec5d4a4fda (diff) | |
| download | linux-a2468e043ae48fbeabdc966847a6675da47a7dc4.tar.bz2 | |
drm/amdgpu: add dimgrey_cavefish asic type
Add chip type for dimgrey_cavefish.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'include/drm')
| -rw-r--r-- | include/drm/amd_asic_type.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/drm/amd_asic_type.h b/include/drm/amd_asic_type.h index 6d01cf04b77f..cde3c8c9f20c 100644 --- a/include/drm/amd_asic_type.h +++ b/include/drm/amd_asic_type.h @@ -57,6 +57,7 @@ enum amd_asic_type { CHIP_SIENNA_CICHLID, /* 28 */ CHIP_NAVY_FLOUNDER, /* 29 */ CHIP_VANGOGH, /* 30 */ + CHIP_DIMGREY_CAVEFISH, /* 31 */ CHIP_LAST, }; |