diff options
| author | David Howells <dhowells@redhat.com> | 2006-10-09 12:19:47 +0100 |
|---|---|---|
| committer | David Howells <dhowells@redhat.com> | 2006-10-09 12:19:47 +0100 |
| commit | 40220c1a192f51695f806d75b1f9970f0f17a6e8 (patch) | |
| tree | 86623a8c361420c22c6511b20770057fd9c9881d /include/asm-sparc | |
| parent | 58ba81dba77eab43633ea47d82e96245ae3ff666 (diff) | |
| download | linux-40220c1a192f51695f806d75b1f9970f0f17a6e8.tar.bz2 | |
IRQ: Use the new typedef for interrupt handler function pointers
Use the new typedef for interrupt handler function pointers rather than
actually spelling out the full thing each time. This was scripted with the
following small shell script:
#!/bin/sh
egrep -nHrl -e 'irqreturn_t[ ]*[(][*]' $* |
while read i
do
echo $i
perl -pi -e 's/irqreturn_t\s*[(]\s*[*]\s*([_a-zA-Z0-9]*)\s*[)]\s*[(]\s*int\s*,\s*void\s*[*]\s*[)]/irq_handler_t \1/g' $i || exit $?
done
Signed-Off-By: David Howells <dhowells@redhat.com>
Diffstat (limited to 'include/asm-sparc')
| -rw-r--r-- | include/asm-sparc/irq.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/include/asm-sparc/irq.h b/include/asm-sparc/irq.h index 70867330f422..ff520ea97473 100644 --- a/include/asm-sparc/irq.h +++ b/include/asm-sparc/irq.h @@ -76,8 +76,8 @@ static inline void load_profile_irq(int cpu, int limit) BTFIXUP_CALL(load_profile_irq)(cpu, limit); } -extern void (*sparc_init_timers)(irqreturn_t (*lvl10_irq)(int, void *)); -extern void claim_ticker14(irqreturn_t (*irq_handler)(int, void *), +extern void (*sparc_init_timers)(irq_handler_t lvl10_irq); +extern void claim_ticker14(irq_handler_t irq_handler, int irq, unsigned int timeout); @@ -91,7 +91,7 @@ BTFIXUPDEF_CALL(void, set_irq_udt, int) #define set_irq_udt(cpu) BTFIXUP_CALL(set_irq_udt)(cpu) #endif -extern int request_fast_irq(unsigned int irq, irqreturn_t (*handler)(int, void *), unsigned long flags, __const__ char *devname); +extern int request_fast_irq(unsigned int irq, irq_handler_t handler, unsigned long flags, __const__ char *devname); /* On the sun4m, just like the timers, we have both per-cpu and master * interrupt registers. |