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authorMartin Schwidefsky <schwidefsky@de.ibm.com>2006-09-28 16:56:43 +0200
committerMartin Schwidefsky <schwidefsky@de.ibm.com>2006-09-28 16:56:43 +0200
commit94c12cc7d196bab34aaa98d38521549fa1e5ef76 (patch)
tree8e0cec0ed44445d74a2cb5160303d6b4dfb1bc31 /include/asm-s390/sigp.h
parent25d83cbfaa44e1b9170c0941c3ef52ca39f54ccc (diff)
downloadlinux-94c12cc7d196bab34aaa98d38521549fa1e5ef76.tar.bz2
[S390] Inline assembly cleanup.
Major cleanup of all s390 inline assemblies. They now have a common coding style. Quite a few have been shortened, mainly by using register asm variables. Use of the EX_TABLE macro helps as well. The atomic ops, bit ops and locking inlines new use the Q-constraint if a newer gcc is used. That results in slightly better code. Thanks to Christian Borntraeger for proof reading the changes. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Diffstat (limited to 'include/asm-s390/sigp.h')
-rw-r--r--include/asm-s390/sigp.h65
1 files changed, 30 insertions, 35 deletions
diff --git a/include/asm-s390/sigp.h b/include/asm-s390/sigp.h
index fc56458aff66..e16d56f8dfe1 100644
--- a/include/asm-s390/sigp.h
+++ b/include/asm-s390/sigp.h
@@ -70,16 +70,16 @@ typedef enum
static inline sigp_ccode
signal_processor(__u16 cpu_addr, sigp_order_code order_code)
{
+ register unsigned long reg1 asm ("1") = 0;
sigp_ccode ccode;
- __asm__ __volatile__(
- " sr 1,1\n" /* parameter=0 in gpr 1 */
- " sigp 1,%1,0(%2)\n"
- " ipm %0\n"
- " srl %0,28\n"
- : "=d" (ccode)
- : "d" (__cpu_logical_map[cpu_addr]), "a" (order_code)
- : "cc" , "memory", "1" );
+ asm volatile(
+ " sigp %1,%2,0(%3)\n"
+ " ipm %0\n"
+ " srl %0,28\n"
+ : "=d" (ccode)
+ : "d" (reg1), "d" (__cpu_logical_map[cpu_addr]),
+ "a" (order_code) : "cc" , "memory");
return ccode;
}
@@ -87,20 +87,18 @@ signal_processor(__u16 cpu_addr, sigp_order_code order_code)
* Signal processor with parameter
*/
static inline sigp_ccode
-signal_processor_p(__u32 parameter, __u16 cpu_addr,
- sigp_order_code order_code)
+signal_processor_p(__u32 parameter, __u16 cpu_addr, sigp_order_code order_code)
{
+ register unsigned int reg1 asm ("1") = parameter;
sigp_ccode ccode;
-
- __asm__ __volatile__(
- " lr 1,%1\n" /* parameter in gpr 1 */
- " sigp 1,%2,0(%3)\n"
- " ipm %0\n"
- " srl %0,28\n"
+
+ asm volatile(
+ " sigp %1,%2,0(%3)\n"
+ " ipm %0\n"
+ " srl %0,28\n"
: "=d" (ccode)
- : "d" (parameter), "d" (__cpu_logical_map[cpu_addr]),
- "a" (order_code)
- : "cc" , "memory", "1" );
+ : "d" (reg1), "d" (__cpu_logical_map[cpu_addr]),
+ "a" (order_code) : "cc" , "memory");
return ccode;
}
@@ -108,24 +106,21 @@ signal_processor_p(__u32 parameter, __u16 cpu_addr,
* Signal processor with parameter and return status
*/
static inline sigp_ccode
-signal_processor_ps(__u32 *statusptr, __u32 parameter,
- __u16 cpu_addr, sigp_order_code order_code)
+signal_processor_ps(__u32 *statusptr, __u32 parameter, __u16 cpu_addr,
+ sigp_order_code order_code)
{
+ register unsigned int reg1 asm ("1") = parameter;
sigp_ccode ccode;
-
- __asm__ __volatile__(
- " sr 2,2\n" /* clear status */
- " lr 3,%2\n" /* parameter in gpr 3 */
- " sigp 2,%3,0(%4)\n"
- " st 2,%1\n"
- " ipm %0\n"
- " srl %0,28\n"
- : "=d" (ccode), "=m" (*statusptr)
- : "d" (parameter), "d" (__cpu_logical_map[cpu_addr]),
- "a" (order_code)
- : "cc" , "memory", "2" , "3"
- );
- return ccode;
+
+ asm volatile(
+ " sigp %1,%2,0(%3)\n"
+ " ipm %0\n"
+ " srl %0,28\n"
+ : "=d" (ccode), "+d" (reg1)
+ : "d" (__cpu_logical_map[cpu_addr]), "a" (order_code)
+ : "cc" , "memory");
+ *statusptr = reg1;
+ return ccode;
}
#endif /* __SIGP__ */