diff options
| author | Chris Dearman <chris@mips.com> | 2007-09-19 00:46:32 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2008-04-28 17:14:25 +0100 |
| commit | 962f480e0f9024ecdcfe2ba1d216c038ee328ced (patch) | |
| tree | 7bdc4f14bd9e894ed3178b3a9b6ec235710868a6 /include/asm-mips/pgtable-32.h | |
| parent | 0bfa130e741f8f73a7bbf6a89aad4816e9094a71 (diff) | |
| download | linux-962f480e0f9024ecdcfe2ba1d216c038ee328ced.tar.bz2 | |
[MIPS] All MIPS32 processors support64-bit physical addresses.
Still, only the 4K may actually implement it.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/pgtable-32.h')
| -rw-r--r-- | include/asm-mips/pgtable-32.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h index ceefe027c761..4396e9ffd418 100644 --- a/include/asm-mips/pgtable-32.h +++ b/include/asm-mips/pgtable-32.h @@ -107,7 +107,7 @@ static inline void pmd_clear(pmd_t *pmdp) pmd_val(*pmdp) = ((unsigned long) invalid_pte_table); } -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) #define pte_page(x) pfn_to_page(pte_pfn(x)) #define pte_pfn(x) ((unsigned long)((x).pte_high >> 6)) static inline pte_t @@ -130,7 +130,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot) #define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) #define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) #endif -#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) */ +#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */ #define __pgd_offset(address) pgd_index(address) #define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) |