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| author | Tony Luck <tony.luck@intel.com> | 2005-08-29 14:15:10 -0700 |
|---|---|---|
| committer | Tony Luck <tony.luck@intel.com> | 2005-08-29 14:15:10 -0700 |
| commit | 7115c13bd6d166982212276610b27773b8c27aec (patch) | |
| tree | 00c78ca82f738acdc6adfde7dede2689ed13b833 /include/asm-ia64 | |
| parent | 7d2e423addf3054a3238347740df6f46d4d83f3d (diff) | |
| parent | 4db8699bcfa8faddb5727b1cb010a4d9b8a42e8c (diff) | |
| download | linux-7115c13bd6d166982212276610b27773b8c27aec.tar.bz2 | |
Pull acpi-p-state into release branch
Diffstat (limited to 'include/asm-ia64')
| -rw-r--r-- | include/asm-ia64/acpi.h | 5 | ||||
| -rw-r--r-- | include/asm-ia64/pal.h | 21 |
2 files changed, 26 insertions, 0 deletions
diff --git a/include/asm-ia64/acpi.h b/include/asm-ia64/acpi.h index 4c06d455139c..3a544ffc5008 100644 --- a/include/asm-ia64/acpi.h +++ b/include/asm-ia64/acpi.h @@ -116,6 +116,11 @@ extern int __initdata nid_to_pxm_map[MAX_NUMNODES]; extern u16 ia64_acpiid_to_sapicid[]; +/* + * Refer Intel ACPI _PDC support document for bit definitions + */ +#define ACPI_PDC_EST_CAPABILITY_SMP 0x8 + #endif /*__KERNEL__*/ #endif /*_ASM_ACPI_H*/ diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h index 2303a10ee595..e828377ad295 100644 --- a/include/asm-ia64/pal.h +++ b/include/asm-ia64/pal.h @@ -75,6 +75,8 @@ #define PAL_CACHE_READ 259 /* read tag & data of cacheline for diagnostic testing */ #define PAL_CACHE_WRITE 260 /* write tag & data of cacheline for diagnostic testing */ #define PAL_VM_TR_READ 261 /* read contents of translation register */ +#define PAL_GET_PSTATE 262 /* get the current P-state */ +#define PAL_SET_PSTATE 263 /* set the P-state */ #ifndef __ASSEMBLY__ @@ -1111,6 +1113,25 @@ ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf) return iprv.status; } +/* Get the current P-state information */ +static inline s64 +ia64_pal_get_pstate (u64 *pstate_index) +{ + struct ia64_pal_retval iprv; + PAL_CALL_STK(iprv, PAL_GET_PSTATE, 0, 0, 0); + *pstate_index = iprv.v0; + return iprv.status; +} + +/* Set the P-state */ +static inline s64 +ia64_pal_set_pstate (u64 pstate_index) +{ + struct ia64_pal_retval iprv; + PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0); + return iprv.status; +} + /* Cause the processor to enter LIGHT HALT state, where prefetching and execution are * suspended, but cache and TLB coherency is maintained. */ |