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authorTakeshi Kihara <takeshi.kihara.df@renesas.com>2017-07-13 01:55:46 +0900
committerGeert Uytterhoeven <geert+renesas@glider.be>2017-07-17 11:02:40 +0200
commit78864ed5f3a743a36e9000db94709eca960efdcb (patch)
treebebccda0c38ae05ecd71dba5f9fc6150982aba92 /fs/efs
parente56c513a7a2afad84bd1eba3a361a1d6d6abf5ce (diff)
downloadlinux-78864ed5f3a743a36e9000db94709eca960efdcb.tar.bz2
pinctrl: sh-pfc: r8a7796: Fix IPSR and MOD_SEL register pin assignment for FSO pins group
This patch fixes IPSR{12,17,18} and MOD_SEL0 pin assignment for FSO pins group. This is a correction because GPSR and IPSR register specification for R8A7796 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.54E. Fixes: f9aece7344bd81ce ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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