diff options
| author | Stefan Agner <stefan@agner.ch> | 2014-03-05 23:11:08 +0100 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2014-03-06 11:34:14 +0100 |
| commit | 224aa3ed45c8735ae02bb2ecca002409fa6aa772 (patch) | |
| tree | 54f6838a6650e1ba3eb2dc6776818e2749031d20 /drivers | |
| parent | 0414855fdc4a40da05221fc6062cccbc0c30f169 (diff) | |
| download | linux-224aa3ed45c8735ae02bb2ecca002409fa6aa772.tar.bz2 | |
clocksource: vf_pit_timer: use complement for sched_clock reading
Vybrids PIT register is monitonic decreasing. However, sched_clock
reading needs to be monitonic increasing. Use bitwise not to get
the complement of the clock register. This fixes the clock going
backward. Also, the clock now starts at 0 since we load the
register with the maximum value at start.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Cc: daniel.lezcano@linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Link: http://lkml.kernel.org/r/d25af915993aec1b486be653eb86f748ddef54fe.1394057313.git.stefan@agner.ch
Cc: stable@vger.kernel.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clocksource/vf_pit_timer.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clocksource/vf_pit_timer.c b/drivers/clocksource/vf_pit_timer.c index 02821b06a39e..a918bc481c52 100644 --- a/drivers/clocksource/vf_pit_timer.c +++ b/drivers/clocksource/vf_pit_timer.c @@ -54,7 +54,7 @@ static inline void pit_irq_acknowledge(void) static u64 pit_read_sched_clock(void) { - return __raw_readl(clksrc_base + PITCVAL); + return ~__raw_readl(clksrc_base + PITCVAL); } static int __init pit_clocksource_init(unsigned long rate) |