diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-07-11 13:47:28 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-08-27 17:00:18 +0200 |
| commit | 0d2602d750152f9fcf3d9af9466f3d67b60aa646 (patch) | |
| tree | 7b543c2c57f4e3534b0730cb48918a4b6270dc7c /drivers | |
| parent | 3a251270e6c877092baded767eba07e9abb1e00d (diff) | |
| download | linux-0d2602d750152f9fcf3d9af9466f3d67b60aa646.tar.bz2 | |
clk: renesas: cpg-mssr: Add support for fixed rate clocks
Add support for defining fixed rate clocks, to be used for on-chip
oscillators.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/renesas/renesas-cpg-mssr.c | 5 | ||||
| -rw-r--r-- | drivers/clk/renesas/renesas-cpg-mssr.h | 3 |
2 files changed, 8 insertions, 0 deletions
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index f4b013e9352d..e04338932786 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -313,6 +313,11 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core, } break; + case CLK_TYPE_FR: + clk = clk_register_fixed_rate(NULL, core->name, NULL, 0, + core->mult); + break; + default: if (info->cpg_clk_register) clk = info->cpg_clk_register(dev, core, info, diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index 642f720b9b05..87bb8f368d4e 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -38,6 +38,7 @@ enum clk_types { CLK_TYPE_FF, /* Fixed Factor Clock */ CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */ CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */ + CLK_TYPE_FR, /* Fixed Rate Clock */ /* Custom definitions start here */ CLK_TYPE_CUSTOM, @@ -56,6 +57,8 @@ enum clk_types { DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset) #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1) +#define DEF_RATE(_name, _id, _rate) \ + DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate) /* * Definitions of Module Clocks |