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| author | Heiner Kallweit <hkallweit1@gmail.com> | 2019-03-22 20:00:20 +0100 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2019-03-25 17:08:21 -0700 |
| commit | d29f5aa0bc0c321e1b9e4658a2a7e08e885da52a (patch) | |
| tree | f00bbcfc3a9cba7459b1ccaca4350e0aea7850b5 /drivers | |
| parent | 27602e2c44da4091bef99e6c877e20c78b7f6e81 (diff) | |
| download | linux-d29f5aa0bc0c321e1b9e4658a2a7e08e885da52a.tar.bz2 | |
net: phy: don't clear BMCR in genphy_soft_reset
So far we effectively clear the BMCR register. Some PHY's can deal
with this (e.g. because they reset BMCR to a default as part of a
soft-reset) whilst on others this causes issues because e.g. the
autoneg bit is cleared. Marvell is an example, see also thread [0].
So let's be a little bit more gentle and leave all bits we're not
interested in as-is. This change is needed for PHY drivers to
properly deal with the original patch.
[0] https://marc.info/?t=155264050700001&r=1&w=2
Fixes: 6e2d85ec0559 ("net: phy: Stop with excessive soft reset")
Tested-by: Phil Reid <preid@electromag.com.au>
Tested-by: liweihang <liweihang@hisilicon.com>
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/phy/phy_device.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 49fdd1ee798e..77068c545de0 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -1831,7 +1831,7 @@ int genphy_soft_reset(struct phy_device *phydev) { int ret; - ret = phy_write(phydev, MII_BMCR, BMCR_RESET); + ret = phy_set_bits(phydev, MII_BMCR, BMCR_RESET); if (ret < 0) return ret; |