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authorMichael Chan <mchan@broadcom.com>2005-04-21 17:10:36 -0700
committerDavid S. Miller <davem@sunset.davemloft.net>2005-04-21 17:10:36 -0700
commit3e7d83bc96d59013792e5546e7832668d3adbce7 (patch)
treee622228e8fd43e1461ea525afa453fbcddc39125 /drivers
parentff645bec523819fa4d28d7e0de7d998e3edb0c57 (diff)
downloadlinux-3e7d83bc96d59013792e5546e7832668d3adbce7.tar.bz2
[TG3]: Add GPIO3 for 5752
Add bit definitions for the new GPIO3 in 5752. GPIO3 must be driven as output when it is unused. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/tg3.c10
-rw-r--r--drivers/net/tg3.h3
2 files changed, 13 insertions, 0 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index a4d0d61d6af0..a94631af21cd 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -5353,6 +5353,11 @@ static int tg3_reset_hw(struct tg3 *tp)
gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
+
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
+ gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
+ GRC_LCLCTRL_GPIO_OUTPUT3;
+
tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
/* GPIO1 must be driven high for eeprom write protect */
@@ -8077,6 +8082,11 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
GRC_LCLCTRL_GPIO_OUTPUT1);
+ /* Unused GPIO3 must be driven as output on 5752 because there
+ * are no pull-up resistors on unused GPIO pins.
+ */
+ else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
+ tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
/* Force the chip into D0. */
err = tg3_set_power_state(tp, 0);
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 3f7cd6fb8891..548f469e9500 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1311,6 +1311,9 @@
#define GRC_LCLCTRL_CLEARINT 0x00000002
#define GRC_LCLCTRL_SETINT 0x00000004
#define GRC_LCLCTRL_INT_ON_ATTN 0x00000008
+#define GRC_LCLCTRL_GPIO_INPUT3 0x00000020
+#define GRC_LCLCTRL_GPIO_OE3 0x00000040
+#define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080
#define GRC_LCLCTRL_GPIO_INPUT0 0x00000100
#define GRC_LCLCTRL_GPIO_INPUT1 0x00000200
#define GRC_LCLCTRL_GPIO_INPUT2 0x00000400