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authorAlexey Kardashevskiy <aik@ozlabs.ru>2015-06-05 16:35:19 +1000
committerMichael Ellerman <mpe@ellerman.id.au>2015-06-11 15:16:51 +1000
commitbbb845c4bac88d8feffa8945dd28b50849984e30 (patch)
treeca2cbb8e0df075d41dc7f200d0f7249bd91665e1 /drivers/vfio
parent43cb60ab7f8c91b9bf5988edc318dee99ec93b9b (diff)
downloadlinux-bbb845c4bac88d8feffa8945dd28b50849984e30.tar.bz2
powerpc/powernv: Implement multilevel TCE tables
TCE tables might get too big in case of 4K IOMMU pages and DDW enabled on huge guests (hundreds of GB of RAM) so the kernel might be unable to allocate contiguous chunk of physical memory to store the TCE table. To address this, POWER8 CPU (actually, IODA2) supports multi-level TCE tables, up to 5 levels which splits the table into a tree of smaller subtables. This adds multi-level TCE tables support to pnv_pci_ioda2_table_alloc_pages() and pnv_pci_ioda2_table_free_pages() helpers. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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