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authorStefan Agner <stefan@agner.ch>2018-04-20 14:44:07 +0200
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2018-04-23 09:53:36 +0200
commit0aa821d846c0590ad64a00af95a3dcc29263d70f (patch)
tree44c8369b1c4a8946bb0511613477681665658b26 /drivers/tty
parent6d215f83e5fccb3dd023e97fef1bd0029bfedde9 (diff)
downloadlinux-0aa821d846c0590ad64a00af95a3dcc29263d70f.tar.bz2
serial: imx: fix cached UCR2 read on software reset
To reset the UART the SRST needs be cleared (low active). According to the documentation the bit will remain active for 4 module clocks until it is cleared (set to 1). Hence the real register need to be read in case the cached register indicates that the SRST bit is zero. This bug lead to wrong baudrate because the baud rate register got restored before reset completed in imx_flush_buffer. Fixes: 3a0ab62f43de ("serial: imx: implement shadow registers for UCRx and UFCR") Signed-off-by: Stefan Agner <stefan@agner.ch> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/tty')
-rw-r--r--drivers/tty/serial/imx.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 65d7a2bfb6d2..c2fc6bef7a6f 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -316,7 +316,7 @@ static u32 imx_uart_readl(struct imx_port *sport, u32 offset)
* differ from the value that was last written. As it only
* clears after being set, reread conditionally.
*/
- if (sport->ucr2 & UCR2_SRST)
+ if (!(sport->ucr2 & UCR2_SRST))
sport->ucr2 = readl(sport->port.membase + offset);
return sport->ucr2;
break;