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| author | Mika Westerberg <mika.westerberg@linux.intel.com> | 2013-01-22 12:26:32 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2013-02-08 13:14:40 +0000 |
| commit | a0d2642e9296882cda3ad03ff3d9a6649cd70439 (patch) | |
| tree | 4c3f4a29ba904a357789cd7c2286eb035fa16340 /drivers/spi/spi-pxa2xx.h | |
| parent | b833172fd8f44fb56e0b3cb810155a6baecc65dc (diff) | |
| download | linux-a0d2642e9296882cda3ad03ff3d9a6649cd70439.tar.bz2 | |
spi/pxa2xx: add support for Intel Low Power Subsystem SPI
Intel LPSS SPI is pretty much the same as the PXA27xx SPI except that it
has few additional features over the original:
o FIFO depth is 256 entries
o RX FIFO has one watermark
o TX FIFO has two watermarks, low and high
o chip select can be controlled by writing to a register
The new FIFO registers follow immediately the PXA27xx registers but then there
are some additional LPSS private registers at offset 1k or 2k from the base
address. For these private registers we add new accessors that take advantage
of drv_data->lpss_base once it is resolved.
We add a new type LPSS_SSP that can be used to distinguish the LPSS devices
from others.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Tested-by: Lu Cao <lucao@marvell.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'drivers/spi/spi-pxa2xx.h')
| -rw-r--r-- | drivers/spi/spi-pxa2xx.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/spi/spi-pxa2xx.h b/drivers/spi/spi-pxa2xx.h index 97ff4717e6ac..5adc2a11c7bc 100644 --- a/drivers/spi/spi-pxa2xx.h +++ b/drivers/spi/spi-pxa2xx.h @@ -86,6 +86,8 @@ struct driver_data { int (*read)(struct driver_data *drv_data); irqreturn_t (*transfer_handler)(struct driver_data *drv_data); void (*cs_control)(u32 command); + + void __iomem *lpss_base; }; struct chip_data { @@ -97,6 +99,8 @@ struct chip_data { u32 dma_burst_size; u32 threshold; u32 dma_threshold; + u16 lpss_rx_threshold; + u16 lpss_tx_threshold; u8 enable_dma; u8 bits_per_word; u32 speed_hz; @@ -124,6 +128,8 @@ DEFINE_SSP_REG(SSITR, 0x0c) DEFINE_SSP_REG(SSDR, 0x10) DEFINE_SSP_REG(SSTO, 0x28) DEFINE_SSP_REG(SSPSP, 0x2c) +DEFINE_SSP_REG(SSITF, SSITF) +DEFINE_SSP_REG(SSIRF, SSIRF) #define START_STATE ((void *)0) #define RUNNING_STATE ((void *)1) |