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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-05-23 11:02:04 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2018-05-24 15:15:39 +0100 |
| commit | 0921e11e1e12802ae0a3c19cb02e33354ca51967 (patch) | |
| tree | 0532b6b2e20aa022f1341675d8fcc268e06bb7a5 /drivers/spi/spi-bcm-qspi.c | |
| parent | bc519d9574618e47a0c788000fb78da95e18d953 (diff) | |
| download | linux-0921e11e1e12802ae0a3c19cb02e33354ca51967.tar.bz2 | |
spi: sh-msiof: Fix setting SIRMDR1.SYNCAC to match SITMDR1.SYNCAC
According to section 59.2.4 MSIOF Receive Mode Register 1 (SIRMDR1) in
the R-Car Gen3 datasheet Rev.1.00, the value of the SIRMDR1.SYNCAC bit
must match the value of the SITMDR1.SYNCAC bit. However,
sh_msiof_spi_setup() changes only the latter.
Fix this by updating the SIRMDR1 register like the SITMDR1 register,
taking into account register bits that exist in SITMDR1 only.
Reported-by: Renesas BSP team via Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Fixes: 7ff0b53c4051145d ("spi: sh-msiof: Avoid writing to registers from spi_master.setup()")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-bcm-qspi.c')
0 files changed, 0 insertions, 0 deletions