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authorJonas Bonn <jonas@norrbonn.se>2019-01-30 09:40:05 +0100
committerMark Brown <broonie@kernel.org>2019-01-30 23:02:11 +0000
commit473a78a7bbeb7c77b81b596095f59ce4fbbd49dc (patch)
tree8e499db920a1f02fd4ac2a20f1105442c92aa64b /drivers/spi/spi-atmel.c
parentb7bb367afa4bf9de60830683305c63030c3e581d (diff)
downloadlinux-473a78a7bbeb7c77b81b596095f59ce4fbbd49dc.tar.bz2
spi-atmel: support inter-word delay
If the SPI slave requires an inter-word delay, configure the DLYBCT register accordingly. Tested on a SAMA5D2 board (derived from SAMA5D2-Xplained reference board). Signed-off-by: Jonas Bonn <jonas@norrbonn.se> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> CC: Nicolas Ferre <nicolas.ferre@microchip.com> CC: Mark Brown <broonie@kernel.org> CC: Alexandre Belloni <alexandre.belloni@bootlin.com> CC: Ludovic Desroches <ludovic.desroches@microchip.com> CC: linux-spi@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-atmel.c')
-rw-r--r--drivers/spi/spi-atmel.c11
1 files changed, 6 insertions, 5 deletions
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index f53f0c5e63da..4954f0ab1606 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -1201,13 +1201,14 @@ static int atmel_spi_setup(struct spi_device *spi)
csr |= SPI_BIT(CSAAT);
/* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
- *
- * DLYBCT would add delays between words, slowing down transfers.
- * It could potentially be useful to cope with DMA bottlenecks, but
- * in those cases it's probably best to just use a lower bitrate.
*/
csr |= SPI_BF(DLYBS, 0);
- csr |= SPI_BF(DLYBCT, 0);
+
+ /* DLYBCT adds delays between words. This is useful for slow devices
+ * that need a bit of time to setup the next transfer.
+ */
+ csr |= SPI_BF(DLYBCT,
+ (as->spi_clk / 1000000 * spi->word_delay_usecs) >> 5);
asd = spi->controller_state;
if (!asd) {