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authorDmitry Osipenko <digetx@gmail.com>2019-09-26 22:17:55 +0300
committerThierry Reding <treding@nvidia.com>2019-10-29 14:36:24 +0100
commit69dfb3d4a89afccca1d8f282e49ad1362100cc43 (patch)
tree2768bee51e3d6dd02bf4fa5669c128009e04b38d /drivers/soc
parente57a243f5d896f02510e4be92df0873b4c1aab7f (diff)
downloadlinux-69dfb3d4a89afccca1d8f282e49ad1362100cc43.tar.bz2
soc/tegra: pmc: Remove unnecessary memory barrier
The removed barrier isn't needed because writes/reads are strictly ordered and even if PMC had separate ports for writes, it wouldn't matter since the hardware logic takes into effect after triggering CPU's power-gating and at that point all CPU accesses are guaranteed to be completed. That barrier was copied from the old arch/ code during transition to the soc/ PMC driver and even that the code structure was different back then, the barrier didn't have a real useful purpose from the start. Lastly, the tegra_pmc_writel() naturally inserts wmb() because it uses writel(), and thus this change doesn't actually make any difference in terms of interacting with hardware. Hence let's remove the barrier to clean up code a tad. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/soc')
-rw-r--r--drivers/soc/tegra/pmc.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index 1f78e8497fde..8db63cfba833 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -1478,8 +1478,6 @@ void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
do_div(ticks, USEC_PER_SEC);
tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);
- wmb();
-
value = tegra_pmc_readl(pmc, PMC_CNTRL);
value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
value |= PMC_CNTRL_CPU_PWRREQ_OE;