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authorMagnus Damm <damm@opensource.se>2011-10-17 17:59:54 +0900
committerPaul Mundt <lethal@linux-sh.org>2011-10-28 14:39:24 +0900
commit52e3124f248e9ada990cd2aeafe250a53713c6f0 (patch)
tree64e89834168bc819c0c47bd01ff698acbdb12f32 /drivers/sh/intc
parenta136d3d85f2dec52df077a1d8c9728f8835ce532 (diff)
downloadlinux-52e3124f248e9ada990cd2aeafe250a53713c6f0.tar.bz2
sh: intc: Add IRQ trigger bit field check
R-Mobile SoCs such as sh73a0 include PINT blocks in INTC that come with 2-bit IRQ trigger support. Add code to make sure the bit width is checked so 4-bit only modes like for instance EDGE_BOTH will fail for PINT. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers/sh/intc')
-rw-r--r--drivers/sh/intc/chip.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/sh/intc/chip.c b/drivers/sh/intc/chip.c
index 33b2ed451e09..e0ada3773786 100644
--- a/drivers/sh/intc/chip.c
+++ b/drivers/sh/intc/chip.c
@@ -202,11 +202,16 @@ static int intc_set_type(struct irq_data *data, unsigned int type)
if (!value)
return -EINVAL;
+ value &= ~SENSE_VALID_FLAG;
+
ihp = intc_find_irq(d->sense, d->nr_sense, irq);
if (ihp) {
+ /* PINT has 2-bit sense registers, should fail on EDGE_BOTH */
+ if (value >= (1 << _INTC_WIDTH(ihp->handle)))
+ return -EINVAL;
+
addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
- intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle,
- value & ~SENSE_VALID_FLAG);
+ intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
}
return 0;