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| author | Xiang Chen <chenxiang66@hisilicon.com> | 2020-01-20 20:22:31 +0800 |
|---|---|---|
| committer | Martin K. Petersen <martin.petersen@oracle.com> | 2020-01-20 19:31:13 -0500 |
| commit | 81f338e9709db0b67d05bab02809d6a4e6694884 (patch) | |
| tree | ae10d8b3d29bce523d21651f06b4db5d85d4d63e /drivers/scsi/gdth.h | |
| parent | 1baa80118e0324bf5063c2576b531a14cb57f874 (diff) | |
| download | linux-81f338e9709db0b67d05bab02809d6a4e6694884.tar.bz2 | |
scsi: hisi_sas: use threaded irq to process CQ interrupts
Currently IRQ_EFFECTIVE_AFF_MASK is enabled for ARM_GIC and ARM_GIC3, so it
only allows a single target CPU in the affinity mask to process interrupts
and also interrupt thread, and the performance of using threaded irq is
almost the same as tasklet. But if the config is not enabled, the interrupt
thread will be allowed all the CPUs in the affinity mask. At that situation
it improves the performance (about 20%).
Note: IRQ_EFFECTIVE_AFF_MASK is configured differently for different
architecture chip, and it seems to be better to make it be configured
easily.
Link: https://lore.kernel.org/r/1579522957-4393-2-git-send-email-john.garry@huawei.com
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'drivers/scsi/gdth.h')
0 files changed, 0 insertions, 0 deletions