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authorRadhakrishna Sripada <radhakrishna.sripada@intel.com>2020-01-09 14:37:27 -0800
committerMatt Roper <matthew.d.roper@intel.com>2020-01-15 08:29:07 -0800
commitf78d5da6e7bd500df734bd1d5260f99ceee9d01f (patch)
tree0cab92a14b3a4ecfbf3f7f61272dd03040768f10 /drivers/rpmsg
parentd54151c5c8c08e2cbb88d62643a9c9c8d9e5f367 (diff)
downloadlinux-f78d5da6e7bd500df734bd1d5260f99ceee9d01f.tar.bz2
drm/i915/tgl: Add Wa_1409825376 to tgl
Workaround database indicates we should disable VRH clockgating in pre-production hardware. V2: - Use REG_BIT macro - Update reference in commit message(Matt) Bspec: 52890 Bspec: 49424 Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200109223727.5630-1-radhakrishna.sripada@intel.com
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