diff options
| author | Claudiu Beznea <claudiu.beznea@microchip.com> | 2019-02-25 16:44:37 +0000 |
|---|---|---|
| committer | Thierry Reding <thierry.reding@gmail.com> | 2019-03-04 11:56:08 +0100 |
| commit | 0285827d546d9087aadce6d3728dd824e32e3777 (patch) | |
| tree | 3a6f13df3e9fe0ec8901de9402321afde26efc79 /drivers/pwm | |
| parent | 53784159f6f513dcb5a8f61503312c9c2f57eeb6 (diff) | |
| download | linux-0285827d546d9087aadce6d3728dd824e32e3777.tar.bz2 | |
pwm: atmel: Add support for controllers with 32 bit counters
SAM9X60's PWM controller uses 32 bits counters thus it could generate
signals with higher period and duty cycles than the old ones. Prepare
the current driver to be able to work with old controllers (that uses
16 bits counters) and with the new SAM9X60's controller, by providing
counters information based on compatible string.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Diffstat (limited to 'drivers/pwm')
| -rw-r--r-- | drivers/pwm/pwm-atmel.c | 34 |
1 files changed, 23 insertions, 11 deletions
diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c index 7e86a5266eb6..647d063562db 100644 --- a/drivers/pwm/pwm-atmel.c +++ b/drivers/pwm/pwm-atmel.c @@ -48,15 +48,11 @@ #define PWMV2_CPRD 0x0C #define PWMV2_CPRDUPD 0x10 -/* - * Max value for duty and period - * - * Although the duty and period register is 32 bit, - * however only the LSB 16 bits are significant. - */ -#define PWM_MAX_DTY 0xFFFF -#define PWM_MAX_PRD 0xFFFF -#define PRD_MAX_PRES 10 +/* Max values for period and prescaler */ + +/* Only the LSB 16 bits are significant. */ +#define PWM_MAXV1_PRD 0xFFFF +#define PRD_MAXV1_PRES 10 struct atmel_pwm_registers { u8 period; @@ -65,8 +61,14 @@ struct atmel_pwm_registers { u8 duty_upd; }; +struct atmel_pwm_config { + u32 max_period; + u32 max_pres; +}; + struct atmel_pwm_data { struct atmel_pwm_registers regs; + struct atmel_pwm_config cfg; }; struct atmel_pwm_chip { @@ -125,10 +127,10 @@ static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip, cycles *= clk_get_rate(atmel_pwm->clk); do_div(cycles, NSEC_PER_SEC); - for (*pres = 0; cycles > PWM_MAX_PRD; cycles >>= 1) + for (*pres = 0; cycles > atmel_pwm->data->cfg.max_period; cycles >>= 1) (*pres)++; - if (*pres > PRD_MAX_PRES) { + if (*pres > atmel_pwm->data->cfg.max_pres) { dev_err(chip->dev, "pres exceeds the maximum value\n"); return -EINVAL; } @@ -288,6 +290,11 @@ static const struct atmel_pwm_data atmel_pwm_data_v1 = { .duty = PWMV1_CDTY, .duty_upd = PWMV1_CUPD, }, + .cfg = { + /* 16 bits to keep period and duty. */ + .max_period = PWM_MAXV1_PRD, + .max_pres = PRD_MAXV1_PRES, + }, }; static const struct atmel_pwm_data atmel_pwm_data_v2 = { @@ -297,6 +304,11 @@ static const struct atmel_pwm_data atmel_pwm_data_v2 = { .duty = PWMV2_CDTY, .duty_upd = PWMV2_CDTYUPD, }, + .cfg = { + /* 16 bits to keep period and duty. */ + .max_period = PWM_MAXV1_PRD, + .max_pres = PRD_MAXV1_PRES, + }, }; static const struct platform_device_id atmel_pwm_devtypes[] = { |