diff options
| author | Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> | 2016-10-07 16:01:12 +0530 |
|---|---|---|
| committer | Darren Hart <dvhart@linux.intel.com> | 2016-12-13 09:28:54 -0800 |
| commit | 8434709ba71473f75572245c247d3c1e92509cf3 (patch) | |
| tree | c3b7e8a3f3fbecf9a9d4f028647c76b91c46d091 /drivers/platform | |
| parent | 5241b1938a4d33eee3d3b43f23067c8e5b96db45 (diff) | |
| download | linux-8434709ba71473f75572245c247d3c1e92509cf3.tar.bz2 | |
platform/x86: intel_pmc_core: Fix PWRMBASE mask and mmio reg len
On Sunrise Point PCH, the Power Management Controller provides 4K bytes of
memory space for various power management and debug registers. This fix is
needed to access power management & debug registers that are mapped at a
higher offset.
Also, this provides a fix for correctly masking the PWRMBASE as the initial
bits (0-11) are reserved.
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
Diffstat (limited to 'drivers/platform')
| -rw-r--r-- | drivers/platform/x86/intel_pmc_core.c | 1 | ||||
| -rw-r--r-- | drivers/platform/x86/intel_pmc_core.h | 3 |
2 files changed, 3 insertions, 1 deletions
diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index e8b1b836ca2d..5774882a5300 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -149,6 +149,7 @@ static int pmc_core_probe(struct pci_dev *dev, const struct pci_device_id *id) dev_dbg(&dev->dev, "PMC Core: failed to read PCI config space.\n"); return err; } + pmcdev->base_addr &= PMC_BASE_ADDR_MASK; dev_dbg(&dev->dev, "PMC Core: PWRMBASE is %#x\n", pmcdev->base_addr); pmcdev->regbase = devm_ioremap_nocache(ptr_dev, diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h index e3f671f4d122..cde31ec02266 100644 --- a/drivers/platform/x86/intel_pmc_core.h +++ b/drivers/platform/x86/intel_pmc_core.h @@ -26,8 +26,9 @@ #define SPT_PMC_BASE_ADDR_OFFSET 0x48 #define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET 0x13c -#define SPT_PMC_MMIO_REG_LEN 0x100 +#define SPT_PMC_MMIO_REG_LEN 0x1000 #define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x64 +#define PMC_BASE_ADDR_MASK ~(SPT_PMC_MMIO_REG_LEN - 1) /** * struct pmc_dev - pmc device structure |