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authorLinus Torvalds <torvalds@linux-foundation.org>2018-04-03 12:20:54 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2018-04-03 12:20:54 -0700
commit77624cd2a7783fccf2c518768a6fd7a7aeccd002 (patch)
tree406283e54084299dc83f8c5456375941ed5dd67a /drivers/pinctrl
parentdc73d6a8d42d208c027b4bcca59a77d045895977 (diff)
parent4fc97ef94bbfa185d16b3e44199b7559d0668747 (diff)
downloadlinux-77624cd2a7783fccf2c518768a6fd7a7aeccd002.tar.bz2
Merge tag 'pinctrl-v4.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control bulk updates from Linus Walleij: "New drivers: - Qualcomm SDM845: this is their new flagship SoC platform which seems to be targeted at premium mobile handsets. - Renesas R-Car M3-N SoC. - Renesas R8A77980 SoC. - NXP (ex Freescale) i.MX 6SLL SoC. - Mediatek MT2712 SoC. - Allwinner H6 SoC. Improvements: - Uniphier adds a few new functions and pins. - Renesas refactorings and additional pin definitions. - Improved pin groups for Axis Artpec6. Cleanup: - Drop the TZ1090 drivers. This platform is no longer maintained and is being deleted. - Drop ST-Ericsson U8540/U9540 support as this was never productified. - Overall minor fixes and janitorial" * tag 'pinctrl-v4.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (82 commits) pinctrl: uniphier: add UART hardware flow control pin-mux settings pinctrl: sunxi: add support for the Allwinner H6 main pin controller pinctrl: sunxi: change irq_bank_base to irq_bank_map pinctrl: sunxi: introduce IRQ bank conversion function pinctrl: sunxi: refactor irq related register function to have desc pinctrl: msm8998: Remove owner assignment from platform_driver pinctrl: uniphier: divide I2S and S/PDIF audio out pin-mux group pinctrl: uniphier: add PXs2 Audio in/out pin-mux settings pinctrl/amd: poll InterruptEnable bits in enable_irq pinctrl: ocelot: fix gpio direction pinctrl: mtk: fix check warnings. pintcrl: mtk: support bias-disable of generic and special pins simultaneously pinctrl: add mt2712 pinctrl driver pinctrl: pinctrl-single: Fix pcs_request_gpio() when bits_per_mux != 0 pinctrl: imx: Add pinctrl driver support for imx6sll dt-bindings: imx: update pinctrl doc for imx6sll pinctrl: intel: Implement intel_gpio_get_direction callback pinctrl: stm32: add 'depends on HAS_IOMEM' to fix unmet dependency pinctrl: mediatek: mtk-common: use true and false for boolean values pinctrl: sunxi: always look for apb block ...
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/Kconfig12
-rw-r--r--drivers/pinctrl/Makefile2
-rw-r--r--drivers/pinctrl/core.c109
-rw-r--r--drivers/pinctrl/devicetree.c6
-rw-r--r--drivers/pinctrl/freescale/Kconfig7
-rw-r--r--drivers/pinctrl/freescale/Makefile1
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx6sll.c360
-rw-r--r--drivers/pinctrl/intel/pinctrl-intel.c19
-rw-r--r--drivers/pinctrl/mediatek/Kconfig7
-rw-r--r--drivers/pinctrl/mediatek/Makefile1
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mt2712.c633
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-common.c12
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h840
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h1757
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h123
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h429
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h609
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-mt8173.h405
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson8b.c20
-rw-r--r--drivers/pinctrl/nomadik/Kconfig12
-rw-r--r--drivers/pinctrl/nomadik/Makefile3
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-ab8540.c408
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-ab9540.c486
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-abx500.c197
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-abx500.h44
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-nomadik-db8540.c1243
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c16
-rw-r--r--drivers/pinctrl/pinctrl-amd.c23
-rw-r--r--drivers/pinctrl/pinctrl-artpec6.c66
-rw-r--r--drivers/pinctrl/pinctrl-mcp23s08.c54
-rw-r--r--drivers/pinctrl/pinctrl-ocelot.c4
-rw-r--r--drivers/pinctrl/pinctrl-single.c22
-rw-r--r--drivers/pinctrl/pinctrl-tz1090-pdc.c989
-rw-r--r--drivers/pinctrl/pinctrl-tz1090.c2005
-rw-r--r--drivers/pinctrl/qcom/Kconfig9
-rw-r--r--drivers/pinctrl/qcom/Makefile1
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm8998.c1
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sdm845.c1323
-rw-r--r--drivers/pinctrl/sh-pfc/Kconfig10
-rw-r--r--drivers/pinctrl/sh-pfc/Makefile2
-rw-r--r--drivers/pinctrl/sh-pfc/core.c12
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7790.c8
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c82
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7795.c410
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7796.c415
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a77965.c3243
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a77970.c98
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a77980.c2799
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a77995.c221
-rw-r--r--drivers/pinctrl/sh-pfc/pinctrl.c2
-rw-r--r--drivers/pinctrl/sh-pfc/sh_pfc.h15
-rw-r--r--drivers/pinctrl/stm32/Kconfig12
-rw-r--r--drivers/pinctrl/stm32/pinctrl-stm32.c3
-rw-r--r--drivers/pinctrl/sunxi/Kconfig4
-rw-r--r--drivers/pinctrl/sunxi/Makefile1
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c614
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c4
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c4
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi.c25
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi.h40
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c20
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c20
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c5
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c5
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c5
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c5
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c40
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c5
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c5
70 files changed, 13148 insertions, 7246 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 008073570a38..01fe8e0455a0 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -244,18 +244,6 @@ config PINCTRL_ST
select PINCONF
select GPIOLIB_IRQCHIP
-config PINCTRL_TZ1090
- bool "Toumaz Xenif TZ1090 pin control driver"
- depends on SOC_TZ1090
- select PINMUX
- select GENERIC_PINCONF
-
-config PINCTRL_TZ1090_PDC
- bool "Toumaz Xenif TZ1090 PDC pin control driver"
- depends on SOC_TZ1090
- select PINMUX
- select PINCONF
-
config PINCTRL_U300
bool "U300 pin controller driver"
depends on ARCH_U300
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 92a40bdb6273..657332b121fb 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -31,8 +31,6 @@ obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_SIRF) += sirf/
obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o
obj-$(CONFIG_ARCH_TEGRA) += tegra/
-obj-$(CONFIG_PINCTRL_TZ1090) += pinctrl-tz1090.o
-obj-$(CONFIG_PINCTRL_TZ1090_PDC) += pinctrl-tz1090-pdc.o
obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index 2c0dbfcff3e6..e5a303002021 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -1416,6 +1416,7 @@ int pinctrl_register_mappings(const struct pinctrl_map *maps,
{
return pinctrl_register_map(maps, num_maps, true);
}
+EXPORT_SYMBOL_GPL(pinctrl_register_mappings);
void pinctrl_unregister_map(const struct pinctrl_map *map)
{
@@ -1586,6 +1587,7 @@ static int pinctrl_pins_show(struct seq_file *s, void *what)
return 0;
}
+DEFINE_SHOW_ATTRIBUTE(pinctrl_pins);
static int pinctrl_groups_show(struct seq_file *s, void *what)
{
@@ -1631,6 +1633,7 @@ static int pinctrl_groups_show(struct seq_file *s, void *what)
return 0;
}
+DEFINE_SHOW_ATTRIBUTE(pinctrl_groups);
static int pinctrl_gpioranges_show(struct seq_file *s, void *what)
{
@@ -1664,6 +1667,7 @@ static int pinctrl_gpioranges_show(struct seq_file *s, void *what)
return 0;
}
+DEFINE_SHOW_ATTRIBUTE(pinctrl_gpioranges);
static int pinctrl_devices_show(struct seq_file *s, void *what)
{
@@ -1690,6 +1694,7 @@ static int pinctrl_devices_show(struct seq_file *s, void *what)
return 0;
}
+DEFINE_SHOW_ATTRIBUTE(pinctrl_devices);
static inline const char *map_type(enum pinctrl_map_type type)
{
@@ -1743,6 +1748,7 @@ static int pinctrl_maps_show(struct seq_file *s, void *what)
return 0;
}
+DEFINE_SHOW_ATTRIBUTE(pinctrl_maps);
static int pinctrl_show(struct seq_file *s, void *what)
{
@@ -1788,87 +1794,30 @@ static int pinctrl_show(struct seq_file *s, void *what)
return 0;
}
-
-static int pinctrl_pins_open(struct inode *inode, struct file *file)
-{
- return single_open(file, pinctrl_pins_show, inode->i_private);
-}
-
-static int pinctrl_groups_open(struct inode *inode, struct file *file)
-{
- return single_open(file, pinctrl_groups_show, inode->i_private);
-}
-
-static int pinctrl_gpioranges_open(struct inode *inode, struct file *file)
-{
- return single_open(file, pinctrl_gpioranges_show, inode->i_private);
-}
-
-static int pinctrl_devices_open(struct inode *inode, struct file *file)
-{
- return single_open(file, pinctrl_devices_show, NULL);
-}
-
-static int pinctrl_maps_open(struct inode *inode, struct file *file)
-{
- return single_open(file, pinctrl_maps_show, NULL);
-}
-
-static int pinctrl_open(struct inode *inode, struct file *file)
-{
- return single_open(file, pinctrl_show, NULL);
-}
-
-static const struct file_operations pinctrl_pins_ops = {
- .open = pinctrl_pins_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static const struct file_operations pinctrl_groups_ops = {
- .open = pinctrl_groups_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static const struct file_operations pinctrl_gpioranges_ops = {
- .open = pinctrl_gpioranges_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static const struct file_operations pinctrl_devices_ops = {
- .open = pinctrl_devices_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static const struct file_operations pinctrl_maps_ops = {
- .open = pinctrl_maps_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static const struct file_operations pinctrl_ops = {
- .open = pinctrl_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
+DEFINE_SHOW_ATTRIBUTE(pinctrl);
static struct dentry *debugfs_root;
static void pinctrl_init_device_debugfs(struct pinctrl_dev *pctldev)
{
struct dentry *device_root;
+ const char *debugfs_name;
+
+ if (pctldev->desc->name &&
+ strcmp(dev_name(pctldev->dev), pctldev->desc->name)) {
+ debugfs_name = devm_kasprintf(pctldev->dev, GFP_KERNEL,
+ "%s-%s", dev_name(pctldev->dev),
+ pctldev->desc->name);
+ if (!debugfs_name) {
+ pr_warn("failed to determine debugfs dir name for %s\n",
+ dev_name(pctldev->dev));
+ return;
+ }
+ } else {
+ debugfs_name = dev_name(pctldev->dev);
+ }
- device_root = debugfs_create_dir(dev_name(pctldev->dev),
- debugfs_root);
+ device_root = debugfs_create_dir(debugfs_name, debugfs_root);
pctldev->device_root = device_root;
if (IS_ERR(device_root) || !device_root) {
@@ -1877,11 +1826,11 @@ static void pinctrl_init_device_debugfs(struct pinctrl_dev *pctldev)
return;
}
debugfs_create_file("pins", S_IFREG | S_IRUGO,
- device_root, pctldev, &pinctrl_pins_ops);
+ device_root, pctldev, &pinctrl_pins_fops);
debugfs_create_file("pingroups", S_IFREG | S_IRUGO,
- device_root, pctldev, &pinctrl_groups_ops);
+ device_root, pctldev, &pinctrl_groups_fops);
debugfs_create_file("gpio-ranges", S_IFREG | S_IRUGO,
- device_root, pctldev, &pinctrl_gpioranges_ops);
+ device_root, pctldev, &pinctrl_gpioranges_fops);
if (pctldev->desc->pmxops)
pinmux_init_device_debugfs(device_root, pctldev);
if (pctldev->desc->confops)
@@ -1903,11 +1852,11 @@ static void pinctrl_init_debugfs(void)
}
debugfs_create_file("pinctrl-devices", S_IFREG | S_IRUGO,
- debugfs_root, NULL, &pinctrl_devices_ops);
+ debugfs_root, NULL, &pinctrl_devices_fops);
debugfs_create_file("pinctrl-maps", S_IFREG | S_IRUGO,
- debugfs_root, NULL, &pinctrl_maps_ops);
+ debugfs_root, NULL, &pinctrl_maps_fops);
debugfs_create_file("pinctrl-handles", S_IFREG | S_IRUGO,
- debugfs_root, NULL, &pinctrl_ops);
+ debugfs_root, NULL, &pinctrl_fops);
}
#else /* CONFIG_DEBUG_FS */
diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c
index 1ff6c3573493..b601039d6c69 100644
--- a/drivers/pinctrl/devicetree.c
+++ b/drivers/pinctrl/devicetree.c
@@ -122,8 +122,10 @@ static int dt_to_map_one_config(struct pinctrl *p,
/* OK let's just assume this will appear later then */
return -EPROBE_DEFER;
}
- if (!pctldev)
- pctldev = get_pinctrl_dev_from_of_node(np_pctldev);
+ /* If we're creating a hog we can use the passed pctldev */
+ if (pctldev && (np_pctldev == p->dev->of_node))
+ break;
+ pctldev = get_pinctrl_dev_from_of_node(np_pctldev);
if (pctldev)
break;
/* Do not defer probing of hogs (circular loop) */
diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
index 4dbc576ae27c..0d8ba1ef5329 100644
--- a/drivers/pinctrl/freescale/Kconfig
+++ b/drivers/pinctrl/freescale/Kconfig
@@ -82,6 +82,13 @@ config PINCTRL_IMX6SL
help
Say Y here to enable the imx6sl pinctrl driver
+config PINCTRL_IMX6SLL
+ bool "IMX6SLL pinctrl driver"
+ depends on SOC_IMX6SLL
+ select PINCTRL_IMX
+ help
+ Say Y here to enable the imx6sll pinctrl driver
+
config PINCTRL_IMX6SX
bool "IMX6SX pinctrl driver"
depends on SOC_IMX6SX
diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile
index 19bb9a55a567..368be8cfc9b1 100644
--- a/drivers/pinctrl/freescale/Makefile
+++ b/drivers/pinctrl/freescale/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o
obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o
+obj-$(CONFIG_PINCTRL_IMX6SLL) += pinctrl-imx6sll.o
obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o
obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6sll.c b/drivers/pinctrl/freescale/pinctrl-imx6sll.c
new file mode 100644
index 000000000000..0fbea9cf536d
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-imx6sll.c
@@ -0,0 +1,360 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP.
+ *
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+enum imx6sll_pads {
+ MX6SLL_PAD_RESERVE0 = 0,
+ MX6SLL_PAD_RESERVE1 = 1,
+ MX6SLL_PAD_RESERVE2 = 2,
+ MX6SLL_PAD_RESERVE3 = 3,
+ MX6SLL_PAD_RESERVE4 = 4,
+ MX6SLL_PAD_WDOG_B = 5,
+ MX6SLL_PAD_REF_CLK_24M = 6,
+ MX6SLL_PAD_REF_CLK_32K = 7,
+ MX6SLL_PAD_PWM1 = 8,
+ MX6SLL_PAD_KEY_COL0 = 9,
+ MX6SLL_PAD_KEY_ROW0 = 10,
+ MX6SLL_PAD_KEY_COL1 = 11,
+ MX6SLL_PAD_KEY_ROW1 = 12,
+ MX6SLL_PAD_KEY_COL2 = 13,
+ MX6SLL_PAD_KEY_ROW2 = 14,
+ MX6SLL_PAD_KEY_COL3 = 15,
+ MX6SLL_PAD_KEY_ROW3 = 16,
+ MX6SLL_PAD_KEY_COL4 = 17,
+ MX6SLL_PAD_KEY_ROW4 = 18,
+ MX6SLL_PAD_KEY_COL5 = 19,
+ MX6SLL_PAD_KEY_ROW5 = 20,
+ MX6SLL_PAD_KEY_COL6 = 21,
+ MX6SLL_PAD_KEY_ROW6 = 22,
+ MX6SLL_PAD_KEY_COL7 = 23,
+ MX6SLL_PAD_KEY_ROW7 = 24,
+ MX6SLL_PAD_EPDC_DATA00 = 25,
+ MX6SLL_PAD_EPDC_DATA01 = 26,
+ MX6SLL_PAD_EPDC_DATA02 = 27,
+ MX6SLL_PAD_EPDC_DATA03 = 28,
+ MX6SLL_PAD_EPDC_DATA04 = 29,
+ MX6SLL_PAD_EPDC_DATA05 = 30,
+ MX6SLL_PAD_EPDC_DATA06 = 31,
+ MX6SLL_PAD_EPDC_DATA07 = 32,
+ MX6SLL_PAD_EPDC_DATA08 = 33,
+ MX6SLL_PAD_EPDC_DATA09 = 34,
+ MX6SLL_PAD_EPDC_DATA10 = 35,
+ MX6SLL_PAD_EPDC_DATA11 = 36,
+ MX6SLL_PAD_EPDC_DATA12 = 37,
+ MX6SLL_PAD_EPDC_DATA13 = 38,
+ MX6SLL_PAD_EPDC_DATA14 = 39,
+ MX6SLL_PAD_EPDC_DATA15 = 40,
+ MX6SLL_PAD_EPDC_SDCLK = 41,
+ MX6SLL_PAD_EPDC_SDLE = 42,
+ MX6SLL_PAD_EPDC_SDOE = 43,
+ MX6SLL_PAD_EPDC_SDSHR = 44,
+ MX6SLL_PAD_EPDC_SDCE0 = 45,
+ MX6SLL_PAD_EPDC_SDCE1 = 46,
+ MX6SLL_PAD_EPDC_SDCE2 = 47,
+ MX6SLL_PAD_EPDC_SDCE3 = 48,
+ MX6SLL_PAD_EPDC_GDCLK = 49,
+ MX6SLL_PAD_EPDC_GDOE = 50,
+ MX6SLL_PAD_EPDC_GDRL = 51,
+ MX6SLL_PAD_EPDC_GDSP = 52,
+ MX6SLL_PAD_EPDC_VCOM0 = 53,
+ MX6SLL_PAD_EPDC_VCOM1 = 54,
+ MX6SLL_PAD_EPDC_BDR0 = 55,
+ MX6SLL_PAD_EPDC_BDR1 = 56,
+ MX6SLL_PAD_EPDC_PWR_CTRL0 = 57,
+ MX6SLL_PAD_EPDC_PWR_CTRL1 = 58,
+ MX6SLL_PAD_EPDC_PWR_CTRL2 = 59,
+ MX6SLL_PAD_EPDC_PWR_CTRL3 = 60,
+ MX6SLL_PAD_EPDC_PWR_COM = 61,
+ MX6SLL_PAD_EPDC_PWR_INT = 62,
+ MX6SLL_PAD_EPDC_PWR_STAT = 63,
+ MX6SLL_PAD_EPDC_PWR_WAKE = 64,
+ MX6SLL_PAD_LCD_CLK = 65,
+ MX6SLL_PAD_LCD_ENABLE = 66,
+ MX6SLL_PAD_LCD_HSYNC = 67,
+ MX6SLL_PAD_LCD_VSYNC = 68,
+ MX6SLL_PAD_LCD_RESET = 69,
+ MX6SLL_PAD_LCD_DATA00 = 70,
+ MX6SLL_PAD_LCD_DATA01 = 71,
+ MX6SLL_PAD_LCD_DATA02 = 72,
+ MX6SLL_PAD_LCD_DATA03 = 73,
+ MX6SLL_PAD_LCD_DATA04 = 74,
+ MX6SLL_PAD_LCD_DATA05 = 75,
+ MX6SLL_PAD_LCD_DATA06 = 76,
+ MX6SLL_PAD_LCD_DATA07 = 77,
+ MX6SLL_PAD_LCD_DATA08 = 78,
+ MX6SLL_PAD_LCD_DATA09 = 79,
+ MX6SLL_PAD_LCD_DATA10 = 80,
+ MX6SLL_PAD_LCD_DATA11 = 81,
+ MX6SLL_PAD_LCD_DATA12 = 82,
+ MX6SLL_PAD_LCD_DATA13 = 83,
+ MX6SLL_PAD_LCD_DATA14 = 84,
+ MX6SLL_PAD_LCD_DATA15 = 85,
+ MX6SLL_PAD_LCD_DATA16 = 86,
+ MX6SLL_PAD_LCD_DATA17 = 87,
+ MX6SLL_PAD_LCD_DATA18 = 88,
+ MX6SLL_PAD_LCD_DATA19 = 89,
+ MX6SLL_PAD_LCD_DATA20 = 90,
+ MX6SLL_PAD_LCD_DATA21 = 91,
+ MX6SLL_PAD_LCD_DATA22 = 92,
+ MX6SLL_PAD_LCD_DATA23 = 93,
+ MX6SLL_PAD_AUD_RXFS = 94,
+ MX6SLL_PAD_AUD_RXC = 95,
+ MX6SLL_PAD_AUD_RXD = 96,
+ MX6SLL_PAD_AUD_TXC = 97,
+ MX6SLL_PAD_AUD_TXFS = 98,
+ MX6SLL_PAD_AUD_TXD = 99,
+ MX6SLL_PAD_AUD_MCLK = 100,
+ MX6SLL_PAD_UART1_RXD = 101,
+ MX6SLL_PAD_UART1_TXD = 102,
+ MX6SLL_PAD_I2C1_SCL = 103,
+ MX6SLL_PAD_I2C1_SDA = 104,
+ MX6SLL_PAD_I2C2_SCL = 105,
+ MX6SLL_PAD_I2C2_SDA = 106,
+ MX6SLL_PAD_ECSPI1_SCLK = 107,
+ MX6SLL_PAD_ECSPI1_MOSI = 108,
+ MX6SLL_PAD_ECSPI1_MISO = 109,
+ MX6SLL_PAD_ECSPI1_SS0 = 110,
+ MX6SLL_PAD_ECSPI2_SCLK = 111,
+ MX6SLL_PAD_ECSPI2_MOSI = 112,
+ MX6SLL_PAD_ECSPI2_MISO = 113,
+ MX6SLL_PAD_ECSPI2_SS0 = 114,
+ MX6SLL_PAD_SD1_CLK = 115,
+ MX6SLL_PAD_SD1_CMD = 116,
+ MX6SLL_PAD_SD1_DATA0 = 117,
+ MX6SLL_PAD_SD1_DATA1 = 118,
+ MX6SLL_PAD_SD1_DATA2 = 119,
+ MX6SLL_PAD_SD1_DATA3 = 120,
+ MX6SLL_PAD_SD1_DATA4 = 121,
+ MX6SLL_PAD_SD1_DATA5 = 122,
+ MX6SLL_PAD_SD1_DATA6 = 123,
+ MX6SLL_PAD_SD1_DATA7 = 124,
+ MX6SLL_PAD_SD2_RESET = 125,
+ MX6SLL_PAD_SD2_CLK = 126,
+ MX6SLL_PAD_SD2_CMD = 127,
+ MX6SLL_PAD_SD2_DATA0 = 128,
+ MX6SLL_PAD_SD2_DATA1 = 129,
+ MX6SLL_PAD_SD2_DATA2 = 130,
+ MX6SLL_PAD_SD2_DATA3 = 131,
+ MX6SLL_PAD_SD2_DATA4 = 132,
+ MX6SLL_PAD_SD2_DATA5 = 133,
+ MX6SLL_PAD_SD2_DATA6 = 134,
+ MX6SLL_PAD_SD2_DATA7 = 135,
+ MX6SLL_PAD_SD3_CLK = 136,
+ MX6SLL_PAD_SD3_CMD = 137,
+ MX6SLL_PAD_SD3_DATA0 = 138,
+ MX6SLL_PAD_SD3_DATA1 = 139,
+ MX6SLL_PAD_SD3_DATA2 = 140,
+ MX6SLL_PAD_SD3_DATA3 = 141,
+ MX6SLL_PAD_GPIO4_IO20 = 142,
+ MX6SLL_PAD_GPIO4_IO21 = 143,
+ MX6SLL_PAD_GPIO4_IO19 = 144,
+ MX6SLL_PAD_GPIO4_IO25 = 145,
+ MX6SLL_PAD_GPIO4_IO18 = 146,
+ MX6SLL_PAD_GPIO4_IO24 = 147,
+ MX6SLL_PAD_GPIO4_IO23 = 148,
+ MX6SLL_PAD_GPIO4_IO17 = 149,
+ MX6SLL_PAD_GPIO4_IO22 = 150,
+ MX6SLL_PAD_GPIO4_IO16 = 151,
+ MX6SLL_PAD_GPIO4_IO26 = 152,
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx6sll_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE0),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE1),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE2),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE3),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE4),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_WDOG_B),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_REF_CLK_24M),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_REF_CLK_32K),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_PWM1),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL0),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW0),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL1),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW1),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL2),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW2),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL3),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW3),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL4),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW4),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL5),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW5),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL6),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW6),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL7),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW7),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA00),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA01),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA02),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA03),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA04),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA05),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA06),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA07),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA08),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA09),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA10),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA11),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA12),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA13),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA14),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA15),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCLK),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDLE),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDOE),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDSHR),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE0),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE1),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE2),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE3),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDCLK),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDOE),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDRL),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDSP),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_VCOM0),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_VCOM1),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_BDR0),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_BDR1),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL0),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL1),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL2),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL3),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_COM),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_INT),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_STAT),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_WAKE),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_CLK),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_ENABLE),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_HSYNC),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_VSYNC),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_RESET),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA00),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA01),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA02),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA03),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA04),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA05),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA06),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA07),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA08),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA09),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA10),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA11),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA12),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA13),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA14),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA15),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA16),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA17),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA18),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA19),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA20),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA21),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA22),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA23),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXFS),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXC),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXD),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXC),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXFS),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXD),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_MCLK),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_UART1_RXD),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_UART1_TXD),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_I2C1_SCL),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_I2C1_SDA),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_I2C2_SCL),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_I2C2_SDA),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_SCLK),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_MOSI),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_MISO),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_SS0),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_SCLK),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_MOSI),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_MISO),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_SS0),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_CLK),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_CMD),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA0),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA1),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA2),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA3),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA4),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA5),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA6),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA7),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_RESET),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_CLK),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_CMD),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA0),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA1),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA2),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA3),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA4),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA5),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA6),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA7),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_CLK),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_CMD),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA0),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA1),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA2),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA3),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO20),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO21),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO19),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO25),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO18),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO24),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO23),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO17),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO22),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO16),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO26),
+};
+
+static const struct imx_pinctrl_soc_info imx6sll_pinctrl_info = {
+ .pins = imx6sll_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx6sll_pinctrl_pads),
+ .gpr_compatible = "fsl,imx6sll-iomuxc-gpr",
+};
+
+static const struct of_device_id imx6sll_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx6sll-iomuxc", .data = &imx6sll_pinctrl_info, },
+ { /* sentinel */ }
+};
+
+static int imx6sll_pinctrl_probe(struct platform_device *pdev)
+{
+ return imx_pinctrl_probe(pdev, &imx6sll_pinctrl_info);
+}
+
+static struct platform_driver imx6sll_pinctrl_driver = {
+ .driver = {
+ .name = "imx6sll-pinctrl",
+ .of_match_table = of_match_ptr(imx6sll_pinctrl_of_match),
+ .suppress_bind_attrs = true,
+ },
+ .probe = imx6sll_pinctrl_probe,
+};
+
+static int __init imx6sll_pinctrl_init(void)
+{
+ return platform_driver_register(&imx6sll_pinctrl_driver);
+}
+arch_initcall(imx6sll_pinctrl_init);
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index 96e73e30204e..1e24a6b8a64e 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -788,6 +788,24 @@ static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
+static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
+{
+ struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
+ void __iomem *reg;
+ u32 padcfg0;
+
+ reg = intel_get_padcfg(pctrl, offset, PADCFG0);
+ if (!reg)
+ return -EINVAL;
+
+ padcfg0 = readl(reg);
+
+ if (padcfg0 & PADCFG0_PMODE_MASK)
+ return -EINVAL;
+
+ return !!(padcfg0 & PADCFG0_GPIOTXDIS);
+}
+
static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
return pinctrl_gpio_direction_input(chip->base + offset);
@@ -804,6 +822,7 @@ static const struct gpio_chip intel_gpio_chip = {
.owner = THIS_MODULE,
.request = gpiochip_generic_request,
.free = gpiochip_generic_free,
+ .get_direction = intel_gpio_get_direction,
.direction_input = intel_gpio_direction_input,
.direction_output = intel_gpio_direction_output,
.get = intel_gpio_get,
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 3e598740b379..862c5dbc6977 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -32,6 +32,13 @@ config PINCTRL_MT8127
select PINCTRL_MTK
# For ARMv8 SoCs
+config PINCTRL_MT2712
+ bool "MediaTek MT2712 pin control"
+ depends on OF
+ depends on ARM64 || COMPILE_TEST
+ default ARM64 && ARCH_MEDIATEK
+ select PINCTRL_MTK
+
config PINCTRL_MT7622
bool "MediaTek MT7622 pin control"
depends on OF
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
index ed7d2b2cc6e9..7959e773533f 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
# SoC Drivers
obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o
+obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2712.c b/drivers/pinctrl/mediatek/pinctrl-mt2712.c
new file mode 100644
index 000000000000..81e11f9e70f1
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c
@@ -0,0 +1,633 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/regmap.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#include "pinctrl-mtk-common.h"
+#include "pinctrl-mtk-mt2712.h"
+
+static const struct mtk_pin_spec_pupd_set_samereg mt2712_spec_pupd[] = {
+ MTK_PIN_PUPD_SPEC_SR(18, 0xe50, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(19, 0xe60, 12, 11, 10),
+ MTK_PIN_PUPD_SPEC_SR(20, 0xe50, 5, 4, 3),
+ MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 15, 14, 13),
+ MTK_PIN_PUPD_SPEC_SR(22, 0xe50, 8, 7, 6),
+ MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 2, 1, 0),
+
+ MTK_PIN_PUPD_SPEC_SR(30, 0xf30, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(31, 0xf30, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(32, 0xf30, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(33, 0xf30, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(34, 0xf40, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(35, 0xf40, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(36, 0xf40, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(37, 0xc40, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(38, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(39, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(40, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(41, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(42, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(43, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(44, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(45, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(46, 0xc50, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(47, 0xda0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(48, 0xd90, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(49, 0xdf0, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(50, 0xdf0, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(51, 0xdf0, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(52, 0xdf0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(53, 0xd50, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(54, 0xd80, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(55, 0xe00, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(56, 0xd40, 2, 1, 0),
+
+ MTK_PIN_PUPD_SPEC_SR(63, 0xc80, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(64, 0xdb0, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(65, 0xdb0, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(66, 0xdb0, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(67, 0xcd0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(68, 0xdb0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(69, 0xc90, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(70, 0xcc0, 2, 1, 0),
+
+ MTK_PIN_PUPD_SPEC_SR(89, 0xce0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(90, 0xdd0, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(91, 0xdd0, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(92, 0xdd0, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(93, 0xdd0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(94, 0xd20, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(95, 0xcf0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(96, 0xd30, 2, 1, 0),
+
+ MTK_PIN_PUPD_SPEC_SR(135, 0xe50, 11, 10, 9),
+ MTK_PIN_PUPD_SPEC_SR(136, 0xe50, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(137, 0xe70, 5, 4, 3),
+ MTK_PIN_PUPD_SPEC_SR(138, 0xe70, 8, 7, 6),
+ MTK_PIN_PUPD_SPEC_SR(139, 0xe70, 11, 10, 9),
+ MTK_PIN_PUPD_SPEC_SR(140, 0xe70, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(141, 0xe60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(142, 0xe60, 5, 4, 3)
+};
+
+static int mt2712_spec_pull_set(struct regmap *regmap,
+ unsigned int pin,
+ unsigned char align,
+ bool isup,
+ unsigned int r1r0)
+{
+ return mtk_pctrl_spec_pull_set_samereg(regmap, mt2712_spec_pupd,
+ ARRAY_SIZE(mt2712_spec_pupd), pin, align, isup, r1r0);
+}
+
+static const struct mtk_pin_ies_smt_set mt2712_smt_set[] = {
+ MTK_PIN_IES_SMT_SPEC(0, 3, 0x900, 2),
+ MTK_PIN_IES_SMT_SPEC(4, 7, 0x900, 0),
+ MTK_PIN_IES_SMT_SPEC(8, 11, 0x900, 1),
+ MTK_PIN_IES_SMT_SPEC(12, 12, 0x8d0, 6),
+ MTK_PIN_IES_SMT_SPEC(13, 13, 0x8d0, 7),
+ MTK_PIN_IES_SMT_SPEC(14, 14, 0x8d0, 6),
+ MTK_PIN_IES_SMT_SPEC(15, 15, 0x8d0, 7),
+ MTK_PIN_IES_SMT_SPEC(18, 23, 0x8d0, 1),
+ MTK_PIN_IES_SMT_SPEC(24, 25, 0x8d0, 2),
+ MTK_PIN_IES_SMT_SPEC(26, 26, 0x8d0, 3),
+ MTK_PIN_IES_SMT_SPEC(27, 27, 0x8d0, 4),
+ MTK_PIN_IES_SMT_SPEC(28, 29, 0x8d0, 3),
+ MTK_PIN_IES_SMT_SPEC(30, 36, 0xf50, 13),
+ MTK_PIN_IES_SMT_SPEC(37, 37, 0xc40, 13),
+ MTK_PIN_IES_SMT_SPEC(38, 45, 0xc60, 13),
+ MTK_PIN_IES_SMT_SPEC(46, 46, 0xc50, 13),
+ MTK_PIN_IES_SMT_SPEC(47, 47, 0xda0, 13),
+ MTK_PIN_IES_SMT_SPEC(48, 48, 0xd90, 13),
+ MTK_PIN_IES_SMT_SPEC(49, 52, 0xd60, 13),
+ MTK_PIN_IES_SMT_SPEC(53, 53, 0xd50, 13),
+ MTK_PIN_IES_SMT_SPEC(54, 54, 0xd80, 13),
+ MTK_PIN_IES_SMT_SPEC(55, 55, 0xe00, 13),
+ MTK_PIN_IES_SMT_SPEC(56, 56, 0xd40, 13),
+ MTK_PIN_IES_SMT_SPEC(57, 62, 0x900, 3),
+ MTK_PIN_IES_SMT_SPEC(63, 63, 0xc80, 13),
+ MTK_PIN_IES_SMT_SPEC(64, 66, 0xca0, 13),
+ MTK_PIN_IES_SMT_SPEC(67, 67, 0xc80, 13),
+ MTK_PIN_IES_SMT_SPEC(68, 68, 0xca0, 13),
+ MTK_PIN_IES_SMT_SPEC(69, 69, 0xc90, 13),
+ MTK_PIN_IES_SMT_SPEC(70, 70, 0xc80, 13),
+ MTK_PIN_IES_SMT_SPEC(71, 74, 0x8d0, 8),
+ MTK_PIN_IES_SMT_SPEC(75, 77, 0x8d0, 9),
+ MTK_PIN_IES_SMT_SPEC(78, 81, 0x8d0, 10),
+ MTK_PIN_IES_SMT_SPEC(82, 88, 0x8d0, 9),
+ MTK_PIN_IES_SMT_SPEC(89, 89, 0xce0, 13),
+ MTK_PIN_IES_SMT_SPEC(90, 93, 0xd00, 13),
+ MTK_PIN_IES_SMT_SPEC(94, 94, 0xce0, 13),
+ MTK_PIN_IES_SMT_SPEC(95, 96, 0xcf0, 13),
+ MTK_PIN_IES_SMT_SPEC(97, 100, 0x8d0, 11),
+ MTK_PIN_IES_SMT_SPEC(101, 104, 0x8d0, 12),
+ MTK_PIN_IES_SMT_SPEC(105, 105, 0x8d0, 13),
+ MTK_PIN_IES_SMT_SPEC(106, 106, 0x8d0, 14),
+ MTK_PIN_IES_SMT_SPEC(107, 107, 0x8d0, 15),
+ MTK_PIN_IES_SMT_SPEC(108, 108, 0x8e0, 0),
+ MTK_PIN_IES_SMT_SPEC(109, 109, 0x8e0, 1),
+ MTK_PIN_IES_SMT_SPEC(110, 110, 0x8e0, 2),
+ MTK_PIN_IES_SMT_SPEC(111, 111, 0x8d0, 13),
+ MTK_PIN_IES_SMT_SPEC(112, 112, 0x8d0, 14),
+ MTK_PIN_IES_SMT_SPEC(113, 113, 0x8d0, 15),
+ MTK_PIN_IES_SMT_SPEC(114, 114, 0x8e0, 0),
+ MTK_PIN_IES_SMT_SPEC(115, 115, 0x8e0, 1),
+ MTK_PIN_IES_SMT_SPEC(116, 116, 0x8e0, 2),
+ MTK_PIN_IES_SMT_SPEC(117, 117, 0x8e0, 3),
+ MTK_PIN_IES_SMT_SPEC(118, 118, 0x8e0, 4),
+ MTK_PIN_IES_SMT_SPEC(119, 119, 0x8e0, 5),
+ MTK_PIN_IES_SMT_SPEC(120, 120, 0x8e0, 3),
+ MTK_PIN_IES_SMT_SPEC(121, 121, 0x8e0, 4),
+ MTK_PIN_IES_SMT_SPEC(122, 122, 0x8e0, 5),
+ MTK_PIN_IES_SMT_SPEC(123, 126, 0x8e0, 6),
+ MTK_PIN_IES_SMT_SPEC(127, 130, 0x8e0, 7),
+ MTK_PIN_IES_SMT_SPEC(131, 134, 0x8e0, 8),
+ MTK_PIN_IES_SMT_SPEC(135, 142, 0x8d0, 1),
+ MTK_PIN_IES_SMT_SPEC(143, 147, 0x8e0, 9),
+ MTK_PIN_IES_SMT_SPEC(148, 152, 0x8e0, 10),
+ MTK_PIN_IES_SMT_SPEC(153, 156, 0x8e0, 11),
+ MTK_PIN_IES_SMT_SPEC(157, 160, 0x8e0, 12),
+ MTK_PIN_IES_SMT_SPEC(161, 164, 0x8e0, 13),
+ MTK_PIN_IES_SMT_SPEC(165, 168, 0x8e0, 14),
+ MTK_PIN_IES_SMT_SPEC(169, 170, 0x8e0, 15),
+ MTK_PIN_IES_SMT_SPEC(171, 172, 0x8f0, 0),
+ MTK_PIN_IES_SMT_SPEC(173, 173, 0x8f0, 1),
+ MTK_PIN_IES_SMT_SPEC(174, 175, 0x8f0, 2),
+ MTK_PIN_IES_SMT_SPEC(176, 176, 0x8f0, 1),
+ MTK_PIN_IES_SMT_SPEC(177, 177, 0x8f0, 3),
+ MTK_PIN_IES_SMT_SPEC(178, 178, 0x8f0, 4),
+ MTK_PIN_IES_SMT_SPEC(179, 179, 0x8f0, 3),
+ MTK_PIN_IES_SMT_SPEC(180, 180, 0x8f0, 4),
+ MTK_PIN_IES_SMT_SPEC(181, 181, 0x8f0, 5),
+ MTK_PIN_IES_SMT_SPEC(182, 182, 0x8f0, 6),
+ MTK_PIN_IES_SMT_SPEC(183, 183, 0x8f0, 5),
+ MTK_PIN_IES_SMT_SPEC(184, 184, 0x8f0, 6),
+ MTK_PIN_IES_SMT_SPEC(185, 186, 0x8f0, 7),
+ MTK_PIN_IES_SMT_SPEC(187, 187, 0x8f0, 8),
+ MTK_PIN_IES_SMT_SPEC(188, 188, 0x8f0, 9),
+ MTK_PIN_IES_SMT_SPEC(189, 189, 0x8f0, 8),
+ MTK_PIN_IES_SMT_SPEC(190, 190, 0x8f0, 9),
+ MTK_PIN_IES_SMT_SPEC(191, 191, 0x8f0, 10),
+ MTK_PIN_IES_SMT_SPEC(192, 192, 0x8f0, 11),
+ MTK_PIN_IES_SMT_SPEC(193, 194, 0x8f0, 10),
+ MTK_PIN_IES_SMT_SPEC(195, 195, 0x8f0, 11),
+ MTK_PIN_IES_SMT_SPEC(196, 199, 0x8f0, 12),
+ MTK_PIN_IES_SMT_SPEC(200, 203, 0x8f0, 13),
+ MTK_PIN_IES_SMT_SPEC(204, 206, 0x8f0, 14),
+ MTK_PIN_IES_SMT_SPEC(207, 209, 0x8f0, 15)
+};
+
+static const struct mtk_pin_ies_smt_set mt2712_ies_set[] = {
+ MTK_PIN_IES_SMT_SPEC(0, 3, 0x8c0, 2),
+ MTK_PIN_IES_SMT_SPEC(4, 7, 0x8c0, 0),
+ MTK_PIN_IES_SMT_SPEC(8, 9, 0x8c0, 1),
+ MTK_PIN_IES_SMT_SPEC(10, 11, 0x8c0, 4),
+ MTK_PIN_IES_SMT_SPEC(12, 12, 0x890, 6),
+ MTK_PIN_IES_SMT_SPEC(13, 13, 0x890, 7),
+ MTK_PIN_IES_SMT_SPEC(14, 14, 0x890, 6),
+ MTK_PIN_IES_SMT_SPEC(15, 15, 0x890, 7),
+ MTK_PIN_IES_SMT_SPEC(18, 23, 0x890, 1),
+ MTK_PIN_IES_SMT_SPEC(24, 25, 0x890, 2),
+ MTK_PIN_IES_SMT_SPEC(26, 26, 0x890, 3),
+ MTK_PIN_IES_SMT_SPEC(27, 27, 0x890, 4),
+ MTK_PIN_IES_SMT_SPEC(28, 29, 0x890, 3),
+ MTK_PIN_IES_SMT_SPEC(30, 36, 0xf50, 14),
+ MTK_PIN_IES_SMT_SPEC(37, 37, 0xc40, 14),
+ MTK_PIN_IES_SMT_SPEC(38, 45, 0xc60, 14),
+ MTK_PIN_IES_SMT_SPEC(46, 46, 0xc50, 14),
+ MTK_PIN_IES_SMT_SPEC(47, 47, 0xda0, 14),
+ MTK_PIN_IES_SMT_SPEC(48, 48, 0xd90, 14),
+ MTK_PIN_IES_SMT_SPEC(49, 52, 0xd60, 14),
+ MTK_PIN_IES_SMT_SPEC(53, 53, 0xd50, 14),
+ MTK_PIN_IES_SMT_SPEC(54, 54, 0xd80, 14),
+ MTK_PIN_IES_SMT_SPEC(55, 55, 0xe00, 14),
+ MTK_PIN_IES_SMT_SPEC(56, 56, 0xd40, 14),
+ MTK_PIN_IES_SMT_SPEC(57, 62, 0x8c0, 3),
+ MTK_PIN_IES_SMT_SPEC(63, 63, 0xc80, 14),
+ MTK_PIN_IES_SMT_SPEC(64, 66, 0xca0, 14),
+ MTK_PIN_IES_SMT_SPEC(67, 68, 0xc80, 14),
+ MTK_PIN_IES_SMT_SPEC(69, 69, 0xc90, 14),
+ MTK_PIN_IES_SMT_SPEC(70, 70, 0xc80, 14),
+ MTK_PIN_IES_SMT_SPEC(71, 74, 0x890, 8),
+ MTK_PIN_IES_SMT_SPEC(75, 77, 0x890, 9),
+ MTK_PIN_IES_SMT_SPEC(78, 81, 0x890, 10),
+ MTK_PIN_IES_SMT_SPEC(82, 88, 0x890, 9),
+ MTK_PIN_IES_SMT_SPEC(89, 89, 0xce0, 14),
+ MTK_PIN_IES_SMT_SPEC(90, 93, 0xd00, 14),
+ MTK_PIN_IES_SMT_SPEC(94, 94, 0xce0, 14),
+ MTK_PIN_IES_SMT_SPEC(95, 96, 0xcf0, 14),
+ MTK_PIN_IES_SMT_SPEC(97, 100, 0x890, 11),
+ MTK_PIN_IES_SMT_SPEC(101, 104, 0x890, 12),
+ MTK_PIN_IES_SMT_SPEC(105, 105, 0x890, 13),
+ MTK_PIN_IES_SMT_SPEC(106, 106, 0x890, 14),
+ MTK_PIN_IES_SMT_SPEC(107, 107, 0x890, 15),
+ MTK_PIN_IES_SMT_SPEC(108, 108, 0x8a0, 0),
+ MTK_PIN_IES_SMT_SPEC(109, 109, 0x8a0, 1),
+ MTK_PIN_IES_SMT_SPEC(110, 110, 0x8a0, 2),
+ MTK_PIN_IES_SMT_SPEC(111, 111, 0x890, 13),
+ MTK_PIN_IES_SMT_SPEC(112, 112, 0x890, 14),
+ MTK_PIN_IES_SMT_SPEC(113, 113, 0x890, 15),
+ MTK_PIN_IES_SMT_SPEC(114, 114, 0x8a0, 0),
+ MTK_PIN_IES_SMT_SPEC(115, 115, 0x8a0, 1),
+ MTK_PIN_IES_SMT_SPEC(116, 116, 0x8a0, 2),
+ MTK_PIN_IES_SMT_SPEC(117, 117, 0x8a0, 3),
+ MTK_PIN_IES_SMT_SPEC(118, 118, 0x8a0, 4),
+ MTK_PIN_IES_SMT_SPEC(119, 119, 0x8a0, 5),
+ MTK_PIN_IES_SMT_SPEC(120, 120, 0x8a0, 3),
+ MTK_PIN_IES_SMT_SPEC(121, 121, 0x8a0, 4),
+ MTK_PIN_IES_SMT_SPEC(122, 122, 0x8a0, 5),
+ MTK_PIN_IES_SMT_SPEC(123, 126, 0x8a0, 6),
+ MTK_PIN_IES_SMT_SPEC(127, 130, 0x8a0, 7),
+ MTK_PIN_IES_SMT_SPEC(131, 135, 0x8a0, 8),
+ MTK_PIN_IES_SMT_SPEC(136, 142, 0x890, 1),
+ MTK_PIN_IES_SMT_SPEC(143, 147, 0x8a0, 9),
+ MTK_PIN_IES_SMT_SPEC(148, 152, 0x8a0, 10),
+ MTK_PIN_IES_SMT_SPEC(153, 156, 0x8a0, 11),
+ MTK_PIN_IES_SMT_SPEC(157, 160, 0x8a0, 12),
+ MTK_PIN_IES_SMT_SPEC(161, 164, 0x8a0, 13),
+ MTK_PIN_IES_SMT_SPEC(165, 168, 0x8a0, 14),
+ MTK_PIN_IES_SMT_SPEC(169, 170, 0x8a0, 15),
+ MTK_PIN_IES_SMT_SPEC(171, 172, 0x8b0, 0),
+ MTK_PIN_IES_SMT_SPEC(173, 173, 0x8b0, 1),
+ MTK_PIN_IES_SMT_SPEC(174, 175, 0x8b0, 2),
+ MTK_PIN_IES_SMT_SPEC(176, 176, 0x8b0, 1),
+ MTK_PIN_IES_SMT_SPEC(177, 177, 0x8b0, 3),
+ MTK_PIN_IES_SMT_SPEC(178, 178, 0x8b0, 4),
+ MTK_PIN_IES_SMT_SPEC(179, 179, 0x8b0, 3),
+ MTK_PIN_IES_SMT_SPEC(180, 180, 0x8b0, 4),
+ MTK_PIN_IES_SMT_SPEC(181, 181, 0x8b0, 5),
+ MTK_PIN_IES_SMT_SPEC(182, 182, 0x8b0, 6),
+ MTK_PIN_IES_SMT_SPEC(183, 183, 0x8b0, 5),
+ MTK_PIN_IES_SMT_SPEC(184, 184, 0x8b0, 6),
+ MTK_PIN_IES_SMT_SPEC(185, 186, 0x8b0, 7),
+ MTK_PIN_IES_SMT_SPEC(187, 187, 0x8b0, 8),
+ MTK_PIN_IES_SMT_SPEC(188, 188, 0x8b0, 9),
+ MTK_PIN_IES_SMT_SPEC(189, 189, 0x8b0, 8),
+ MTK_PIN_IES_SMT_SPEC(190, 190, 0x8b0, 9),
+ MTK_PIN_IES_SMT_SPEC(191, 191, 0x8b0, 10),
+ MTK_PIN_IES_SMT_SPEC(192, 192, 0x8b0, 11),
+ MTK_PIN_IES_SMT_SPEC(193, 194, 0x8b0, 10),
+ MTK_PIN_IES_SMT_SPEC(195, 195, 0x8b0, 11),
+ MTK_PIN_IES_SMT_SPEC(196, 199, 0x8b0, 12),
+ MTK_PIN_IES_SMT_SPEC(200, 203, 0x8b0, 13),
+ MTK_PIN_IES_SMT_SPEC(204, 206, 0x8b0, 14),
+ MTK_PIN_IES_SMT_SPEC(207, 209, 0x8b0, 15)
+};
+
+static int mt2712_ies_smt_set(struct regmap *regmap, unsigned int pin,
+ unsigned char align,
+ int value, enum pin_config_param arg)
+{
+ if (arg == PIN_CONFIG_INPUT_ENABLE)
+ return mtk_pconf_spec_set_ies_smt_range(regmap, mt2712_ies_set,
+ ARRAY_SIZE(mt2712_ies_set), pin, align, value);
+ if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
+ return mtk_pconf_spec_set_ies_smt_range(regmap, mt2712_smt_set,
+ ARRAY_SIZE(mt2712_smt_set), pin, align, value);
+ return -EINVAL;
+}
+
+static const struct mtk_drv_group_desc mt2712_drv_grp[] = {
+ /* 0E4E8SR 4/8/12/16 */
+ MTK_DRV_GRP(4, 16, 1, 2, 4),
+ /* 0E2E4SR 2/4/6/8 */
+ MTK_DRV_GRP(2, 8, 1, 2, 2),
+ /* E8E4E2 2/4/6/8/10/12/14/16 */
+ MTK_DRV_GRP(2, 16, 0, 2, 2)
+};
+
+static const struct mtk_pin_drv_grp mt2712_pin_drv[] = {
+ MTK_PIN_DRV_GRP(0, 0xc10, 4, 0),
+ MTK_PIN_DRV_GRP(1, 0xc10, 4, 0),
+ MTK_PIN_DRV_GRP(2, 0xc10, 4, 0),
+ MTK_PIN_DRV_GRP(3, 0xc10, 4, 0),
+
+ MTK_PIN_DRV_GRP(4, 0xc00, 12, 0),
+ MTK_PIN_DRV_GRP(5, 0xc00, 12, 0),
+ MTK_PIN_DRV_GRP(6, 0xc00, 12, 0),
+ MTK_PIN_DRV_GRP(7, 0xc00, 12, 0),
+
+ MTK_PIN_DRV_GRP(8, 0xc10, 0, 0),
+ MTK_PIN_DRV_GRP(9, 0xc10, 0, 0),
+ MTK_PIN_DRV_GRP(10, 0xc10, 0, 0),
+ MTK_PIN_DRV_GRP(11, 0xc10, 0, 0),
+
+ MTK_PIN_DRV_GRP(12, 0xb60, 0, 0),
+
+ MTK_PIN_DRV_GRP(13, 0xb60, 4, 0),
+
+ MTK_PIN_DRV_GRP(14, 0xb60, 0, 0),
+
+ MTK_PIN_DRV_GRP(15, 0xb60, 4, 0),
+
+ MTK_PIN_DRV_GRP(18, 0xb40, 0, 1),
+ MTK_PIN_DRV_GRP(19, 0xb40, 0, 1),
+ MTK_PIN_DRV_GRP(20, 0xb40, 0, 1),
+ MTK_PIN_DRV_GRP(21, 0xb40, 0, 1),
+ MTK_PIN_DRV_GRP(22, 0xb40, 0, 1),
+ MTK_PIN_DRV_GRP(23, 0xb40, 0, 1),
+
+ MTK_PIN_DRV_GRP(24, 0xb40, 4, 0),
+
+ MTK_PIN_DRV_GRP(25, 0xb40, 8, 0),
+
+ MTK_PIN_DRV_GRP(26, 0xb40, 12, 0),
+
+ MTK_PIN_DRV_GRP(27, 0xb50, 0, 0),
+
+ MTK_PIN_DRV_GRP(28, 0xb40, 12, 0),
+ MTK_PIN_DRV_GRP(29, 0xb40, 12, 0),
+
+ MTK_PIN_DRV_GRP(30, 0xf50, 8, 2),
+ MTK_PIN_DRV_GRP(31, 0xf50, 8, 2),
+ MTK_PIN_DRV_GRP(32, 0xf50, 8, 2),
+ MTK_PIN_DRV_GRP(33, 0xf50, 8, 2),
+ MTK_PIN_DRV_GRP(34, 0xf50, 8, 2),
+ MTK_PIN_DRV_GRP(35, 0xf50, 8, 2),
+ MTK_PIN_DRV_GRP(36, 0xf50, 8, 2),
+
+ MTK_PIN_DRV_GRP(37, 0xc40, 8, 2),
+
+ MTK_PIN_DRV_GRP(38, 0xc60, 8, 2),
+ MTK_PIN_DRV_GRP(39, 0xc60, 8, 2),
+ MTK_PIN_DRV_GRP(40, 0xc60, 8, 2),
+ MTK_PIN_DRV_GRP(41, 0xc60, 8, 2),
+ MTK_PIN_DRV_GRP(42, 0xc60, 8, 2),
+ MTK_PIN_DRV_GRP(43, 0xc60, 8, 2),
+ MTK_PIN_DRV_GRP(44, 0xc60, 8, 2),
+ MTK_PIN_DRV_GRP(45, 0xc60, 8, 2),
+
+ MTK_PIN_DRV_GRP(46, 0xc50, 8, 2),
+
+ MTK_PIN_DRV_GRP(47, 0xda0, 8, 2),
+
+ MTK_PIN_DRV_GRP(48, 0xd90, 8, 2),
+
+ MTK_PIN_DRV_GRP(49, 0xd60, 8, 2),
+ MTK_PIN_DRV_GRP(50, 0xd60, 8, 2),
+ MTK_PIN_DRV_GRP(51, 0xd60, 8, 2),
+ MTK_PIN_DRV_GRP(52, 0xd60, 8, 2),
+
+ MTK_PIN_DRV_GRP(53, 0xd50, 8, 2),
+
+ MTK_PIN_DRV_GRP(54, 0xd80, 8, 2),
+
+ MTK_PIN_DRV_GRP(55, 0xe00, 8, 2),
+
+ MTK_PIN_DRV_GRP(56, 0xd40, 8, 2),
+
+ MTK_PIN_DRV_GRP(63, 0xc80, 8, 2),
+
+ MTK_PIN_DRV_GRP(64, 0xca0, 8, 2),
+ MTK_PIN_DRV_GRP(65, 0xca0, 8, 2),
+ MTK_PIN_DRV_GRP(66, 0xca0, 8, 2),
+
+ MTK_PIN_DRV_GRP(67, 0xcd0, 8, 2),
+
+ MTK_PIN_DRV_GRP(68, 0xca0, 8, 2),
+
+ MTK_PIN_DRV_GRP(69, 0xc90, 8, 2),
+
+ MTK_PIN_DRV_GRP(70, 0xcc0, 8, 2),
+
+ MTK_PIN_DRV_GRP(71, 0xb60, 8, 1),
+ MTK_PIN_DRV_GRP(72, 0xb60, 8, 1),
+ MTK_PIN_DRV_GRP(73, 0xb60, 8, 1),
+ MTK_PIN_DRV_GRP(74, 0xb60, 8, 1),
+
+ MTK_PIN_DRV_GRP(75, 0xb60, 12, 1),
+ MTK_PIN_DRV_GRP(76, 0xb60, 12, 1),
+ MTK_PIN_DRV_GRP(77, 0xb60, 12, 1),
+
+ MTK_PIN_DRV_GRP(78, 0xb70, 0, 1),
+ MTK_PIN_DRV_GRP(79, 0xb70, 0, 1),
+ MTK_PIN_DRV_GRP(80, 0xb70, 0, 1),
+ MTK_PIN_DRV_GRP(81, 0xb70, 0, 1),
+
+ MTK_PIN_DRV_GRP(82, 0xb60, 12, 1),
+ MTK_PIN_DRV_GRP(83, 0xb60, 12, 1),
+ MTK_PIN_DRV_GRP(84, 0xb60, 12, 1),
+ MTK_PIN_DRV_GRP(85, 0xb60, 12, 1),
+ MTK_PIN_DRV_GRP(86, 0xb60, 12, 1),
+ MTK_PIN_DRV_GRP(87, 0xb60, 12, 1),
+ MTK_PIN_DRV_GRP(88, 0xb60, 12, 1),
+
+ MTK_PIN_DRV_GRP(89, 0xce0, 8, 2),
+
+ MTK_PIN_DRV_GRP(90, 0xd00, 8, 2),
+ MTK_PIN_DRV_GRP(91, 0xd00, 8, 2),
+ MTK_PIN_DRV_GRP(92, 0xd00, 8, 2),
+ MTK_PIN_DRV_GRP(93, 0xd00, 8, 2),
+
+ MTK_PIN_DRV_GRP(94, 0xd20, 8, 2),
+
+ MTK_PIN_DRV_GRP(95, 0xcf0, 8, 2),
+
+ MTK_PIN_DRV_GRP(96, 0xd30, 8, 2),
+
+ MTK_PIN_DRV_GRP(97, 0xb70, 4, 0),
+ MTK_PIN_DRV_GRP(98, 0xb70, 4, 0),
+ MTK_PIN_DRV_GRP(99, 0xb70, 4, 0),
+ MTK_PIN_DRV_GRP(100, 0xb70, 4, 0),
+
+ MTK_PIN_DRV_GRP(101, 0xb70, 8, 0),
+ MTK_PIN_DRV_GRP(102, 0xb70, 8, 0),
+ MTK_PIN_DRV_GRP(103, 0xb70, 8, 0),
+ MTK_PIN_DRV_GRP(104, 0xb70, 8, 0),
+
+ MTK_PIN_DRV_GRP(135, 0xb40, 0, 1),
+ MTK_PIN_DRV_GRP(136, 0xb40, 0, 1),
+ MTK_PIN_DRV_GRP(137, 0xb40, 0, 1),
+ MTK_PIN_DRV_GRP(138, 0xb40, 0, 1),
+ MTK_PIN_DRV_GRP(139, 0xb40, 0, 1),
+ MTK_PIN_DRV_GRP(140, 0xb40, 0, 1),
+ MTK_PIN_DRV_GRP(141, 0xb40, 0, 1),
+ MTK_PIN_DRV_GRP(142, 0xb40, 0, 1),
+
+ MTK_PIN_DRV_GRP(143, 0xba0, 12, 0),
+ MTK_PIN_DRV_GRP(144, 0xba0, 12, 0),
+ MTK_PIN_DRV_GRP(145, 0xba0, 12, 0),
+ MTK_PIN_DRV_GRP(146, 0xba0, 12, 0),
+ MTK_PIN_DRV_GRP(147, 0xba0, 12, 0),
+
+ MTK_PIN_DRV_GRP(148, 0xbb0, 0, 0),
+ MTK_PIN_DRV_GRP(149, 0xbb0, 0, 0),
+ MTK_PIN_DRV_GRP(150, 0xbb0, 0, 0),
+ MTK_PIN_DRV_GRP(151, 0xbb0, 0, 0),
+ MTK_PIN_DRV_GRP(152, 0xbb0, 0, 0),
+
+ MTK_PIN_DRV_GRP(153, 0xbb0, 4, 0),
+ MTK_PIN_DRV_GRP(154, 0xbb0, 4, 0),
+ MTK_PIN_DRV_GRP(155, 0xbb0, 4, 0),
+ MTK_PIN_DRV_GRP(156, 0xbb0, 4, 0),
+
+ MTK_PIN_DRV_GRP(157, 0xbb0, 8, 0),
+ MTK_PIN_DRV_GRP(158, 0xbb0, 8, 0),
+ MTK_PIN_DRV_GRP(159, 0xbb0, 8, 0),
+ MTK_PIN_DRV_GRP(160, 0xbb0, 8, 0),
+
+ MTK_PIN_DRV_GRP(161, 0xbb0, 12, 0),
+ MTK_PIN_DRV_GRP(162, 0xbb0, 12, 0),
+ MTK_PIN_DRV_GRP(163, 0xbb0, 12, 0),
+ MTK_PIN_DRV_GRP(164, 0xbb0, 12, 0),
+
+ MTK_PIN_DRV_GRP(165, 0xbc0, 0, 0),
+ MTK_PIN_DRV_GRP(166, 0xbc0, 0, 0),
+ MTK_PIN_DRV_GRP(167, 0xbc0, 0, 0),
+ MTK_PIN_DRV_GRP(168, 0xbc0, 0, 0),
+
+ MTK_PIN_DRV_GRP(169, 0xbc0, 4, 0),
+ MTK_PIN_DRV_GRP(170, 0xbc0, 4, 0),
+
+ MTK_PIN_DRV_GRP(171, 0xbc0, 8, 0),
+ MTK_PIN_DRV_GRP(172, 0xbc0, 8, 0),
+
+ MTK_PIN_DRV_GRP(173, 0xbc0, 12, 0),
+
+ MTK_PIN_DRV_GRP(174, 0xbd0, 0, 0),
+ MTK_PIN_DRV_GRP(175, 0xbd0, 0, 0),
+
+ MTK_PIN_DRV_GRP(176, 0xbc0, 12, 0),
+
+ MTK_PIN_DRV_GRP(177, 0xbd0, 4, 0),
+
+ MTK_PIN_DRV_GRP(178, 0xbd0, 8, 0),
+
+ MTK_PIN_DRV_GRP(179, 0xbd0, 4, 0),
+
+ MTK_PIN_DRV_GRP(180, 0xbd0, 8, 0),
+
+ MTK_PIN_DRV_GRP(181, 0xbd0, 12, 0),
+
+ MTK_PIN_DRV_GRP(182, 0xbe0, 0, 0),
+
+ MTK_PIN_DRV_GRP(183, 0xbd0, 12, 0),
+
+ MTK_PIN_DRV_GRP(184, 0xbe0, 0, 0),
+
+ MTK_PIN_DRV_GRP(185, 0xbe0, 4, 0),
+
+ MTK_PIN_DRV_GRP(186, 0xbe0, 8, 0),
+
+ MTK_PIN_DRV_GRP(187, 0xbe0, 12, 0),
+
+ MTK_PIN_DRV_GRP(188, 0xbf0, 0, 0),
+
+ MTK_PIN_DRV_GRP(189, 0xbe0, 12, 0),
+
+ MTK_PIN_DRV_GRP(190, 0xbf0, 0, 0),
+
+ MTK_PIN_DRV_GRP(191, 0xbf0, 4, 0),
+
+ MTK_PIN_DRV_GRP(192, 0xbf0, 8, 0),
+
+ MTK_PIN_DRV_GRP(193, 0xbf0, 4, 0),
+ MTK_PIN_DRV_GRP(194, 0xbf0, 4, 0),
+
+ MTK_PIN_DRV_GRP(195, 0xbf0, 8, 0),
+
+ MTK_PIN_DRV_GRP(196, 0xbf0, 12, 0),
+ MTK_PIN_DRV_GRP(197, 0xbf0, 12, 0),
+ MTK_PIN_DRV_GRP(198, 0xbf0, 12, 0),
+ MTK_PIN_DRV_GRP(199, 0xbf0, 12, 0),
+
+ MTK_PIN_DRV_GRP(200, 0xc00, 0, 0),
+ MTK_PIN_DRV_GRP(201, 0xc00, 0, 0),
+ MTK_PIN_DRV_GRP(202, 0xc00, 0, 0),
+ MTK_PIN_DRV_GRP(203, 0xc00, 0, 0),
+
+ MTK_PIN_DRV_GRP(204, 0xc00, 4, 0),
+ MTK_PIN_DRV_GRP(205, 0xc00, 4, 0),
+ MTK_PIN_DRV_GRP(206, 0xc00, 4, 0),
+
+ MTK_PIN_DRV_GRP(207, 0xc00, 8, 0),
+ MTK_PIN_DRV_GRP(208, 0xc00, 8, 0),
+ MTK_PIN_DRV_GRP(209, 0xc00, 8, 0),
+};
+
+static const struct mtk_pinctrl_devdata mt2712_pinctrl_data = {
+ .pins = mtk_pins_mt2712,
+ .npins = ARRAY_SIZE(mtk_pins_mt2712),
+ .grp_desc = mt2712_drv_grp,
+ .n_grp_cls = ARRAY_SIZE(mt2712_drv_grp),
+ .pin_drv_grp = mt2712_pin_drv,
+ .n_pin_drv_grps = ARRAY_SIZE(mt2712_pin_drv),
+ .spec_pull_set = mt2712_spec_pull_set,
+ .spec_ies_smt_set = mt2712_ies_smt_set,
+ .dir_offset = 0x0000,
+ .pullen_offset = 0x0100,
+ .pullsel_offset = 0x0200,
+ .dout_offset = 0x0300,
+ .din_offset = 0x0400,
+ .pinmux_offset = 0x0500,
+ .type1_start = 210,
+ .type1_end = 210,
+ .port_shf = 4,
+ .port_mask = 0xf,
+ .port_align = 4,
+ .eint_offsets = {
+ .name = "mt2712_eint",
+ .stat = 0x000,
+ .ack = 0x040,
+ .mask = 0x080,
+ .mask_set = 0x0c0,
+ .mask_clr = 0x100,
+ .sens = 0x140,
+ .sens_set = 0x180,
+ .sens_clr = 0x1c0,
+ .soft = 0x200,
+ .soft_set = 0x240,
+ .soft_clr = 0x280,
+ .pol = 0x300,
+ .pol_set = 0x340,
+ .pol_clr = 0x380,
+ .dom_en = 0x400,
+ .dbnc_ctrl = 0x500,
+ .dbnc_set = 0x600,
+ .dbnc_clr = 0x700,
+ .port_mask = 0xf,
+ .ports = 8,
+ },
+ .ap_num = 229,
+ .db_cnt = 40,
+};
+
+static int mt2712_pinctrl_probe(struct platform_device *pdev)
+{
+ return mtk_pctrl_init(pdev, &mt2712_pinctrl_data, NULL);
+}
+
+static const struct of_device_id mt2712_pctrl_match[] = {
+ {
+ .compatible = "mediatek,mt2712-pinctrl",
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, mt2712_pctrl_match);
+
+static struct platform_driver mtk_pinctrl_driver = {
+ .probe = mt2712_pinctrl_probe,
+ .driver = {
+ .name = "mediatek-mt2712-pinctrl",
+ .of_match_table = mt2712_pctrl_match,
+ .pm = &mtk_eint_pm_ops,
+ },
+};
+
+static int __init mtk_pinctrl_init(void)
+{
+ return platform_driver_register(&mtk_pinctrl_driver);
+}
+
+arch_initcall(mtk_pinctrl_init);
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index 3cf384f8b122..c3975a04d1cd 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -293,7 +293,7 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
unsigned int pin, bool enable, bool isup, unsigned int arg)
{
unsigned int bit;
- unsigned int reg_pullen, reg_pullsel;
+ unsigned int reg_pullen, reg_pullsel, r1r0;
int ret;
/* Some pins' pull setting are very different,
@@ -301,8 +301,12 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
* resistor bit, so we need this special handle.
*/
if (pctl->devdata->spec_pull_set) {
+ /* For special pins, bias-disable is set by R1R0,
+ * the parameter should be "MTK_PUPD_SET_R1R0_00".
+ */
+ r1r0 = enable ? arg : MTK_PUPD_SET_R1R0_00;
ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
- pin, pctl->devdata->port_align, isup, arg);
+ pin, pctl->devdata->port_align, isup, r1r0);
if (!ret)
return 0;
}
@@ -501,7 +505,7 @@ static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
int num_pins, num_funcs, maps_per_pin;
unsigned long *configs;
unsigned int num_configs;
- bool has_config = 0;
+ bool has_config = false;
int i, err;
unsigned reserve = 0;
struct mtk_pinctrl_group *grp;
@@ -520,7 +524,7 @@ static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
return err;
if (num_configs)
- has_config = 1;
+ has_config = true;
num_pins = pins->length / sizeof(u32);
num_funcs = num_pins;
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h
index 1035df49301f..940f7678f09b 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h
@@ -19,53 +19,46 @@
#include "pinctrl-mtk-common.h"
static const struct mtk_desc_pin mtk_pins_mt2701[] = {
- MTK_PIN(
- PINCTRL_PIN(0, "PWRAP_SPI0_MI"),
+ MTK_PIN(PINCTRL_PIN(0, "PWRAP_SPI0_MI"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 148),
MTK_FUNCTION(0, "GPIO0"),
MTK_FUNCTION(1, "PWRAP_SPIDO"),
MTK_FUNCTION(2, "PWRAP_SPIDI")
),
- MTK_PIN(
- PINCTRL_PIN(1, "PWRAP_SPI0_MO"),
+ MTK_PIN(PINCTRL_PIN(1, "PWRAP_SPI0_MO"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 149),
MTK_FUNCTION(0, "GPIO1"),
MTK_FUNCTION(1, "PWRAP_SPIDI"),
MTK_FUNCTION(2, "PWRAP_SPIDO")
),
- MTK_PIN(
- PINCTRL_PIN(2, "PWRAP_INT"),
+ MTK_PIN(PINCTRL_PIN(2, "PWRAP_INT"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 150),
MTK_FUNCTION(0, "GPIO2"),
MTK_FUNCTION(1, "PWRAP_INT")
),
- MTK_PIN(
- PINCTRL_PIN(3, "PWRAP_SPI0_CK"),
+ MTK_PIN(PINCTRL_PIN(3, "PWRAP_SPI0_CK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 151),
MTK_FUNCTION(0, "GPIO3"),
MTK_FUNCTION(1, "PWRAP_SPICK_I")
),
- MTK_PIN(
- PINCTRL_PIN(4, "PWRAP_SPI0_CSN"),
+ MTK_PIN(PINCTRL_PIN(4, "PWRAP_SPI0_CSN"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 152),
MTK_FUNCTION(0, "GPIO4"),
MTK_FUNCTION(1, "PWRAP_SPICS_B_I")
),
- MTK_PIN(
- PINCTRL_PIN(5, "PWRAP_SPI0_CK2"),
+ MTK_PIN(PINCTRL_PIN(5, "PWRAP_SPI0_CK2"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 153),
MTK_FUNCTION(0, "GPIO5"),
MTK_FUNCTION(1, "PWRAP_SPICK2_I"),
MTK_FUNCTION(5, "ANT_SEL1")
),
- MTK_PIN(
- PINCTRL_PIN(6, "PWRAP_SPI0_CSN2"),
+ MTK_PIN(PINCTRL_PIN(6, "PWRAP_SPI0_CSN2"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 154),
MTK_FUNCTION(0, "GPIO6"),
@@ -73,8 +66,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(5, "ANT_SEL0"),
MTK_FUNCTION(7, "DBG_MON_A[0]")
),
- MTK_PIN(
- PINCTRL_PIN(7, "SPI1_CSN"),
+ MTK_PIN(PINCTRL_PIN(7, "SPI1_CSN"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 155),
MTK_FUNCTION(0, "GPIO7"),
@@ -82,8 +74,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(4, "KCOL0"),
MTK_FUNCTION(7, "DBG_MON_B[12]")
),
- MTK_PIN(
- PINCTRL_PIN(8, "SPI1_MI"),
+ MTK_PIN(PINCTRL_PIN(8, "SPI1_MI"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 156),
MTK_FUNCTION(0, "GPIO8"),
@@ -92,8 +83,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(4, "KCOL1"),
MTK_FUNCTION(7, "DBG_MON_B[13]")
),
- MTK_PIN(
- PINCTRL_PIN(9, "SPI1_MO"),
+ MTK_PIN(PINCTRL_PIN(9, "SPI1_MO"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 157),
MTK_FUNCTION(0, "GPIO9"),
@@ -103,36 +93,31 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(4, "KCOL2"),
MTK_FUNCTION(7, "DBG_MON_B[14]")
),
- MTK_PIN(
- PINCTRL_PIN(10, "RTC32K_CK"),
+ MTK_PIN(PINCTRL_PIN(10, "RTC32K_CK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 158),
MTK_FUNCTION(0, "GPIO10"),
MTK_FUNCTION(1, "RTC32K_CK")
),
- MTK_PIN(
- PINCTRL_PIN(11, "WATCHDOG"),
+ MTK_PIN(PINCTRL_PIN(11, "WATCHDOG"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 159),
MTK_FUNCTION(0, "GPIO11"),
MTK_FUNCTION(1, "WATCHDOG")
),
- MTK_PIN(
- PINCTRL_PIN(12, "SRCLKENA"),
+ MTK_PIN(PINCTRL_PIN(12, "SRCLKENA"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 160),
MTK_FUNCTION(0, "GPIO12"),
MTK_FUNCTION(1, "SRCLKENA")
),
- MTK_PIN(
- PINCTRL_PIN(13, "SRCLKENAI"),
+ MTK_PIN(PINCTRL_PIN(13, "SRCLKENAI"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 161),
MTK_FUNCTION(0, "GPIO13"),
MTK_FUNCTION(1, "SRCLKENAI")
),
- MTK_PIN(
- PINCTRL_PIN(14, "URXD2"),
+ MTK_PIN(PINCTRL_PIN(14, "URXD2"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 162),
MTK_FUNCTION(0, "GPIO14"),
@@ -141,8 +126,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(5, "SRCCLKENAI2"),
MTK_FUNCTION(7, "DBG_MON_B[30]")
),
- MTK_PIN(
- PINCTRL_PIN(15, "UTXD2"),
+ MTK_PIN(PINCTRL_PIN(15, "UTXD2"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 163),
MTK_FUNCTION(0, "GPIO15"),
@@ -150,8 +134,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(2, "URXD2"),
MTK_FUNCTION(7, "DBG_MON_B[31]")
),
- MTK_PIN(
- PINCTRL_PIN(16, "I2S5_DATA_IN"),
+ MTK_PIN(PINCTRL_PIN(16, "I2S5_DATA_IN"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 164),
MTK_FUNCTION(0, "GPIO16"),
@@ -159,8 +142,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(3, "PCM_RX"),
MTK_FUNCTION(4, "ANT_SEL4")
),
- MTK_PIN(
- PINCTRL_PIN(17, "I2S5_BCK"),
+ MTK_PIN(PINCTRL_PIN(17, "I2S5_BCK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 165),
MTK_FUNCTION(0, "GPIO17"),
@@ -168,8 +150,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(3, "PCM_CLK0"),
MTK_FUNCTION(4, "ANT_SEL2")
),
- MTK_PIN(
- PINCTRL_PIN(18, "PCM_CLK"),
+ MTK_PIN(PINCTRL_PIN(18, "PCM_CLK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 166),
MTK_FUNCTION(0, "GPIO18"),
@@ -180,8 +161,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(6, "WCN_PCM_CLKO"),
MTK_FUNCTION(7, "DBG_MON_A[3]")
),
- MTK_PIN(
- PINCTRL_PIN(19, "PCM_SYNC"),
+ MTK_PIN(PINCTRL_PIN(19, "PCM_SYNC"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 167),
MTK_FUNCTION(0, "GPIO19"),
@@ -191,8 +171,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(6, "WCN_PCM_SYNC"),
MTK_FUNCTION(7, "DBG_MON_A[5]")
),
- MTK_PIN(
- PINCTRL_PIN(20, "PCM_RX"),
+ MTK_PIN(PINCTRL_PIN(20, "PCM_RX"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO20"),
@@ -204,8 +183,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(6, "WCN_PCM_RX"),
MTK_FUNCTION(7, "DBG_MON_A[4]")
),
- MTK_PIN(
- PINCTRL_PIN(21, "PCM_TX"),
+ MTK_PIN(PINCTRL_PIN(21, "PCM_TX"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO21"),
@@ -217,8 +195,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(6, "WCN_PCM_TX"),
MTK_FUNCTION(7, "DBG_MON_A[2]")
),
- MTK_PIN(
- PINCTRL_PIN(22, "EINT0"),
+ MTK_PIN(PINCTRL_PIN(22, "EINT0"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 0),
MTK_FUNCTION(0, "GPIO22"),
@@ -231,8 +208,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(7, "DBG_MON_A[30]"),
MTK_FUNCTION(10, "PCIE0_PERST_N")
),
- MTK_PIN(
- PINCTRL_PIN(23, "EINT1"),
+ MTK_PIN(PINCTRL_PIN(23, "EINT1"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 1),
MTK_FUNCTION(0, "GPIO23"),
@@ -245,8 +221,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(7, "DBG_MON_A[29]"),
MTK_FUNCTION(10, "PCIE1_PERST_N")
),
- MTK_PIN(
- PINCTRL_PIN(24, "EINT2"),
+ MTK_PIN(PINCTRL_PIN(24, "EINT2"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 2),
MTK_FUNCTION(0, "GPIO24"),
@@ -258,8 +233,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(7, "DBG_MON_A[28]"),
MTK_FUNCTION(10, "PCIE2_PERST_N")
),
- MTK_PIN(
- PINCTRL_PIN(25, "EINT3"),
+ MTK_PIN(PINCTRL_PIN(25, "EINT3"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 3),
MTK_FUNCTION(0, "GPIO25"),
@@ -268,8 +242,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(4, "CONN_MCU_DBGI_N"),
MTK_FUNCTION(7, "DBG_MON_A[27]")
),
- MTK_PIN(
- PINCTRL_PIN(26, "EINT4"),
+ MTK_PIN(PINCTRL_PIN(26, "EINT4"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 4),
MTK_FUNCTION(0, "GPIO26"),
@@ -281,8 +254,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(6, "PCIE2_WAKE_N"),
MTK_FUNCTION(7, "DBG_MON_A[26]")
),
- MTK_PIN(
- PINCTRL_PIN(27, "EINT5"),
+ MTK_PIN(PINCTRL_PIN(27, "EINT5"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 5),
MTK_FUNCTION(0, "GPIO27"),
@@ -293,8 +265,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(6, "PCIE1_WAKE_N"),
MTK_FUNCTION(7, "DBG_MON_A[25]")
),
- MTK_PIN(
- PINCTRL_PIN(28, "EINT6"),
+ MTK_PIN(PINCTRL_PIN(28, "EINT6"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 6),
MTK_FUNCTION(0, "GPIO28"),
@@ -304,8 +275,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(6, "PCIE0_WAKE_N"),
MTK_FUNCTION(7, "DBG_MON_A[24]")
),
- MTK_PIN(
- PINCTRL_PIN(29, "EINT7"),
+ MTK_PIN(PINCTRL_PIN(29, "EINT7"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 7),
MTK_FUNCTION(0, "GPIO29"),
@@ -319,8 +289,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(7, "DBG_MON_A[23]"),
MTK_FUNCTION(14, "PCIE2_PERST_N")
),
- MTK_PIN(
- PINCTRL_PIN(30, "I2S5_LRCK"),
+ MTK_PIN(PINCTRL_PIN(30, "I2S5_LRCK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 12),
MTK_FUNCTION(0, "GPIO30"),
@@ -328,16 +297,14 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(3, "PCM_SYNC"),
MTK_FUNCTION(4, "ANT_SEL1")
),
- MTK_PIN(
- PINCTRL_PIN(31, "I2S5_MCLK"),
+ MTK_PIN(PINCTRL_PIN(31, "I2S5_MCLK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 13),
MTK_FUNCTION(0, "GPIO31"),
MTK_FUNCTION(1, "I2S5_MCLK"),
MTK_FUNCTION(4, "ANT_SEL0")
),
- MTK_PIN(
- PINCTRL_PIN(32, "I2S5_DATA"),
+ MTK_PIN(PINCTRL_PIN(32, "I2S5_DATA"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 14),
MTK_FUNCTION(0, "GPIO32"),
@@ -346,8 +313,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(3, "PCM_TX"),
MTK_FUNCTION(4, "ANT_SEL3")
),
- MTK_PIN(
- PINCTRL_PIN(33, "I2S1_DATA"),
+ MTK_PIN(PINCTRL_PIN(33, "I2S1_DATA"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 15),
MTK_FUNCTION(0, "GPIO33"),
@@ -359,8 +325,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(6, "WCN_PCM_TX"),
MTK_FUNCTION(7, "DBG_MON_B[8]")
),
- MTK_PIN(
- PINCTRL_PIN(34, "I2S1_DATA_IN"),
+ MTK_PIN(PINCTRL_PIN(34, "I2S1_DATA_IN"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 16),
MTK_FUNCTION(0, "GPIO34"),
@@ -371,8 +336,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(6, "WCN_PCM_RX"),
MTK_FUNCTION(7, "DBG_MON_B[7]")
),
- MTK_PIN(
- PINCTRL_PIN(35, "I2S1_BCK"),
+ MTK_PIN(PINCTRL_PIN(35, "I2S1_BCK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 17),
MTK_FUNCTION(0, "GPIO35"),
@@ -382,8 +346,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(6, "WCN_PCM_CLKO"),
MTK_FUNCTION(7, "DBG_MON_B[9]")
),
- MTK_PIN(
- PINCTRL_PIN(36, "I2S1_LRCK"),
+ MTK_PIN(PINCTRL_PIN(36, "I2S1_LRCK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 18),
MTK_FUNCTION(0, "GPIO36"),
@@ -393,8 +356,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(6, "WCN_PCM_SYNC"),
MTK_FUNCTION(7, "DBG_MON_B[10]")
),
- MTK_PIN(
- PINCTRL_PIN(37, "I2S1_MCLK"),
+ MTK_PIN(PINCTRL_PIN(37, "I2S1_MCLK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 19),
MTK_FUNCTION(0, "GPIO37"),
@@ -402,8 +364,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(5, "G1_RXDV"),
MTK_FUNCTION(7, "DBG_MON_B[11]")
),
- MTK_PIN(
- PINCTRL_PIN(38, "I2S2_DATA"),
+ MTK_PIN(PINCTRL_PIN(38, "I2S2_DATA"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 20),
MTK_FUNCTION(0, "GPIO38"),
@@ -411,8 +372,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(3, "PCM_TX"),
MTK_FUNCTION(4, "DMIC_DAT0")
),
- MTK_PIN(
- PINCTRL_PIN(39, "JTMS"),
+ MTK_PIN(PINCTRL_PIN(39, "JTMS"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 21),
MTK_FUNCTION(0, "GPIO39"),
@@ -421,8 +381,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(3, "CONN_MCU_AICE_JMSC"),
MTK_FUNCTION(4, "DFD_TMS_XI")
),
- MTK_PIN(
- PINCTRL_PIN(40, "JTCK"),
+ MTK_PIN(PINCTRL_PIN(40, "JTCK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 22),
MTK_FUNCTION(0, "GPIO40"),
@@ -431,8 +390,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(3, "CONN_MCU_AICE_JCKC"),
MTK_FUNCTION(4, "DFD_TCK_XI")
),
- MTK_PIN(
- PINCTRL_PIN(41, "JTDI"),
+ MTK_PIN(PINCTRL_PIN(41, "JTDI"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 23),
MTK_FUNCTION(0, "GPIO41"),
@@ -440,8 +398,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(2, "CONN_MCU_TDI"),
MTK_FUNCTION(4, "DFD_TDI_XI")
),
- MTK_PIN(
- PINCTRL_PIN(42, "JTDO"),
+ MTK_PIN(PINCTRL_PIN(42, "JTDO"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 24),
MTK_FUNCTION(0, "GPIO42"),
@@ -449,55 +406,48 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(2, "CONN_MCU_TDO"),
MTK_FUNCTION(4, "DFD_TDO")
),
- MTK_PIN(
- PINCTRL_PIN(43, "NCLE"),
+ MTK_PIN(PINCTRL_PIN(43, "NCLE"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 25),
MTK_FUNCTION(0, "GPIO43"),
MTK_FUNCTION(1, "NCLE"),
MTK_FUNCTION(2, "EXT_XCS2")
),
- MTK_PIN(
- PINCTRL_PIN(44, "NCEB1"),
+ MTK_PIN(PINCTRL_PIN(44, "NCEB1"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 26),
MTK_FUNCTION(0, "GPIO44"),
MTK_FUNCTION(1, "NCEB1"),
MTK_FUNCTION(2, "IDDIG")
),
- MTK_PIN(
- PINCTRL_PIN(45, "NCEB0"),
+ MTK_PIN(PINCTRL_PIN(45, "NCEB0"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 27),
MTK_FUNCTION(0, "GPIO45"),
MTK_FUNCTION(1, "NCEB0"),
MTK_FUNCTION(2, "DRV_VBUS")
),
- MTK_PIN(
- PINCTRL_PIN(46, "IR"),
+ MTK_PIN(PINCTRL_PIN(46, "IR"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 28),
MTK_FUNCTION(0, "GPIO46"),
MTK_FUNCTION(1, "IR")
),
- MTK_PIN(
- PINCTRL_PIN(47, "NREB"),
+ MTK_PIN(PINCTRL_PIN(47, "NREB"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 29),
MTK_FUNCTION(0, "GPIO47"),
MTK_FUNCTION(1, "NREB"),
MTK_FUNCTION(2, "IDDIG_P1")
),
- MTK_PIN(
- PINCTRL_PIN(48, "NRNB"),
+ MTK_PIN(PINCTRL_PIN(48, "NRNB"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 30),
MTK_FUNCTION(0, "GPIO48"),
MTK_FUNCTION(1, "NRNB"),
MTK_FUNCTION(2, "DRV_VBUS_P1")
),
- MTK_PIN(
- PINCTRL_PIN(49, "I2S0_DATA"),
+ MTK_PIN(PINCTRL_PIN(49, "I2S0_DATA"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 31),
MTK_FUNCTION(0, "GPIO49"),
@@ -507,8 +457,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(6, "WCN_I2S_DO"),
MTK_FUNCTION(7, "DBG_MON_B[3]")
),
- MTK_PIN(
- PINCTRL_PIN(50, "I2S2_BCK"),
+ MTK_PIN(PINCTRL_PIN(50, "I2S2_BCK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 32),
MTK_FUNCTION(0, "GPIO50"),
@@ -516,8 +465,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(3, "PCM_CLK0"),
MTK_FUNCTION(4, "DMIC_SCK1")
),
- MTK_PIN(
- PINCTRL_PIN(51, "I2S2_DATA_IN"),
+ MTK_PIN(PINCTRL_PIN(51, "I2S2_DATA_IN"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 33),
MTK_FUNCTION(0, "GPIO51"),
@@ -525,8 +473,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(3, "PCM_RX"),
MTK_FUNCTION(4, "DMIC_SCK0")
),
- MTK_PIN(
- PINCTRL_PIN(52, "I2S2_LRCK"),
+ MTK_PIN(PINCTRL_PIN(52, "I2S2_LRCK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 34),
MTK_FUNCTION(0, "GPIO52"),
@@ -534,8 +481,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(3, "PCM_SYNC"),
MTK_FUNCTION(4, "DMIC_DAT1")
),
- MTK_PIN(
- PINCTRL_PIN(53, "SPI0_CSN"),
+ MTK_PIN(PINCTRL_PIN(53, "SPI0_CSN"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 35),
MTK_FUNCTION(0, "GPIO53"),
@@ -545,8 +491,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(5, "PWM1"),
MTK_FUNCTION(7, "DBG_MON_A[7]")
),
- MTK_PIN(
- PINCTRL_PIN(54, "SPI0_CK"),
+ MTK_PIN(PINCTRL_PIN(54, "SPI0_CK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 36),
MTK_FUNCTION(0, "GPIO54"),
@@ -555,8 +500,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(4, "ADC_DAT_IN"),
MTK_FUNCTION(7, "DBG_MON_A[10]")
),
- MTK_PIN(
- PINCTRL_PIN(55, "SPI0_MI"),
+ MTK_PIN(PINCTRL_PIN(55, "SPI0_MI"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 37),
MTK_FUNCTION(0, "GPIO55"),
@@ -567,8 +511,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(5, "PWM2"),
MTK_FUNCTION(7, "DBG_MON_A[8]")
),
- MTK_PIN(
- PINCTRL_PIN(56, "SPI0_MO"),
+ MTK_PIN(PINCTRL_PIN(56, "SPI0_MO"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 38),
MTK_FUNCTION(0, "GPIO56"),
@@ -577,77 +520,67 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(3, "SPDIF_IN0"),
MTK_FUNCTION(7, "DBG_MON_A[9]")
),
- MTK_PIN(
- PINCTRL_PIN(57, "SDA1"),
+ MTK_PIN(PINCTRL_PIN(57, "SDA1"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 39),
MTK_FUNCTION(0, "GPIO57"),
MTK_FUNCTION(1, "SDA1")
),
- MTK_PIN(
- PINCTRL_PIN(58, "SCL1"),
+ MTK_PIN(PINCTRL_PIN(58, "SCL1"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 40),
MTK_FUNCTION(0, "GPIO58"),
MTK_FUNCTION(1, "SCL1")
),
- MTK_PIN(
- PINCTRL_PIN(59, "RAMBUF_I_CLK"),
+ MTK_PIN(PINCTRL_PIN(59, "RAMBUF_I_CLK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO59"),
MTK_FUNCTION(1, "RAMBUF_I_CLK")
),
- MTK_PIN(
- PINCTRL_PIN(60, "WB_RSTB"),
+ MTK_PIN(PINCTRL_PIN(60, "WB_RSTB"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 41),
MTK_FUNCTION(0, "GPIO60"),
MTK_FUNCTION(1, "WB_RSTB"),
MTK_FUNCTION(7, "DBG_MON_A[11]")
),
- MTK_PIN(
- PINCTRL_PIN(61, "F2W_DATA"),
+ MTK_PIN(PINCTRL_PIN(61, "F2W_DATA"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 42),
MTK_FUNCTION(0, "GPIO61"),
MTK_FUNCTION(1, "F2W_DATA"),
MTK_FUNCTION(7, "DBG_MON_A[16]")
),
- MTK_PIN(
- PINCTRL_PIN(62, "F2W_CLK"),
+ MTK_PIN(PINCTRL_PIN(62, "F2W_CLK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 43),
MTK_FUNCTION(0, "GPIO62"),
MTK_FUNCTION(1, "F2W_CK"),
MTK_FUNCTION(7, "DBG_MON_A[15]")
),
- MTK_PIN(
- PINCTRL_PIN(63, "WB_SCLK"),
+ MTK_PIN(PINCTRL_PIN(63, "WB_SCLK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 44),
MTK_FUNCTION(0, "GPIO63"),
MTK_FUNCTION(1, "WB_SCLK"),
MTK_FUNCTION(7, "DBG_MON_A[13]")
),
- MTK_PIN(
- PINCTRL_PIN(64, "WB_SDATA"),
+ MTK_PIN(PINCTRL_PIN(64, "WB_SDATA"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 45),
MTK_FUNCTION(0, "GPIO64"),
MTK_FUNCTION(1, "WB_SDATA"),
MTK_FUNCTION(7, "DBG_MON_A[12]")
),
- MTK_PIN(
- PINCTRL_PIN(65, "WB_SEN"),
+ MTK_PIN(PINCTRL_PIN(65, "WB_SEN"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 46),
MTK_FUNCTION(0, "GPIO65"),
MTK_FUNCTION(1, "WB_SEN"),
MTK_FUNCTION(7, "DBG_MON_A[14]")
),
- MTK_PIN(
- PINCTRL_PIN(66, "WB_CRTL0"),
+ MTK_PIN(PINCTRL_PIN(66, "WB_CRTL0"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 47),
MTK_FUNCTION(0, "GPIO66"),
@@ -655,8 +588,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(5, "DFD_NTRST_XI"),
MTK_FUNCTION(7, "DBG_MON_A[17]")
),
- MTK_PIN(
- PINCTRL_PIN(67, "WB_CRTL1"),
+ MTK_PIN(PINCTRL_PIN(67, "WB_CRTL1"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 48),
MTK_FUNCTION(0, "GPIO67"),
@@ -664,8 +596,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(5, "DFD_TMS_XI"),
MTK_FUNCTION(7, "DBG_MON_A[18]")
),
- MTK_PIN(
- PINCTRL_PIN(68, "WB_CRTL2"),
+ MTK_PIN(PINCTRL_PIN(68, "WB_CRTL2"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 49),
MTK_FUNCTION(0, "GPIO68"),
@@ -673,8 +604,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(5, "DFD_TCK_XI"),
MTK_FUNCTION(7, "DBG_MON_A[19]")
),
- MTK_PIN(
- PINCTRL_PIN(69, "WB_CRTL3"),
+ MTK_PIN(PINCTRL_PIN(69, "WB_CRTL3"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 50),
MTK_FUNCTION(0, "GPIO69"),
@@ -682,8 +612,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(5, "DFD_TDI_XI"),
MTK_FUNCTION(7, "DBG_MON_A[20]")
),
- MTK_PIN(
- PINCTRL_PIN(70, "WB_CRTL4"),
+ MTK_PIN(PINCTRL_PIN(70, "WB_CRTL4"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 51),
MTK_FUNCTION(0, "GPIO70"),
@@ -691,16 +620,14 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(5, "DFD_TDO"),
MTK_FUNCTION(7, "DBG_MON_A[21]")
),
- MTK_PIN(
- PINCTRL_PIN(71, "WB_CRTL5"),
+ MTK_PIN(PINCTRL_PIN(71, "WB_CRTL5"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 52),
MTK_FUNCTION(0, "GPIO71"),
MTK_FUNCTION(1, "WB_CRTL5"),
MTK_FUNCTION(7, "DBG_MON_A[22]")
),
- MTK_PIN(
- PINCTRL_PIN(72, "I2S0_DATA_IN"),
+ MTK_PIN(PINCTRL_PIN(72, "I2S0_DATA_IN"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 53),
MTK_FUNCTION(0, "GPIO72"),
@@ -711,8 +638,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(6, "WCN_I2S_DI"),
MTK_FUNCTION(7, "DBG_MON_B[2]")
),
- MTK_PIN(
- PINCTRL_PIN(73, "I2S0_LRCK"),
+ MTK_PIN(PINCTRL_PIN(73, "I2S0_LRCK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 54),
MTK_FUNCTION(0, "GPIO73"),
@@ -721,8 +647,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(6, "WCN_I2S_LRCK"),
MTK_FUNCTION(7, "DBG_MON_B[5]")
),
- MTK_PIN(
- PINCTRL_PIN(74, "I2S0_BCK"),
+ MTK_PIN(PINCTRL_PIN(74, "I2S0_BCK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 55),
MTK_FUNCTION(0, "GPIO74"),
@@ -731,68 +656,59 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(6, "WCN_I2S_BCK"),
MTK_FUNCTION(7, "DBG_MON_B[4]")
),
- MTK_PIN(
- PINCTRL_PIN(75, "SDA0"),
+ MTK_PIN(PINCTRL_PIN(75, "SDA0"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 56),
MTK_FUNCTION(0, "GPIO75"),
MTK_FUNCTION(1, "SDA0")
),
- MTK_PIN(
- PINCTRL_PIN(76, "SCL0"),
+ MTK_PIN(PINCTRL_PIN(76, "SCL0"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 57),
MTK_FUNCTION(0, "GPIO76"),
MTK_FUNCTION(1, "SCL0")
),
- MTK_PIN(
- PINCTRL_PIN(77, "SDA2"),
+ MTK_PIN(PINCTRL_PIN(77, "SDA2"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 58),
MTK_FUNCTION(0, "GPIO77"),
MTK_FUNCTION(1, "SDA2")
),
- MTK_PIN(
- PINCTRL_PIN(78, "SCL2"),
+ MTK_PIN(PINCTRL_PIN(78, "SCL2"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 59),
MTK_FUNCTION(0, "GPIO78"),
MTK_FUNCTION(1, "SCL2")
),
- MTK_PIN(
- PINCTRL_PIN(79, "URXD0"),
+ MTK_PIN(PINCTRL_PIN(79, "URXD0"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 60),
MTK_FUNCTION(0, "GPIO79"),
MTK_FUNCTION(1, "URXD0"),
MTK_FUNCTION(2, "UTXD0")
),
- MTK_PIN(
- PINCTRL_PIN(80, "UTXD0"),
+ MTK_PIN(PINCTRL_PIN(80, "UTXD0"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 61),
MTK_FUNCTION(0, "GPIO80"),
MTK_FUNCTION(1, "UTXD0"),
MTK_FUNCTION(2, "URXD0")
),
- MTK_PIN(
- PINCTRL_PIN(81, "URXD1"),
+ MTK_PIN(PINCTRL_PIN(81, "URXD1"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 62),
MTK_FUNCTION(0, "GPIO81"),
MTK_FUNCTION(1, "URXD1"),
MTK_FUNCTION(2, "UTXD1")
),
- MTK_PIN(
- PINCTRL_PIN(82, "UTXD1"),
+ MTK_PIN(PINCTRL_PIN(82, "UTXD1"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 63),
MTK_FUNCTION(0, "GPIO82"),
MTK_FUNCTION(1, "UTXD1"),
MTK_FUNCTION(2, "URXD1")
),
- MTK_PIN(
- PINCTRL_PIN(83, "LCM_RST"),
+ MTK_PIN(PINCTRL_PIN(83, "LCM_RST"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 64),
MTK_FUNCTION(0, "GPIO83"),
@@ -800,16 +716,14 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(2, "VDAC_CK_XI"),
MTK_FUNCTION(7, "DBG_MON_B[1]")
),
- MTK_PIN(
- PINCTRL_PIN(84, "DSI_TE"),
+ MTK_PIN(PINCTRL_PIN(84, "DSI_TE"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 65),
MTK_FUNCTION(0, "GPIO84"),
MTK_FUNCTION(1, "DSI_TE"),
MTK_FUNCTION(7, "DBG_MON_B[0]")
),
- MTK_PIN(
- PINCTRL_PIN(85, "MSDC2_CMD"),
+ MTK_PIN(PINCTRL_PIN(85, "MSDC2_CMD"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 66),
MTK_FUNCTION(0, "GPIO85"),
@@ -818,8 +732,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(3, "SDA1"),
MTK_FUNCTION(6, "I2SOUT_BCK")
),
- MTK_PIN(
- PINCTRL_PIN(86, "MSDC2_CLK"),
+ MTK_PIN(PINCTRL_PIN(86, "MSDC2_CLK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 67),
MTK_FUNCTION(0, "GPIO86"),
@@ -828,8 +741,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(3, "SCL1"),
MTK_FUNCTION(6, "I2SOUT_LRCK")
),
- MTK_PIN(
- PINCTRL_PIN(87, "MSDC2_DAT0"),
+ MTK_PIN(PINCTRL_PIN(87, "MSDC2_DAT0"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 68),
MTK_FUNCTION(0, "GPIO87"),
@@ -838,8 +750,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(5, "UTXD0"),
MTK_FUNCTION(6, "I2SOUT_DATA_OUT")
),
- MTK_PIN(
- PINCTRL_PIN(88, "MSDC2_DAT1"),
+ MTK_PIN(PINCTRL_PIN(88, "MSDC2_DAT1"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 71),
MTK_FUNCTION(0, "GPIO88"),
@@ -849,8 +760,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(5, "URXD0"),
MTK_FUNCTION(6, "PWM1")
),
- MTK_PIN(
- PINCTRL_PIN(89, "MSDC2_DAT2"),
+ MTK_PIN(PINCTRL_PIN(89, "MSDC2_DAT2"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 72),
MTK_FUNCTION(0, "GPIO89"),
@@ -860,8 +770,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(5, "UTXD1"),
MTK_FUNCTION(6, "PWM2")
),
- MTK_PIN(
- PINCTRL_PIN(90, "MSDC2_DAT3"),
+ MTK_PIN(PINCTRL_PIN(90, "MSDC2_DAT3"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 73),
MTK_FUNCTION(0, "GPIO90"),
@@ -872,78 +781,67 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(5, "URXD1"),
MTK_FUNCTION(6, "PWM3")
),
- MTK_PIN(
- PINCTRL_PIN(91, "TDN3"),
+ MTK_PIN(PINCTRL_PIN(91, "TDN3"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPI91"),
MTK_FUNCTION(1, "TDN3")
),
- MTK_PIN(
- PINCTRL_PIN(92, "TDP3"),
+ MTK_PIN(PINCTRL_PIN(92, "TDP3"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPI92"),
MTK_FUNCTION(1, "TDP3")
),
- MTK_PIN(
- PINCTRL_PIN(93, "TDN2"),
+ MTK_PIN(PINCTRL_PIN(93, "TDN2"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPI93"),
MTK_FUNCTION(1, "TDN2")
),
- MTK_PIN(
- PINCTRL_PIN(94, "TDP2"),
+ MTK_PIN(PINCTRL_PIN(94, "TDP2"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPI94"),
MTK_FUNCTION(1, "TDP2")
),
- MTK_PIN(
- PINCTRL_PIN(95, "TCN"),
+ MTK_PIN(PINCTRL_PIN(95, "TCN"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPI95"),
MTK_FUNCTION(1, "TCN")
),
- MTK_PIN(
- PINCTRL_PIN(96, "TCP"),
+ MTK_PIN(PINCTRL_PIN(96, "TCP"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPI96"),
MTK_FUNCTION(1, "TCP")
),
- MTK_PIN(
- PINCTRL_PIN(97, "TDN1"),
+ MTK_PIN(PINCTRL_PIN(97, "TDN1"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPI97"),
MTK_FUNCTION(1, "TDN1")
),
- MTK_PIN(
- PINCTRL_PIN(98, "TDP1"),
+ MTK_PIN(PINCTRL_PIN(98, "TDP1"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPI98"),
MTK_FUNCTION(1, "TDP1")
),
- MTK_PIN(
- PINCTRL_PIN(99, "TDN0"),
+ MTK_PIN(PINCTRL_PIN(99, "TDN0"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPI99"),
MTK_FUNCTION(1, "TDN0")
),
- MTK_PIN(
- PINCTRL_PIN(100, "TDP0"),
+ MTK_PIN(PINCTRL_PIN(100, "TDP0"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPI100"),
MTK_FUNCTION(1, "TDP0")
),
- MTK_PIN(
- PINCTRL_PIN(101, "SPI2_CSN"),
+ MTK_PIN(PINCTRL_PIN(101, "SPI2_CSN"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 74),
MTK_FUNCTION(0, "GPIO101"),
@@ -951,8 +849,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(3, "SCL3"),
MTK_FUNCTION(4, "KROW0")
),
- MTK_PIN(
- PINCTRL_PIN(102, "SPI2_MI"),
+ MTK_PIN(PINCTRL_PIN(102, "SPI2_MI"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 75),
MTK_FUNCTION(0, "GPIO102"),
@@ -961,8 +858,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(3, "SDA3"),
MTK_FUNCTION(4, "KROW1")
),
- MTK_PIN(
- PINCTRL_PIN(103, "SPI2_MO"),
+ MTK_PIN(PINCTRL_PIN(103, "SPI2_MO"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 76),
MTK_FUNCTION(0, "GPIO103"),
@@ -971,8 +867,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(3, "SCL3"),
MTK_FUNCTION(4, "KROW2")
),
- MTK_PIN(
- PINCTRL_PIN(104, "SPI2_CLK"),
+ MTK_PIN(PINCTRL_PIN(104, "SPI2_CLK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 77),
MTK_FUNCTION(0, "GPIO104"),
@@ -980,8 +875,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(3, "SDA3"),
MTK_FUNCTION(4, "KROW3")
),
- MTK_PIN(
- PINCTRL_PIN(105, "MSDC1_CMD"),
+ MTK_PIN(PINCTRL_PIN(105, "MSDC1_CMD"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 78),
MTK_FUNCTION(0, "GPIO105"),
@@ -991,8 +885,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(6, "I2SOUT_BCK"),
MTK_FUNCTION(7, "DBG_MON_B[27]")
),
- MTK_PIN(
- PINCTRL_PIN(106, "MSDC1_CLK"),
+ MTK_PIN(PINCTRL_PIN(106, "MSDC1_CLK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 79),
MTK_FUNCTION(0, "GPIO106"),
@@ -1002,8 +895,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(6, "I2SOUT_LRCK"),
MTK_FUNCTION(7, "DBG_MON_B[28]")
),
- MTK_PIN(
- PINCTRL_PIN(107, "MSDC1_DAT0"),
+ MTK_PIN(PINCTRL_PIN(107, "MSDC1_DAT0"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 80),
MTK_FUNCTION(0, "GPIO107"),
@@ -1013,8 +905,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(6, "I2SOUT_DATA_OUT"),
MTK_FUNCTION(7, "DBG_MON_B[26]")
),
- MTK_PIN(
- PINCTRL_PIN(108, "MSDC1_DAT1"),
+ MTK_PIN(PINCTRL_PIN(108, "MSDC1_DAT1"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 81),
MTK_FUNCTION(0, "GPIO108"),
@@ -1025,8 +916,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(6, "PWM1"),
MTK_FUNCTION(7, "DBG_MON_B[25]")
),
- MTK_PIN(
- PINCTRL_PIN(109, "MSDC1_DAT2"),
+ MTK_PIN(PINCTRL_PIN(109, "MSDC1_DAT2"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 82),
MTK_FUNCTION(0, "GPIO109"),
@@ -1037,8 +927,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(6, "PWM2"),
MTK_FUNCTION(7, "DBG_MON_B[24]")
),
- MTK_PIN(
- PINCTRL_PIN(110, "MSDC1_DAT3"),
+ MTK_PIN(PINCTRL_PIN(110, "MSDC1_DAT3"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 83),
MTK_FUNCTION(0, "GPIO110"),
@@ -1050,88 +939,77 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(6, "PWM3"),
MTK_FUNCTION(7, "DBG_MON_B[23]")
),
- MTK_PIN(
- PINCTRL_PIN(111, "MSDC0_DAT7"),
+ MTK_PIN(PINCTRL_PIN(111, "MSDC0_DAT7"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 84),
MTK_FUNCTION(0, "GPIO111"),
MTK_FUNCTION(1, "MSDC0_DAT7"),
MTK_FUNCTION(4, "NLD7")
),
- MTK_PIN(
- PINCTRL_PIN(112, "MSDC0_DAT6"),
+ MTK_PIN(PINCTRL_PIN(112, "MSDC0_DAT6"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 85),
MTK_FUNCTION(0, "GPIO112"),
MTK_FUNCTION(1, "MSDC0_DAT6"),
MTK_FUNCTION(4, "NLD6")
),
- MTK_PIN(
- PINCTRL_PIN(113, "MSDC0_DAT5"),
+ MTK_PIN(PINCTRL_PIN(113, "MSDC0_DAT5"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 86),
MTK_FUNCTION(0, "GPIO113"),
MTK_FUNCTION(1, "MSDC0_DAT5"),
MTK_FUNCTION(4, "NLD5")
),
- MTK_PIN(
- PINCTRL_PIN(114, "MSDC0_DAT4"),
+ MTK_PIN(PINCTRL_PIN(114, "MSDC0_DAT4"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 87),
MTK_FUNCTION(0, "GPIO114"),
MTK_FUNCTION(1, "MSDC0_DAT4"),
MTK_FUNCTION(4, "NLD4")
),
- MTK_PIN(
- PINCTRL_PIN(115, "MSDC0_RSTB"),
+ MTK_PIN(PINCTRL_PIN(115, "MSDC0_RSTB"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 88),
MTK_FUNCTION(0, "GPIO115"),
MTK_FUNCTION(1, "MSDC0_RSTB"),
MTK_FUNCTION(4, "NLD8")
),
- MTK_PIN(
- PINCTRL_PIN(116, "MSDC0_CMD"),
+ MTK_PIN(PINCTRL_PIN(116, "MSDC0_CMD"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 89),
MTK_FUNCTION(0, "GPIO116"),
MTK_FUNCTION(1, "MSDC0_CMD"),
MTK_FUNCTION(4, "NALE")
),
- MTK_PIN(
- PINCTRL_PIN(117, "MSDC0_CLK"),
+ MTK_PIN(PINCTRL_PIN(117, "MSDC0_CLK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 90),
MTK_FUNCTION(0, "GPIO117"),
MTK_FUNCTION(1, "MSDC0_CLK"),
MTK_FUNCTION(4, "NWEB")
),
- MTK_PIN(
- PINCTRL_PIN(118, "MSDC0_DAT3"),
+ MTK_PIN(PINCTRL_PIN(118, "MSDC0_DAT3"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 91),
MTK_FUNCTION(0, "GPIO118"),
MTK_FUNCTION(1, "MSDC0_DAT3"),
MTK_FUNCTION(4, "NLD3")
),
- MTK_PIN(
- PINCTRL_PIN(119, "MSDC0_DAT2"),
+ MTK_PIN(PINCTRL_PIN(119, "MSDC0_DAT2"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 92),
MTK_FUNCTION(0, "GPIO119"),
MTK_FUNCTION(1, "MSDC0_DAT2"),
MTK_FUNCTION(4, "NLD2")
),
- MTK_PIN(
- PINCTRL_PIN(120, "MSDC0_DAT1"),
+ MTK_PIN(PINCTRL_PIN(120, "MSDC0_DAT1"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 93),
MTK_FUNCTION(0, "GPIO120"),
MTK_FUNCTION(1, "MSDC0_DAT1"),
MTK_FUNCTION(4, "NLD1")
),
- MTK_PIN(
- PINCTRL_PIN(121, "MSDC0_DAT0"),
+ MTK_PIN(PINCTRL_PIN(121, "MSDC0_DAT0"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 94),
MTK_FUNCTION(0, "GPIO121"),
@@ -1139,8 +1017,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(4, "NLD0"),
MTK_FUNCTION(5, "WATCHDOG")
),
- MTK_PIN(
- PINCTRL_PIN(122, "CEC"),
+ MTK_PIN(PINCTRL_PIN(122, "CEC"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 95),
MTK_FUNCTION(0, "GPIO122"),
@@ -1148,8 +1025,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(4, "SDA2"),
MTK_FUNCTION(5, "URXD0")
),
- MTK_PIN(
- PINCTRL_PIN(123, "HTPLG"),
+ MTK_PIN(PINCTRL_PIN(123, "HTPLG"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 96),
MTK_FUNCTION(0, "GPIO123"),
@@ -1157,8 +1033,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(4, "SCL2"),
MTK_FUNCTION(5, "UTXD0")
),
- MTK_PIN(
- PINCTRL_PIN(124, "HDMISCK"),
+ MTK_PIN(PINCTRL_PIN(124, "HDMISCK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 97),
MTK_FUNCTION(0, "GPIO124"),
@@ -1166,8 +1041,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(4, "SDA1"),
MTK_FUNCTION(5, "PWM3")
),
- MTK_PIN(
- PINCTRL_PIN(125, "HDMISD"),
+ MTK_PIN(PINCTRL_PIN(125, "HDMISD"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 98),
MTK_FUNCTION(0, "GPIO125"),
@@ -1175,8 +1049,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(4, "SCL1"),
MTK_FUNCTION(5, "PWM4")
),
- MTK_PIN(
- PINCTRL_PIN(126, "I2S0_MCLK"),
+ MTK_PIN(PINCTRL_PIN(126, "I2S0_MCLK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 99),
MTK_FUNCTION(0, "GPIO126"),
@@ -1184,481 +1057,413 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(6, "WCN_I2S_MCLK"),
MTK_FUNCTION(7, "DBG_MON_B[6]")
),
- MTK_PIN(
- PINCTRL_PIN(127, "RAMBUF_IDATA0"),
+ MTK_PIN(PINCTRL_PIN(127, "RAMBUF_IDATA0"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO127"),
MTK_FUNCTION(1, "RAMBUF_IDATA0")
),
- MTK_PIN(
- PINCTRL_PIN(128, "RAMBUF_IDATA1"),
+ MTK_PIN(PINCTRL_PIN(128, "RAMBUF_IDATA1"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO128"),
MTK_FUNCTION(1, "RAMBUF_IDATA1")
),
- MTK_PIN(
- PINCTRL_PIN(129, "RAMBUF_IDATA2"),
+ MTK_PIN(PINCTRL_PIN(129, "RAMBUF_IDATA2"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO129"),
MTK_FUNCTION(1, "RAMBUF_IDATA2")
),
- MTK_PIN(
- PINCTRL_PIN(130, "RAMBUF_IDATA3"),
+ MTK_PIN(PINCTRL_PIN(130, "RAMBUF_IDATA3"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO130"),
MTK_FUNCTION(1, "RAMBUF_IDATA3")
),
- MTK_PIN(
- PINCTRL_PIN(131, "RAMBUF_IDATA4"),
+ MTK_PIN(PINCTRL_PIN(131, "RAMBUF_IDATA4"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO131"),
MTK_FUNCTION(1, "RAMBUF_IDATA4")
),
- MTK_PIN(
- PINCTRL_PIN(132, "RAMBUF_IDATA5"),
+ MTK_PIN(PINCTRL_PIN(132, "RAMBUF_IDATA5"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO132"),
MTK_FUNCTION(1, "RAMBUF_IDATA5")
),
- MTK_PIN(
- PINCTRL_PIN(133, "RAMBUF_IDATA6"),
+ MTK_PIN(PINCTRL_PIN(133, "RAMBUF_IDATA6"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO133"),
MTK_FUNCTION(1, "RAMBUF_IDATA6")
),
- MTK_PIN(
- PINCTRL_PIN(134, "RAMBUF_IDATA7"),
+ MTK_PIN(PINCTRL_PIN(134, "RAMBUF_IDATA7"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO134"),
MTK_FUNCTION(1, "RAMBUF_IDATA7")
),
- MTK_PIN(
- PINCTRL_PIN(135, "RAMBUF_IDATA8"),
+ MTK_PIN(PINCTRL_PIN(135, "RAMBUF_IDATA8"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO135"),
MTK_FUNCTION(1, "RAMBUF_IDATA8")
),
- MTK_PIN(
- PINCTRL_PIN(136, "RAMBUF_IDATA9"),
+ MTK_PIN(PINCTRL_PIN(136, "RAMBUF_IDATA9"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO136"),
MTK_FUNCTION(1, "RAMBUF_IDATA9")
),
- MTK_PIN(
- PINCTRL_PIN(137, "RAMBUF_IDATA10"),
+ MTK_PIN(PINCTRL_PIN(137, "RAMBUF_IDATA10"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO137"),
MTK_FUNCTION(1, "RAMBUF_IDATA10")
),
- MTK_PIN(
- PINCTRL_PIN(138, "RAMBUF_IDATA11"),
+ MTK_PIN(PINCTRL_PIN(138, "RAMBUF_IDATA11"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO138"),
MTK_FUNCTION(1, "RAMBUF_IDATA11")
),
- MTK_PIN(
- PINCTRL_PIN(139, "RAMBUF_IDATA12"),
+ MTK_PIN(PINCTRL_PIN(139, "RAMBUF_IDATA12"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO139"),
MTK_FUNCTION(1, "RAMBUF_IDATA12")
),
- MTK_PIN(
- PINCTRL_PIN(140, "RAMBUF_IDATA13"),
+ MTK_PIN(PINCTRL_PIN(140, "RAMBUF_IDATA13"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO140"),
MTK_FUNCTION(1, "RAMBUF_IDATA13")
),
- MTK_PIN(
- PINCTRL_PIN(141, "RAMBUF_IDATA14"),
+ MTK_PIN(PINCTRL_PIN(141, "RAMBUF_IDATA14"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO141"),
MTK_FUNCTION(1, "RAMBUF_IDATA14")
),
- MTK_PIN(
- PINCTRL_PIN(142, "RAMBUF_IDATA15"),
+ MTK_PIN(PINCTRL_PIN(142, "RAMBUF_IDATA15"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO142"),
MTK_FUNCTION(1, "RAMBUF_IDATA15")
),
- MTK_PIN(
- PINCTRL_PIN(143, "RAMBUF_ODATA0"),
+ MTK_PIN(PINCTRL_PIN(143, "RAMBUF_ODATA0"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO143"),
MTK_FUNCTION(1, "RAMBUF_ODATA0")
),
- MTK_PIN(
- PINCTRL_PIN(144, "RAMBUF_ODATA1"),
+ MTK_PIN(PINCTRL_PIN(144, "RAMBUF_ODATA1"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO144"),
MTK_FUNCTION(1, "RAMBUF_ODATA1")
),
- MTK_PIN(
- PINCTRL_PIN(145, "RAMBUF_ODATA2"),
+ MTK_PIN(PINCTRL_PIN(145, "RAMBUF_ODATA2"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO145"),
MTK_FUNCTION(1, "RAMBUF_ODATA2")
),
- MTK_PIN(
- PINCTRL_PIN(146, "RAMBUF_ODATA3"),
+ MTK_PIN(PINCTRL_PIN(146, "RAMBUF_ODATA3"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO146"),
MTK_FUNCTION(1, "RAMBUF_ODATA3")
),
- MTK_PIN(
- PINCTRL_PIN(147, "RAMBUF_ODATA4"),
+ MTK_PIN(PINCTRL_PIN(147, "RAMBUF_ODATA4"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO147"),
MTK_FUNCTION(1, "RAMBUF_ODATA4")
),
- MTK_PIN(
- PINCTRL_PIN(148, "RAMBUF_ODATA5"),
+ MTK_PIN(PINCTRL_PIN(148, "RAMBUF_ODATA5"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO148"),
MTK_FUNCTION(1, "RAMBUF_ODATA5")
),
- MTK_PIN(
- PINCTRL_PIN(149, "RAMBUF_ODATA6"),
+ MTK_PIN(PINCTRL_PIN(149, "RAMBUF_ODATA6"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO149"),
MTK_FUNCTION(1, "RAMBUF_ODATA6")
),
- MTK_PIN(
- PINCTRL_PIN(150, "RAMBUF_ODATA7"),
+ MTK_PIN(PINCTRL_PIN(150, "RAMBUF_ODATA7"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO150"),
MTK_FUNCTION(1, "RAMBUF_ODATA7")
),
- MTK_PIN(
- PINCTRL_PIN(151, "RAMBUF_ODATA8"),
+ MTK_PIN(PINCTRL_PIN(151, "RAMBUF_ODATA8"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO151"),
MTK_FUNCTION(1, "RAMBUF_ODATA8")
),
- MTK_PIN(
- PINCTRL_PIN(152, "RAMBUF_ODATA9"),
+ MTK_PIN(PINCTRL_PIN(152, "RAMBUF_ODATA9"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO152"),
MTK_FUNCTION(1, "RAMBUF_ODATA9")
),
- MTK_PIN(
- PINCTRL_PIN(153, "RAMBUF_ODATA10"),
+ MTK_PIN(PINCTRL_PIN(153, "RAMBUF_ODATA10"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO153"),
MTK_FUNCTION(1, "RAMBUF_ODATA10")
),
- MTK_PIN(
- PINCTRL_PIN(154, "RAMBUF_ODATA11"),
+ MTK_PIN(PINCTRL_PIN(154, "RAMBUF_ODATA11"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO154"),
MTK_FUNCTION(1, "RAMBUF_ODATA11")
),
- MTK_PIN(
- PINCTRL_PIN(155, "RAMBUF_ODATA12"),
+ MTK_PIN(PINCTRL_PIN(155, "RAMBUF_ODATA12"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO155"),
MTK_FUNCTION(1, "RAMBUF_ODATA12")
),
- MTK_PIN(
- PINCTRL_PIN(156, "RAMBUF_ODATA13"),
+ MTK_PIN(PINCTRL_PIN(156, "RAMBUF_ODATA13"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO156"),
MTK_FUNCTION(1, "RAMBUF_ODATA13")
),
- MTK_PIN(
- PINCTRL_PIN(157, "RAMBUF_ODATA14"),
+ MTK_PIN(PINCTRL_PIN(157, "RAMBUF_ODATA14"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO157"),
MTK_FUNCTION(1, "RAMBUF_ODATA14")
),
- MTK_PIN(
- PINCTRL_PIN(158, "RAMBUF_ODATA15"),
+ MTK_PIN(PINCTRL_PIN(158, "RAMBUF_ODATA15"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO158"),
MTK_FUNCTION(1, "RAMBUF_ODATA15")
),
- MTK_PIN(
- PINCTRL_PIN(159, "RAMBUF_BE0"),
+ MTK_PIN(PINCTRL_PIN(159, "RAMBUF_BE0"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO159"),
MTK_FUNCTION(1, "RAMBUF_BE0")
),
- MTK_PIN(
- PINCTRL_PIN(160, "RAMBUF_BE1"),
+ MTK_PIN(PINCTRL_PIN(160, "RAMBUF_BE1"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO160"),
MTK_FUNCTION(1, "RAMBUF_BE1")
),
- MTK_PIN(
- PINCTRL_PIN(161, "AP2PT_INT"),
+ MTK_PIN(PINCTRL_PIN(161, "AP2PT_INT"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO161"),
MTK_FUNCTION(1, "AP2PT_INT")
),
- MTK_PIN(
- PINCTRL_PIN(162, "AP2PT_INT_CLR"),
+ MTK_PIN(PINCTRL_PIN(162, "AP2PT_INT_CLR"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO162"),
MTK_FUNCTION(1, "AP2PT_INT_CLR")
),
- MTK_PIN(
- PINCTRL_PIN(163, "PT2AP_INT"),
+ MTK_PIN(PINCTRL_PIN(163, "PT2AP_INT"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO163"),
MTK_FUNCTION(1, "PT2AP_INT")
),
- MTK_PIN(
- PINCTRL_PIN(164, "PT2AP_INT_CLR"),
+ MTK_PIN(PINCTRL_PIN(164, "PT2AP_INT_CLR"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO164"),
MTK_FUNCTION(1, "PT2AP_INT_CLR")
),
- MTK_PIN(
- PINCTRL_PIN(165, "AP2UP_INT"),
+ MTK_PIN(PINCTRL_PIN(165, "AP2UP_INT"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO165"),
MTK_FUNCTION(1, "AP2UP_INT")
),
- MTK_PIN(
- PINCTRL_PIN(166, "AP2UP_INT_CLR"),
+ MTK_PIN(PINCTRL_PIN(166, "AP2UP_INT_CLR"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO166"),
MTK_FUNCTION(1, "AP2UP_INT_CLR")
),
- MTK_PIN(
- PINCTRL_PIN(167, "UP2AP_INT"),
+ MTK_PIN(PINCTRL_PIN(167, "UP2AP_INT"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO167"),
MTK_FUNCTION(1, "UP2AP_INT")
),
- MTK_PIN(
- PINCTRL_PIN(168, "UP2AP_INT_CLR"),
+ MTK_PIN(PINCTRL_PIN(168, "UP2AP_INT_CLR"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO168"),
MTK_FUNCTION(1, "UP2AP_INT_CLR")
),
- MTK_PIN(
- PINCTRL_PIN(169, "RAMBUF_ADDR0"),
+ MTK_PIN(PINCTRL_PIN(169, "RAMBUF_ADDR0"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO169"),
MTK_FUNCTION(1, "RAMBUF_ADDR0")
),
- MTK_PIN(
- PINCTRL_PIN(170, "RAMBUF_ADDR1"),
+ MTK_PIN(PINCTRL_PIN(170, "RAMBUF_ADDR1"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO170"),
MTK_FUNCTION(1, "RAMBUF_ADDR1")
),
- MTK_PIN(
- PINCTRL_PIN(171, "RAMBUF_ADDR2"),
+ MTK_PIN(PINCTRL_PIN(171, "RAMBUF_ADDR2"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO171"),
MTK_FUNCTION(1, "RAMBUF_ADDR2")
),
- MTK_PIN(
- PINCTRL_PIN(172, "RAMBUF_ADDR3"),
+ MTK_PIN(PINCTRL_PIN(172, "RAMBUF_ADDR3"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO172"),
MTK_FUNCTION(1, "RAMBUF_ADDR3")
),
- MTK_PIN(
- PINCTRL_PIN(173, "RAMBUF_ADDR4"),
+ MTK_PIN(PINCTRL_PIN(173, "RAMBUF_ADDR4"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO173"),
MTK_FUNCTION(1, "RAMBUF_ADDR4")
),
- MTK_PIN(
- PINCTRL_PIN(174, "RAMBUF_ADDR5"),
+ MTK_PIN(PINCTRL_PIN(174, "RAMBUF_ADDR5"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO174"),
MTK_FUNCTION(1, "RAMBUF_ADDR5")
),
- MTK_PIN(
- PINCTRL_PIN(175, "RAMBUF_ADDR6"),
+ MTK_PIN(PINCTRL_PIN(175, "RAMBUF_ADDR6"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO175"),
MTK_FUNCTION(1, "RAMBUF_ADDR6")
),
- MTK_PIN(
- PINCTRL_PIN(176, "RAMBUF_ADDR7"),
+ MTK_PIN(PINCTRL_PIN(176, "RAMBUF_ADDR7"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO176"),
MTK_FUNCTION(1, "RAMBUF_ADDR7")
),
- MTK_PIN(
- PINCTRL_PIN(177, "RAMBUF_ADDR8"),
+ MTK_PIN(PINCTRL_PIN(177, "RAMBUF_ADDR8"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO177"),
MTK_FUNCTION(1, "RAMBUF_ADDR8")
),
- MTK_PIN(
- PINCTRL_PIN(178, "RAMBUF_ADDR9"),
+ MTK_PIN(PINCTRL_PIN(178, "RAMBUF_ADDR9"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO178"),
MTK_FUNCTION(1, "RAMBUF_ADDR9")
),
- MTK_PIN(
- PINCTRL_PIN(179, "RAMBUF_ADDR10"),
+ MTK_PIN(PINCTRL_PIN(179, "RAMBUF_ADDR10"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO179"),
MTK_FUNCTION(1, "RAMBUF_ADDR10")
),
- MTK_PIN(
- PINCTRL_PIN(180, "RAMBUF_RW"),
+ MTK_PIN(PINCTRL_PIN(180, "RAMBUF_RW"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO180"),
MTK_FUNCTION(1, "RAMBUF_RW")
),
- MTK_PIN(
- PINCTRL_PIN(181, "RAMBUF_LAST"),
+ MTK_PIN(PINCTRL_PIN(181, "RAMBUF_LAST"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO181"),
MTK_FUNCTION(1, "RAMBUF_LAST")
),
- MTK_PIN(
- PINCTRL_PIN(182, "RAMBUF_HP"),
+ MTK_PIN(PINCTRL_PIN(182, "RAMBUF_HP"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO182"),
MTK_FUNCTION(1, "RAMBUF_HP")
),
- MTK_PIN(
- PINCTRL_PIN(183, "RAMBUF_REQ"),
+ MTK_PIN(PINCTRL_PIN(183, "RAMBUF_REQ"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO183"),
MTK_FUNCTION(1, "RAMBUF_REQ")
),
- MTK_PIN(
- PINCTRL_PIN(184, "RAMBUF_ALE"),
+ MTK_PIN(PINCTRL_PIN(184, "RAMBUF_ALE"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO184"),
MTK_FUNCTION(1, "RAMBUF_ALE")
),
- MTK_PIN(
- PINCTRL_PIN(185, "RAMBUF_DLE"),
+ MTK_PIN(PINCTRL_PIN(185, "RAMBUF_DLE"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO185"),
MTK_FUNCTION(1, "RAMBUF_DLE")
),
- MTK_PIN(
- PINCTRL_PIN(186, "RAMBUF_WDLE"),
+ MTK_PIN(PINCTRL_PIN(186, "RAMBUF_WDLE"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO186"),
MTK_FUNCTION(1, "RAMBUF_WDLE")
),
- MTK_PIN(
- PINCTRL_PIN(187, "RAMBUF_O_CLK"),
+ MTK_PIN(PINCTRL_PIN(187, "RAMBUF_O_CLK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO187"),
MTK_FUNCTION(1, "RAMBUF_O_CLK")
),
- MTK_PIN(
- PINCTRL_PIN(188, "I2S2_MCLK"),
+ MTK_PIN(PINCTRL_PIN(188, "I2S2_MCLK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 100),
MTK_FUNCTION(0, "GPIO188"),
MTK_FUNCTION(1, "I2S2_MCLK")
),
- MTK_PIN(
- PINCTRL_PIN(189, "I2S3_DATA"),
+ MTK_PIN(PINCTRL_PIN(189, "I2S3_DATA"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 101),
MTK_FUNCTION(0, "GPIO189"),
MTK_FUNCTION(2, "I2S3_DATA_BYPS"),
MTK_FUNCTION(3, "PCM_TX")
),
- MTK_PIN(
- PINCTRL_PIN(190, "I2S3_DATA_IN"),
+ MTK_PIN(PINCTRL_PIN(190, "I2S3_DATA_IN"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 102),
MTK_FUNCTION(0, "GPIO190"),
MTK_FUNCTION(1, "I2S3_DATA_IN"),
MTK_FUNCTION(3, "PCM_RX")
),
- MTK_PIN(
- PINCTRL_PIN(191, "I2S3_BCK"),
+ MTK_PIN(PINCTRL_PIN(191, "I2S3_BCK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 103),
MTK_FUNCTION(0, "GPIO191"),
MTK_FUNCTION(1, "I2S3_BCK"),
MTK_FUNCTION(3, "PCM_CLK0")
),
- MTK_PIN(
- PINCTRL_PIN(192, "I2S3_LRCK"),
+ MTK_PIN(PINCTRL_PIN(192, "I2S3_LRCK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 104),
MTK_FUNCTION(0, "GPIO192"),
MTK_FUNCTION(1, "I2S3_LRCK"),
MTK_FUNCTION(3, "PCM_SYNC")
),
- MTK_PIN(
- PINCTRL_PIN(193, "I2S3_MCLK"),
+ MTK_PIN(PINCTRL_PIN(193, "I2S3_MCLK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 105),
MTK_FUNCTION(0, "GPIO193"),
MTK_FUNCTION(1, "I2S3_MCLK")
),
- MTK_PIN(
- PINCTRL_PIN(194, "I2S4_DATA"),
+ MTK_PIN(PINCTRL_PIN(194, "I2S4_DATA"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 106),
MTK_FUNCTION(0, "GPIO194"),
@@ -1666,39 +1471,34 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(2, "I2S4_DATA_BYPS"),
MTK_FUNCTION(3, "PCM_TX")
),
- MTK_PIN(
- PINCTRL_PIN(195, "I2S4_DATA_IN"),
+ MTK_PIN(PINCTRL_PIN(195, "I2S4_DATA_IN"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 107),
MTK_FUNCTION(0, "GPIO195"),
MTK_FUNCTION(1, "I2S4_DATA_IN"),
MTK_FUNCTION(3, "PCM_RX")
),
- MTK_PIN(
- PINCTRL_PIN(196, "I2S4_BCK"),
+ MTK_PIN(PINCTRL_PIN(196, "I2S4_BCK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 108),
MTK_FUNCTION(0, "GPIO196"),
MTK_FUNCTION(1, "I2S4_BCK"),
MTK_FUNCTION(3, "PCM_CLK0")
),
- MTK_PIN(
- PINCTRL_PIN(197, "I2S4_LRCK"),
+ MTK_PIN(PINCTRL_PIN(197, "I2S4_LRCK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 109),
MTK_FUNCTION(0, "GPIO197"),
MTK_FUNCTION(1, "I2S4_LRCK"),
MTK_FUNCTION(3, "PCM_SYNC")
),
- MTK_PIN(
- PINCTRL_PIN(198, "I2S4_MCLK"),
+ MTK_PIN(PINCTRL_PIN(198, "I2S4_MCLK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 110),
MTK_FUNCTION(0, "GPIO198"),
MTK_FUNCTION(1, "I2S4_MCLK")
),
- MTK_PIN(
- PINCTRL_PIN(199, "SPI1_CLK"),
+ MTK_PIN(PINCTRL_PIN(199, "SPI1_CLK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 111),
MTK_FUNCTION(0, "GPIO199"),
@@ -1707,8 +1507,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(4, "KCOL3"),
MTK_FUNCTION(7, "DBG_MON_B[15]")
),
- MTK_PIN(
- PINCTRL_PIN(200, "SPDIF_OUT"),
+ MTK_PIN(PINCTRL_PIN(200, "SPDIF_OUT"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 112),
MTK_FUNCTION(0, "GPIO200"),
@@ -1717,8 +1516,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(6, "URXD2"),
MTK_FUNCTION(7, "DBG_MON_B[16]")
),
- MTK_PIN(
- PINCTRL_PIN(201, "SPDIF_IN0"),
+ MTK_PIN(PINCTRL_PIN(201, "SPDIF_IN0"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 113),
MTK_FUNCTION(0, "GPIO201"),
@@ -1727,15 +1525,13 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(6, "UTXD2"),
MTK_FUNCTION(7, "DBG_MON_B[17]")
),
- MTK_PIN(
- PINCTRL_PIN(202, "SPDIF_IN1"),
+ MTK_PIN(PINCTRL_PIN(202, "SPDIF_IN1"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 114),
MTK_FUNCTION(0, "GPIO202"),
MTK_FUNCTION(1, "SPDIF_IN1")
),
- MTK_PIN(
- PINCTRL_PIN(203, "PWM0"),
+ MTK_PIN(PINCTRL_PIN(203, "PWM0"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 115),
MTK_FUNCTION(0, "GPIO203"),
@@ -1745,8 +1541,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(7, "DBG_MON_B[18]"),
MTK_FUNCTION(9, "I2S2_DATA")
),
- MTK_PIN(
- PINCTRL_PIN(204, "PWM1"),
+ MTK_PIN(PINCTRL_PIN(204, "PWM1"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 116),
MTK_FUNCTION(0, "GPIO204"),
@@ -1756,8 +1551,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(7, "DBG_MON_B[19]"),
MTK_FUNCTION(9, "I2S3_DATA")
),
- MTK_PIN(
- PINCTRL_PIN(205, "PWM2"),
+ MTK_PIN(PINCTRL_PIN(205, "PWM2"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 117),
MTK_FUNCTION(0, "GPIO205"),
@@ -1766,8 +1560,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(5, "G1_TXD0"),
MTK_FUNCTION(7, "DBG_MON_B[20]")
),
- MTK_PIN(
- PINCTRL_PIN(206, "PWM3"),
+ MTK_PIN(PINCTRL_PIN(206, "PWM3"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 118),
MTK_FUNCTION(0, "GPIO206"),
@@ -1777,8 +1570,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(5, "G1_TXC"),
MTK_FUNCTION(7, "DBG_MON_B[21]")
),
- MTK_PIN(
- PINCTRL_PIN(207, "PWM4"),
+ MTK_PIN(PINCTRL_PIN(207, "PWM4"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 119),
MTK_FUNCTION(0, "GPIO207"),
@@ -1788,8 +1580,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(5, "G1_RXC"),
MTK_FUNCTION(7, "DBG_MON_B[22]")
),
- MTK_PIN(
- PINCTRL_PIN(208, "AUD_EXT_CK1"),
+ MTK_PIN(PINCTRL_PIN(208, "AUD_EXT_CK1"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 120),
MTK_FUNCTION(0, "GPIO208"),
@@ -1802,8 +1593,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(7, "DBG_MON_A[31]"),
MTK_FUNCTION(11, "PCIE0_PERST_N")
),
- MTK_PIN(
- PINCTRL_PIN(209, "AUD_EXT_CK2"),
+ MTK_PIN(PINCTRL_PIN(209, "AUD_EXT_CK2"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 121),
MTK_FUNCTION(0, "GPIO209"),
@@ -1815,190 +1605,163 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(7, "DBG_MON_A[32]"),
MTK_FUNCTION(11, "PCIE1_PERST_N")
),
- MTK_PIN(
- PINCTRL_PIN(210, "AUD_CLOCK"),
+ MTK_PIN(PINCTRL_PIN(210, "AUD_CLOCK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO210"),
MTK_FUNCTION(1, "AUD_CLOCK")
),
- MTK_PIN(
- PINCTRL_PIN(211, "DVP_RESET"),
+ MTK_PIN(PINCTRL_PIN(211, "DVP_RESET"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO211"),
MTK_FUNCTION(1, "DVP_RESET")
),
- MTK_PIN(
- PINCTRL_PIN(212, "DVP_CLOCK"),
+ MTK_PIN(PINCTRL_PIN(212, "DVP_CLOCK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO212"),
MTK_FUNCTION(1, "DVP_CLOCK")
),
- MTK_PIN(
- PINCTRL_PIN(213, "DVP_CS"),
+ MTK_PIN(PINCTRL_PIN(213, "DVP_CS"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO213"),
MTK_FUNCTION(1, "DVP_CS")
),
- MTK_PIN(
- PINCTRL_PIN(214, "DVP_CK"),
+ MTK_PIN(PINCTRL_PIN(214, "DVP_CK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO214"),
MTK_FUNCTION(1, "DVP_CK")
),
- MTK_PIN(
- PINCTRL_PIN(215, "DVP_DI"),
+ MTK_PIN(PINCTRL_PIN(215, "DVP_DI"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO215"),
MTK_FUNCTION(1, "DVP_DI")
),
- MTK_PIN(
- PINCTRL_PIN(216, "DVP_DO"),
+ MTK_PIN(PINCTRL_PIN(216, "DVP_DO"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO216"),
MTK_FUNCTION(1, "DVP_DO")
),
- MTK_PIN(
- PINCTRL_PIN(217, "AP_CS"),
+ MTK_PIN(PINCTRL_PIN(217, "AP_CS"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO217"),
MTK_FUNCTION(1, "AP_CS")
),
- MTK_PIN(
- PINCTRL_PIN(218, "AP_CK"),
+ MTK_PIN(PINCTRL_PIN(218, "AP_CK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO218"),
MTK_FUNCTION(1, "AP_CK")
),
- MTK_PIN(
- PINCTRL_PIN(219, "AP_DI"),
+ MTK_PIN(PINCTRL_PIN(219, "AP_DI"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO219"),
MTK_FUNCTION(1, "AP_DI")
),
- MTK_PIN(
- PINCTRL_PIN(220, "AP_DO"),
+ MTK_PIN(PINCTRL_PIN(220, "AP_DO"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO220"),
MTK_FUNCTION(1, "AP_DO")
),
- MTK_PIN(
- PINCTRL_PIN(221, "DVD_BCLK"),
+ MTK_PIN(PINCTRL_PIN(221, "DVD_BCLK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO221"),
MTK_FUNCTION(1, "DVD_BCLK")
),
- MTK_PIN(
- PINCTRL_PIN(222, "T8032_CLK"),
+ MTK_PIN(PINCTRL_PIN(222, "T8032_CLK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO222"),
MTK_FUNCTION(1, "T8032_CLK")
),
- MTK_PIN(
- PINCTRL_PIN(223, "AP_BCLK"),
+ MTK_PIN(PINCTRL_PIN(223, "AP_BCLK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO223"),
MTK_FUNCTION(1, "AP_BCLK")
),
- MTK_PIN(
- PINCTRL_PIN(224, "HOST_CS"),
+ MTK_PIN(PINCTRL_PIN(224, "HOST_CS"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO224"),
MTK_FUNCTION(1, "HOST_CS")
),
- MTK_PIN(
- PINCTRL_PIN(225, "HOST_CK"),
+ MTK_PIN(PINCTRL_PIN(225, "HOST_CK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO225"),
MTK_FUNCTION(1, "HOST_CK")
),
- MTK_PIN(
- PINCTRL_PIN(226, "HOST_DO0"),
+ MTK_PIN(PINCTRL_PIN(226, "HOST_DO0"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO226"),
MTK_FUNCTION(1, "HOST_DO0")
),
- MTK_PIN(
- PINCTRL_PIN(227, "HOST_DO1"),
+ MTK_PIN(PINCTRL_PIN(227, "HOST_DO1"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO227"),
MTK_FUNCTION(1, "HOST_DO1")
),
- MTK_PIN(
- PINCTRL_PIN(228, "SLV_CS"),
+ MTK_PIN(PINCTRL_PIN(228, "SLV_CS"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO228"),
MTK_FUNCTION(1, "SLV_CS")
),
- MTK_PIN(
- PINCTRL_PIN(229, "SLV_CK"),
+ MTK_PIN(PINCTRL_PIN(229, "SLV_CK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO229"),
MTK_FUNCTION(1, "SLV_CK")
),
- MTK_PIN(
- PINCTRL_PIN(230, "SLV_DI0"),
+ MTK_PIN(PINCTRL_PIN(230, "SLV_DI0"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO230"),
MTK_FUNCTION(1, "SLV_DI0")
),
- MTK_PIN(
- PINCTRL_PIN(231, "SLV_DI1"),
+ MTK_PIN(PINCTRL_PIN(231, "SLV_DI1"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO231"),
MTK_FUNCTION(1, "SLV_DI1")
),
- MTK_PIN(
- PINCTRL_PIN(232, "AP2DSP_INT"),
+ MTK_PIN(PINCTRL_PIN(232, "AP2DSP_INT"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO232"),
MTK_FUNCTION(1, "AP2DSP_INT")
),
- MTK_PIN(
- PINCTRL_PIN(233, "AP2DSP_INT_CLR"),
+ MTK_PIN(PINCTRL_PIN(233, "AP2DSP_INT_CLR"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO233"),
MTK_FUNCTION(1, "AP2DSP_INT_CLR")
),
- MTK_PIN(
- PINCTRL_PIN(234, "DSP2AP_INT"),
+ MTK_PIN(PINCTRL_PIN(234, "DSP2AP_INT"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO234"),
MTK_FUNCTION(1, "DSP2AP_INT")
),
- MTK_PIN(
- PINCTRL_PIN(235, "DSP2AP_INT_CLR"),
+ MTK_PIN(PINCTRL_PIN(235, "DSP2AP_INT_CLR"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO235"),
MTK_FUNCTION(1, "DSP2AP_INT_CLR")
),
- MTK_PIN(
- PINCTRL_PIN(236, "EXT_SDIO3"),
+ MTK_PIN(PINCTRL_PIN(236, "EXT_SDIO3"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 122),
MTK_FUNCTION(0, "GPIO236"),
@@ -2006,46 +1769,40 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(2, "IDDIG"),
MTK_FUNCTION(7, "DBG_MON_A[1]")
),
- MTK_PIN(
- PINCTRL_PIN(237, "EXT_SDIO2"),
+ MTK_PIN(PINCTRL_PIN(237, "EXT_SDIO2"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 123),
MTK_FUNCTION(0, "GPIO237"),
MTK_FUNCTION(1, "EXT_SDIO2"),
MTK_FUNCTION(2, "DRV_VBUS")
),
- MTK_PIN(
- PINCTRL_PIN(238, "EXT_SDIO1"),
+ MTK_PIN(PINCTRL_PIN(238, "EXT_SDIO1"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 124),
MTK_FUNCTION(0, "GPIO238"),
MTK_FUNCTION(1, "EXT_SDIO1"),
MTK_FUNCTION(2, "IDDIG_P1")
),
- MTK_PIN(
- PINCTRL_PIN(239, "EXT_SDIO0"),
+ MTK_PIN(PINCTRL_PIN(239, "EXT_SDIO0"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 125),
MTK_FUNCTION(0, "GPIO239"),
MTK_FUNCTION(1, "EXT_SDIO0"),
MTK_FUNCTION(2, "DRV_VBUS_P1")
),
- MTK_PIN(
- PINCTRL_PIN(240, "EXT_XCS"),
+ MTK_PIN(PINCTRL_PIN(240, "EXT_XCS"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 126),
MTK_FUNCTION(0, "GPIO240"),
MTK_FUNCTION(1, "EXT_XCS")
),
- MTK_PIN(
- PINCTRL_PIN(241, "EXT_SCK"),
+ MTK_PIN(PINCTRL_PIN(241, "EXT_SCK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 127),
MTK_FUNCTION(0, "GPIO241"),
MTK_FUNCTION(1, "EXT_SCK")
),
- MTK_PIN(
- PINCTRL_PIN(242, "URTS2"),
+ MTK_PIN(PINCTRL_PIN(242, "URTS2"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 128),
MTK_FUNCTION(0, "GPIO242"),
@@ -2055,8 +1812,7 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(4, "SCL1"),
MTK_FUNCTION(7, "DBG_MON_B[32]")
),
- MTK_PIN(
- PINCTRL_PIN(243, "UCTS2"),
+ MTK_PIN(PINCTRL_PIN(243, "UCTS2"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 129),
MTK_FUNCTION(0, "GPIO243"),
@@ -2066,265 +1822,229 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(4, "SDA1"),
MTK_FUNCTION(7, "DBG_MON_A[6]")
),
- MTK_PIN(
- PINCTRL_PIN(244, "HDMI_SDA_RX"),
+ MTK_PIN(PINCTRL_PIN(244, "HDMI_SDA_RX"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 130),
MTK_FUNCTION(0, "GPIO244"),
MTK_FUNCTION(1, "HDMI_SDA_RX")
),
- MTK_PIN(
- PINCTRL_PIN(245, "HDMI_SCL_RX"),
+ MTK_PIN(PINCTRL_PIN(245, "HDMI_SCL_RX"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 131),
MTK_FUNCTION(0, "GPIO245"),
MTK_FUNCTION(1, "HDMI_SCL_RX")
),
- MTK_PIN(
- PINCTRL_PIN(246, "MHL_SENCE"),
+ MTK_PIN(PINCTRL_PIN(246, "MHL_SENCE"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 132),
MTK_FUNCTION(0, "GPIO246")
),
- MTK_PIN(
- PINCTRL_PIN(247, "HDMI_HPD_CBUS_RX"),
+ MTK_PIN(PINCTRL_PIN(247, "HDMI_HPD_CBUS_RX"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 69),
MTK_FUNCTION(0, "GPIO247"),
MTK_FUNCTION(1, "HDMI_HPD_RX")
),
- MTK_PIN(
- PINCTRL_PIN(248, "HDMI_TESTOUTP_RX"),
+ MTK_PIN(PINCTRL_PIN(248, "HDMI_TESTOUTP_RX"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 133),
MTK_FUNCTION(0, "GPIO248"),
MTK_FUNCTION(1, "HDMI_TESTOUTP_RX")
),
- MTK_PIN(
- PINCTRL_PIN(249, "MSDC0E_RSTB"),
+ MTK_PIN(PINCTRL_PIN(249, "MSDC0E_RSTB"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 134),
MTK_FUNCTION(0, "GPIO249"),
MTK_FUNCTION(1, "MSDC0E_RSTB")
),
- MTK_PIN(
- PINCTRL_PIN(250, "MSDC0E_DAT7"),
+ MTK_PIN(PINCTRL_PIN(250, "MSDC0E_DAT7"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 135),
MTK_FUNCTION(0, "GPIO250"),
MTK_FUNCTION(1, "MSDC3_DAT7"),
MTK_FUNCTION(6, "PCIE0_CLKREQ_N")
),
- MTK_PIN(
- PINCTRL_PIN(251, "MSDC0E_DAT6"),
+ MTK_PIN(PINCTRL_PIN(251, "MSDC0E_DAT6"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 136),
MTK_FUNCTION(0, "GPIO251"),
MTK_FUNCTION(1, "MSDC3_DAT6"),
MTK_FUNCTION(6, "PCIE0_WAKE_N")
),
- MTK_PIN(
- PINCTRL_PIN(252, "MSDC0E_DAT5"),
+ MTK_PIN(PINCTRL_PIN(252, "MSDC0E_DAT5"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 137),
MTK_FUNCTION(0, "GPIO252"),
MTK_FUNCTION(1, "MSDC3_DAT5"),
MTK_FUNCTION(6, "PCIE1_CLKREQ_N")
),
- MTK_PIN(
- PINCTRL_PIN(253, "MSDC0E_DAT4"),
+ MTK_PIN(PINCTRL_PIN(253, "MSDC0E_DAT4"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 138),
MTK_FUNCTION(0, "GPIO253"),
MTK_FUNCTION(1, "MSDC3_DAT4"),
MTK_FUNCTION(6, "PCIE1_WAKE_N")
),
- MTK_PIN(
- PINCTRL_PIN(254, "MSDC0E_DAT3"),
+ MTK_PIN(PINCTRL_PIN(254, "MSDC0E_DAT3"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 139),
MTK_FUNCTION(0, "GPIO254"),
MTK_FUNCTION(1, "MSDC3_DAT3"),
MTK_FUNCTION(6, "PCIE2_CLKREQ_N")
),
- MTK_PIN(
- PINCTRL_PIN(255, "MSDC0E_DAT2"),
+ MTK_PIN(PINCTRL_PIN(255, "MSDC0E_DAT2"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 140),
MTK_FUNCTION(0, "GPIO255"),
MTK_FUNCTION(1, "MSDC3_DAT2"),
MTK_FUNCTION(6, "PCIE2_WAKE_N")
),
- MTK_PIN(
- PINCTRL_PIN(256, "MSDC0E_DAT1"),
+ MTK_PIN(PINCTRL_PIN(256, "MSDC0E_DAT1"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 141),
MTK_FUNCTION(0, "GPIO256"),
MTK_FUNCTION(1, "MSDC3_DAT1")
),
- MTK_PIN(
- PINCTRL_PIN(257, "MSDC0E_DAT0"),
+ MTK_PIN(PINCTRL_PIN(257, "MSDC0E_DAT0"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 142),
MTK_FUNCTION(0, "GPIO257"),
MTK_FUNCTION(1, "MSDC3_DAT0")
),
- MTK_PIN(
- PINCTRL_PIN(258, "MSDC0E_CMD"),
+ MTK_PIN(PINCTRL_PIN(258, "MSDC0E_CMD"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 143),
MTK_FUNCTION(0, "GPIO258"),
MTK_FUNCTION(1, "MSDC3_CMD")
),
- MTK_PIN(
- PINCTRL_PIN(259, "MSDC0E_CLK"),
+ MTK_PIN(PINCTRL_PIN(259, "MSDC0E_CLK"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 144),
MTK_FUNCTION(0, "GPIO259"),
MTK_FUNCTION(1, "MSDC3_CLK")
),
- MTK_PIN(
- PINCTRL_PIN(260, "MSDC0E_DSL"),
+ MTK_PIN(PINCTRL_PIN(260, "MSDC0E_DSL"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 145),
MTK_FUNCTION(0, "GPIO260"),
MTK_FUNCTION(1, "MSDC3_DSL")
),
- MTK_PIN(
- PINCTRL_PIN(261, "MSDC1_INS"),
+ MTK_PIN(PINCTRL_PIN(261, "MSDC1_INS"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 146),
MTK_FUNCTION(0, "GPIO261"),
MTK_FUNCTION(1, "MSDC1_INS"),
MTK_FUNCTION(7, "DBG_MON_B[29]")
),
- MTK_PIN(
- PINCTRL_PIN(262, "G2_TXEN"),
+ MTK_PIN(PINCTRL_PIN(262, "G2_TXEN"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 8),
MTK_FUNCTION(0, "GPIO262"),
MTK_FUNCTION(1, "G2_TXEN")
),
- MTK_PIN(
- PINCTRL_PIN(263, "G2_TXD3"),
+ MTK_PIN(PINCTRL_PIN(263, "G2_TXD3"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 9),
MTK_FUNCTION(0, "GPIO263"),
MTK_FUNCTION(1, "G2_TXD3"),
MTK_FUNCTION(6, "ANT_SEL5")
),
- MTK_PIN(
- PINCTRL_PIN(264, "G2_TXD2"),
+ MTK_PIN(PINCTRL_PIN(264, "G2_TXD2"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 10),
MTK_FUNCTION(0, "GPIO264"),
MTK_FUNCTION(1, "G2_TXD2"),
MTK_FUNCTION(6, "ANT_SEL4")
),
- MTK_PIN(
- PINCTRL_PIN(265, "G2_TXD1"),
+ MTK_PIN(PINCTRL_PIN(265, "G2_TXD1"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 11),
MTK_FUNCTION(0, "GPIO265"),
MTK_FUNCTION(1, "G2_TXD1"),
MTK_FUNCTION(6, "ANT_SEL3")
),
- MTK_PIN(
- PINCTRL_PIN(266, "G2_TXD0"),
+ MTK_PIN(PINCTRL_PIN(266, "G2_TXD0"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO266"),
MTK_FUNCTION(1, "G2_TXD0"),
MTK_FUNCTION(6, "ANT_SEL2")
),
- MTK_PIN(
- PINCTRL_PIN(267, "G2_TXC"),
+ MTK_PIN(PINCTRL_PIN(267, "G2_TXC"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO267"),
MTK_FUNCTION(1, "G2_TXC")
),
- MTK_PIN(
- PINCTRL_PIN(268, "G2_RXC"),
+ MTK_PIN(PINCTRL_PIN(268, "G2_RXC"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO268"),
MTK_FUNCTION(1, "G2_RXC")
),
- MTK_PIN(
- PINCTRL_PIN(269, "G2_RXD0"),
+ MTK_PIN(PINCTRL_PIN(269, "G2_RXD0"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO269"),
MTK_FUNCTION(1, "G2_RXD0")
),
- MTK_PIN(
- PINCTRL_PIN(270, "G2_RXD1"),
+ MTK_PIN(PINCTRL_PIN(270, "G2_RXD1"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO270"),
MTK_FUNCTION(1, "G2_RXD1")
),
- MTK_PIN(
- PINCTRL_PIN(271, "G2_RXD2"),
+ MTK_PIN(PINCTRL_PIN(271, "G2_RXD2"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO271"),
MTK_FUNCTION(1, "G2_RXD2")
),
- MTK_PIN(
- PINCTRL_PIN(272, "G2_RXD3"),
+ MTK_PIN(PINCTRL_PIN(272, "G2_RXD3"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO272"),
MTK_FUNCTION(1, "G2_RXD3")
),
- MTK_PIN(
- PINCTRL_PIN(273, "ESW_INT"),
+ MTK_PIN(PINCTRL_PIN(273, "ESW_INT"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 168),
MTK_FUNCTION(0, "GPIO273"),
MTK_FUNCTION(1, "ESW_INT")
),
- MTK_PIN(
- PINCTRL_PIN(274, "G2_RXDV"),
+ MTK_PIN(PINCTRL_PIN(274, "G2_RXDV"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO274"),
MTK_FUNCTION(1, "G2_RXDV")
),
- MTK_PIN(
- PINCTRL_PIN(275, "MDC"),
+ MTK_PIN(PINCTRL_PIN(275, "MDC"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO275"),
MTK_FUNCTION(1, "MDC"),
MTK_FUNCTION(6, "ANT_SEL0")
),
- MTK_PIN(
- PINCTRL_PIN(276, "MDIO"),
+ MTK_PIN(PINCTRL_PIN(276, "MDIO"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO276"),
MTK_FUNCTION(1, "MDIO"),
MTK_FUNCTION(6, "ANT_SEL1")
),
- MTK_PIN(
- PINCTRL_PIN(277, "ESW_RST"),
+ MTK_PIN(PINCTRL_PIN(277, "ESW_RST"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO277"),
MTK_FUNCTION(1, "ESW_RST")
),
- MTK_PIN(
- PINCTRL_PIN(278, "JTAG_RESET"),
+ MTK_PIN(PINCTRL_PIN(278, "JTAG_RESET"),
NULL, "mt2701",
MTK_EINT_FUNCTION(0, 147),
MTK_FUNCTION(0, "GPIO278"),
MTK_FUNCTION(1, "JTAG_RESET")
),
- MTK_PIN(
- PINCTRL_PIN(279, "USB3_RES_BOND"),
+ MTK_PIN(PINCTRL_PIN(279, "USB3_RES_BOND"),
NULL, "mt2701",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO279"),
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h
new file mode 100644
index 000000000000..ba2356a8ab89
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h
@@ -0,0 +1,1757 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
+ *
+ */
+#ifndef PINCTRL_MTK_MT2712_H
+#define PINCTRL_MTK_MT2712_H
+
+#include <linux/pinctrl/pinctrl.h>
+#include "pinctrl-mtk-common.h"
+
+static const struct mtk_desc_pin mtk_pins_mt2712[] = {
+ MTK_PIN(PINCTRL_PIN(0, "EINT0"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 6),
+ MTK_FUNCTION(0, "GPIO0"),
+ MTK_FUNCTION(1, "EINT0"),
+ MTK_FUNCTION(2, "MBIST_DIAG_SCANOUT"),
+ MTK_FUNCTION(3, "DSIA_TE"),
+ MTK_FUNCTION(4, "DSIC_TE"),
+ MTK_FUNCTION(5, "DIN_D3"),
+ MTK_FUNCTION(6, "PURE_HW_PROTECT")
+ ),
+ MTK_PIN(PINCTRL_PIN(1, "EINT1"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 7),
+ MTK_FUNCTION(0, "GPIO1"),
+ MTK_FUNCTION(1, "EINT1"),
+ MTK_FUNCTION(2, "IR_IN"),
+ MTK_FUNCTION(3, "DSIB_TE"),
+ MTK_FUNCTION(4, "DSID_TE"),
+ MTK_FUNCTION(5, "DIN_D4")
+ ),
+ MTK_PIN(PINCTRL_PIN(2, "EINT2"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 8),
+ MTK_FUNCTION(0, "GPIO2"),
+ MTK_FUNCTION(1, "EINT2"),
+ MTK_FUNCTION(2, "IR_IN"),
+ MTK_FUNCTION(3, "LCM_RST1"),
+ MTK_FUNCTION(5, "DIN_D5")
+ ),
+ MTK_PIN(PINCTRL_PIN(3, "EINT3"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 9),
+ MTK_FUNCTION(0, "GPIO3"),
+ MTK_FUNCTION(1, "EINT3"),
+ MTK_FUNCTION(2, "IR_IN"),
+ MTK_FUNCTION(3, "LCM_RST0"),
+ MTK_FUNCTION(5, "DIN_D6")
+ ),
+ MTK_PIN(PINCTRL_PIN(4, "PWM0"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 10),
+ MTK_FUNCTION(0, "GPIO4"),
+ MTK_FUNCTION(1, "PWM0"),
+ MTK_FUNCTION(2, "DISP0_PWM"),
+ MTK_FUNCTION(3, "DISP1_PWM"),
+ MTK_FUNCTION(5, "DIN_CLK")
+ ),
+ MTK_PIN(PINCTRL_PIN(5, "PWM1"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 11),
+ MTK_FUNCTION(0, "GPIO5"),
+ MTK_FUNCTION(1, "PWM1"),
+ MTK_FUNCTION(2, "DISP1_PWM"),
+ MTK_FUNCTION(3, "DISP0_PWM"),
+ MTK_FUNCTION(5, "DIN_VSYNC")
+ ),
+ MTK_PIN(PINCTRL_PIN(6, "PWM2"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 12),
+ MTK_FUNCTION(0, "GPIO6"),
+ MTK_FUNCTION(1, "PWM2"),
+ MTK_FUNCTION(2, "DISP0_PWM"),
+ MTK_FUNCTION(3, "DISP1_PWM"),
+ MTK_FUNCTION(4, "DISP2_PWM"),
+ MTK_FUNCTION(5, "DIN_HSYNC")
+ ),
+ MTK_PIN(PINCTRL_PIN(7, "PWM3"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 13),
+ MTK_FUNCTION(0, "GPIO7"),
+ MTK_FUNCTION(1, "PWM3"),
+ MTK_FUNCTION(2, "DISP1_PWM"),
+ MTK_FUNCTION(3, "DISP0_PWM"),
+ MTK_FUNCTION(4, "LCM_RST2"),
+ MTK_FUNCTION(5, "DIN_D0")
+ ),
+ MTK_PIN(PINCTRL_PIN(8, "PWM4"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 14),
+ MTK_FUNCTION(0, "GPIO8"),
+ MTK_FUNCTION(1, "PWM4"),
+ MTK_FUNCTION(2, "DISP0_PWM"),
+ MTK_FUNCTION(3, "DISP1_PWM"),
+ MTK_FUNCTION(4, "DSIA_TE"),
+ MTK_FUNCTION(5, "DIN_D1")
+ ),
+ MTK_PIN(PINCTRL_PIN(9, "PWM5"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 15),
+ MTK_FUNCTION(0, "GPIO9"),
+ MTK_FUNCTION(1, "PWM5"),
+ MTK_FUNCTION(2, "DISP1_PWM"),
+ MTK_FUNCTION(3, "DISP0_PWM"),
+ MTK_FUNCTION(4, "DSIB_TE"),
+ MTK_FUNCTION(5, "DIN_D2")
+ ),
+ MTK_PIN(PINCTRL_PIN(10, "PWM6"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 16),
+ MTK_FUNCTION(0, "GPIO10"),
+ MTK_FUNCTION(1, "PWM6"),
+ MTK_FUNCTION(2, "DISP0_PWM"),
+ MTK_FUNCTION(3, "DISP1_PWM"),
+ MTK_FUNCTION(4, "LCM_RST0")
+ ),
+ MTK_PIN(PINCTRL_PIN(11, "PWM7"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 17),
+ MTK_FUNCTION(0, "GPIO11"),
+ MTK_FUNCTION(1, "PWM7"),
+ MTK_FUNCTION(2, "DISP1_PWM"),
+ MTK_FUNCTION(3, "DISP0_PWM"),
+ MTK_FUNCTION(4, "LCM_RST1")
+ ),
+ MTK_PIN(PINCTRL_PIN(12, "IDDIG_P0"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(1, 22),
+ MTK_FUNCTION(0, "GPIO12"),
+ MTK_FUNCTION(1, "IDDIG_A"),
+ MTK_FUNCTION(5, "DIN_D7")
+ ),
+ MTK_PIN(PINCTRL_PIN(13, "DRV_VBUS_P0"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 43),
+ MTK_FUNCTION(0, "GPIO13"),
+ MTK_FUNCTION(1, "DRV_VBUS_A")
+ ),
+ MTK_PIN(PINCTRL_PIN(14, "IDDIG_P1"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(1, 44),
+ MTK_FUNCTION(0, "GPIO14"),
+ MTK_FUNCTION(1, "IDDIG_B")
+ ),
+ MTK_PIN(PINCTRL_PIN(15, "DRV_VBUS_P1"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 45),
+ MTK_FUNCTION(0, "GPIO15"),
+ MTK_FUNCTION(1, "DRV_VBUS_B")
+ ),
+ MTK_PIN(PINCTRL_PIN(16, "DRV_VBUS_P2"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 46),
+ MTK_FUNCTION(0, "GPIO16"),
+ MTK_FUNCTION(1, "DRV_VBUS_C")
+ ),
+ MTK_PIN(PINCTRL_PIN(17, "DRV_VBUS_P3"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 47),
+ MTK_FUNCTION(0, "GPIO17"),
+ MTK_FUNCTION(1, "DRV_VBUS_D")
+ ),
+ MTK_PIN(PINCTRL_PIN(18, "KPROW0"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 18),
+ MTK_FUNCTION(0, "GPIO18"),
+ MTK_FUNCTION(1, "KROW0")
+ ),
+ MTK_PIN(PINCTRL_PIN(19, "KPCOL0"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 19),
+ MTK_FUNCTION(0, "GPIO19"),
+ MTK_FUNCTION(1, "KCOL0")
+ ),
+ MTK_PIN(PINCTRL_PIN(20, "KPROW1"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 48),
+ MTK_FUNCTION(0, "GPIO20"),
+ MTK_FUNCTION(1, "KROW1")
+ ),
+ MTK_PIN(PINCTRL_PIN(21, "KPCOL1"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 49),
+ MTK_FUNCTION(0, "GPIO21"),
+ MTK_FUNCTION(1, "KCOL1")
+ ),
+ MTK_PIN(PINCTRL_PIN(22, "KPROW2"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 50),
+ MTK_FUNCTION(0, "GPIO22"),
+ MTK_FUNCTION(1, "KROW2"),
+ MTK_FUNCTION(2, "DISP1_PWM")
+ ),
+ MTK_PIN(PINCTRL_PIN(23, "KPCOL2"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 51),
+ MTK_FUNCTION(0, "GPIO23"),
+ MTK_FUNCTION(1, "KCOL2"),
+ MTK_FUNCTION(2, "DISP0_PWM")
+ ),
+ MTK_PIN(PINCTRL_PIN(24, "CMMCLK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 52),
+ MTK_FUNCTION(0, "GPIO24"),
+ MTK_FUNCTION(1, "CMMCLK"),
+ MTK_FUNCTION(7, "DBG_MON_A_1_")
+ ),
+ MTK_PIN(PINCTRL_PIN(25, "CM2MCLK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 53),
+ MTK_FUNCTION(0, "GPIO25"),
+ MTK_FUNCTION(1, "CM2MCLK"),
+ MTK_FUNCTION(7, "DBG_MON_A_2_")
+ ),
+ MTK_PIN(PINCTRL_PIN(26, "PCM_TX"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 54),
+ MTK_FUNCTION(0, "GPIO26"),
+ MTK_FUNCTION(1, "PCM1_DO"),
+ MTK_FUNCTION(2, "MRG_TX"),
+ MTK_FUNCTION(3, "DAI_TX"),
+ MTK_FUNCTION(4, "MRG_RX"),
+ MTK_FUNCTION(5, "DAI_RX"),
+ MTK_FUNCTION(6, "PCM1_DI"),
+ MTK_FUNCTION(7, "DBG_MON_A_3_")
+ ),
+ MTK_PIN(PINCTRL_PIN(27, "PCM_CLK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 55),
+ MTK_FUNCTION(0, "GPIO27"),
+ MTK_FUNCTION(1, "PCM1_CLK"),
+ MTK_FUNCTION(2, "MRG_CLK"),
+ MTK_FUNCTION(3, "DAI_CLK"),
+ MTK_FUNCTION(7, "DBG_MON_A_4_")
+ ),
+ MTK_PIN(PINCTRL_PIN(28, "PCM_RX"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 56),
+ MTK_FUNCTION(0, "GPIO28"),
+ MTK_FUNCTION(1, "PCM1_DI"),
+ MTK_FUNCTION(2, "MRG_RX"),
+ MTK_FUNCTION(3, "DAI_RX"),
+ MTK_FUNCTION(4, "MRG_TX"),
+ MTK_FUNCTION(5, "DAI_TX"),
+ MTK_FUNCTION(6, "PCM1_DO"),
+ MTK_FUNCTION(7, "DBG_MON_A_5_")
+ ),
+ MTK_PIN(PINCTRL_PIN(29, "PCM_SYNC"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 57),
+ MTK_FUNCTION(0, "GPIO29"),
+ MTK_FUNCTION(1, "PCM1_SYNC"),
+ MTK_FUNCTION(2, "MRG_SYNC"),
+ MTK_FUNCTION(3, "DAI_SYNC"),
+ MTK_FUNCTION(7, "DBG_MON_A_6_")
+ ),
+ MTK_PIN(PINCTRL_PIN(30, "NCEB0"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 58),
+ MTK_FUNCTION(0, "GPIO30"),
+ MTK_FUNCTION(1, "NCEB0"),
+ MTK_FUNCTION(2, "USB0_FT_SDA"),
+ MTK_FUNCTION(7, "DBG_MON_A_7_")
+ ),
+ MTK_PIN(PINCTRL_PIN(31, "NCEB1"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 59),
+ MTK_FUNCTION(0, "GPIO31"),
+ MTK_FUNCTION(1, "NCEB1"),
+ MTK_FUNCTION(2, "USB1_FT_SCL"),
+ MTK_FUNCTION(7, "DBG_MON_A_8_")
+ ),
+ MTK_PIN(PINCTRL_PIN(32, "NF_DQS"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 60),
+ MTK_FUNCTION(0, "GPIO32"),
+ MTK_FUNCTION(1, "NF_DQS"),
+ MTK_FUNCTION(2, "USB1_FT_SDA"),
+ MTK_FUNCTION(7, "DBG_MON_A_9_")
+ ),
+ MTK_PIN(PINCTRL_PIN(33, "NWEB"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 61),
+ MTK_FUNCTION(0, "GPIO33"),
+ MTK_FUNCTION(1, "NWEB"),
+ MTK_FUNCTION(2, "USB2_FT_SCL"),
+ MTK_FUNCTION(7, "DBG_MON_A_10_")
+ ),
+ MTK_PIN(PINCTRL_PIN(34, "NREB"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 62),
+ MTK_FUNCTION(0, "GPIO34"),
+ MTK_FUNCTION(1, "NREB"),
+ MTK_FUNCTION(2, "USB2_FT_SDA"),
+ MTK_FUNCTION(7, "DBG_MON_A_11_")
+ ),
+ MTK_PIN(PINCTRL_PIN(35, "NCLE"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 63),
+ MTK_FUNCTION(0, "GPIO35"),
+ MTK_FUNCTION(1, "NCLE"),
+ MTK_FUNCTION(2, "USB3_FT_SCL"),
+ MTK_FUNCTION(7, "DBG_MON_A_12_")
+ ),
+ MTK_PIN(PINCTRL_PIN(36, "NALE"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 64),
+ MTK_FUNCTION(0, "GPIO36"),
+ MTK_FUNCTION(1, "NALE"),
+ MTK_FUNCTION(2, "USB3_FT_SDA"),
+ MTK_FUNCTION(7, "DBG_MON_A_13_")
+ ),
+ MTK_PIN(PINCTRL_PIN(37, "MSDC0E_CLK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO37"),
+ MTK_FUNCTION(1, "MSDC0_CLK"),
+ MTK_FUNCTION(2, "USB0_FT_SCL"),
+ MTK_FUNCTION(7, "DBG_MON_A_0_")
+ ),
+ MTK_PIN(PINCTRL_PIN(38, "MSDC0E_DAT7"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO38"),
+ MTK_FUNCTION(1, "MSDC0_DAT7"),
+ MTK_FUNCTION(2, "NAND_ND7"),
+ MTK_FUNCTION(7, "DBG_MON_A_14_")
+ ),
+ MTK_PIN(PINCTRL_PIN(39, "MSDC0E_DAT6"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO39"),
+ MTK_FUNCTION(1, "MSDC0_DAT6"),
+ MTK_FUNCTION(2, "NAND_ND6"),
+ MTK_FUNCTION(7, "DBG_MON_A_15_")
+ ),
+ MTK_PIN(PINCTRL_PIN(40, "MSDC0E_DAT5"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO40"),
+ MTK_FUNCTION(1, "MSDC0_DAT5"),
+ MTK_FUNCTION(2, "NAND_ND5"),
+ MTK_FUNCTION(7, "DBG_MON_A_16_")
+ ),
+ MTK_PIN(PINCTRL_PIN(41, "MSDC0E_DAT4"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO41"),
+ MTK_FUNCTION(1, "MSDC0_DAT4"),
+ MTK_FUNCTION(2, "NAND_ND4"),
+ MTK_FUNCTION(7, "DBG_MON_A_17_")
+ ),
+ MTK_PIN(PINCTRL_PIN(42, "MSDC0E_DAT3"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO42"),
+ MTK_FUNCTION(1, "MSDC0_DAT3"),
+ MTK_FUNCTION(2, "NAND_ND3"),
+ MTK_FUNCTION(7, "DBG_MON_A_18_")
+ ),
+ MTK_PIN(PINCTRL_PIN(43, "MSDC0E_DAT2"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO43"),
+ MTK_FUNCTION(1, "MSDC0_DAT2"),
+ MTK_FUNCTION(2, "NAND_ND2"),
+ MTK_FUNCTION(7, "DBG_MON_A_19_")
+ ),
+ MTK_PIN(PINCTRL_PIN(44, "MSDC0E_DAT1"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO44"),
+ MTK_FUNCTION(1, "MSDC0_DAT1"),
+ MTK_FUNCTION(2, "NAND_ND1"),
+ MTK_FUNCTION(7, "DBG_MON_A_20_")
+ ),
+ MTK_PIN(PINCTRL_PIN(45, "MSDC0E_DAT0"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO45"),
+ MTK_FUNCTION(1, "MSDC0_DAT0"),
+ MTK_FUNCTION(2, "NAND_ND0"),
+ MTK_FUNCTION(7, "DBG_MON_A_21_")
+ ),
+ MTK_PIN(PINCTRL_PIN(46, "MSDC0E_CMD"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO46"),
+ MTK_FUNCTION(1, "MSDC0_CMD"),
+ MTK_FUNCTION(2, "NAND_NRNB"),
+ MTK_FUNCTION(7, "DBG_MON_A_22_")
+ ),
+ MTK_PIN(PINCTRL_PIN(47, "MSDC0E_DSL"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO47"),
+ MTK_FUNCTION(1, "MSDC0_DSL"),
+ MTK_FUNCTION(7, "DBG_MON_A_23_")
+ ),
+ MTK_PIN(PINCTRL_PIN(48, "MSDC0E_RSTB"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 142),
+ MTK_FUNCTION(0, "GPIO48"),
+ MTK_FUNCTION(1, "MSDC0_RSTB"),
+ MTK_FUNCTION(7, "DBG_MON_A_24_")
+ ),
+ MTK_PIN(PINCTRL_PIN(49, "MSDC3_DAT3"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 65),
+ MTK_FUNCTION(0, "GPIO49"),
+ MTK_FUNCTION(1, "MSDC3_DAT3"),
+ MTK_FUNCTION(7, "DBG_MON_A_25_")
+ ),
+ MTK_PIN(PINCTRL_PIN(50, "MSDC3_DAT2"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 66),
+ MTK_FUNCTION(0, "GPIO50"),
+ MTK_FUNCTION(1, "MSDC3_DAT2"),
+ MTK_FUNCTION(7, "DBG_MON_A_26_")
+ ),
+ MTK_PIN(PINCTRL_PIN(51, "MSDC3_DAT1"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 67),
+ MTK_FUNCTION(0, "GPIO51"),
+ MTK_FUNCTION(1, "MSDC3_DAT1"),
+ MTK_FUNCTION(7, "DBG_MON_A_27_")
+ ),
+ MTK_PIN(PINCTRL_PIN(52, "MSDC3_DAT0"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 68),
+ MTK_FUNCTION(0, "GPIO52"),
+ MTK_FUNCTION(1, "MSDC3_DAT0"),
+ MTK_FUNCTION(7, "DBG_MON_A_28_")
+ ),
+ MTK_PIN(PINCTRL_PIN(53, "MSDC3_CMD"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 69),
+ MTK_FUNCTION(0, "GPIO53"),
+ MTK_FUNCTION(1, "MSDC3_CMD"),
+ MTK_FUNCTION(7, "DBG_MON_A_29_")
+ ),
+ MTK_PIN(PINCTRL_PIN(54, "MSDC3_INS"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 20),
+ MTK_FUNCTION(0, "GPIO54"),
+ MTK_FUNCTION(1, "MSDC3_INS"),
+ MTK_FUNCTION(7, "DBG_MON_A_30_")
+ ),
+ MTK_PIN(PINCTRL_PIN(55, "MSDC3_DSL"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 70),
+ MTK_FUNCTION(0, "GPIO55"),
+ MTK_FUNCTION(1, "MSDC3_DSL"),
+ MTK_FUNCTION(7, "DBG_MON_A_31_")
+ ),
+ MTK_PIN(PINCTRL_PIN(56, "MSDC3_CLK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 71),
+ MTK_FUNCTION(0, "GPIO56"),
+ MTK_FUNCTION(1, "MSDC3_CLK"),
+ MTK_FUNCTION(7, "DBG_MON_A_32_")
+ ),
+ MTK_PIN(PINCTRL_PIN(57, "NOR_CS"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 72),
+ MTK_FUNCTION(0, "GPIO57"),
+ MTK_FUNCTION(1, "NOR_CS")
+ ),
+ MTK_PIN(PINCTRL_PIN(58, "NOR_CK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 73),
+ MTK_FUNCTION(0, "GPIO58"),
+ MTK_FUNCTION(1, "NOR_CK")
+ ),
+ MTK_PIN(PINCTRL_PIN(59, "NOR_IO0"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 74),
+ MTK_FUNCTION(0, "GPIO59"),
+ MTK_FUNCTION(1, "NOR_IO0")
+ ),
+ MTK_PIN(PINCTRL_PIN(60, "NOR_IO1"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 75),
+ MTK_FUNCTION(0, "GPIO60"),
+ MTK_FUNCTION(1, "NOR_IO1")
+ ),
+ MTK_PIN(PINCTRL_PIN(61, "NOR_IO2"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 76),
+ MTK_FUNCTION(0, "GPIO61"),
+ MTK_FUNCTION(1, "NOR_IO2")
+ ),
+ MTK_PIN(PINCTRL_PIN(62, "NOR_IO3"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 77),
+ MTK_FUNCTION(0, "GPIO62"),
+ MTK_FUNCTION(1, "NOR_IO3")
+ ),
+ MTK_PIN(PINCTRL_PIN(63, "MSDC1_CLK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 78),
+ MTK_FUNCTION(0, "GPIO63"),
+ MTK_FUNCTION(1, "MSDC1_CLK"),
+ MTK_FUNCTION(2, "UDI_TCK")
+ ),
+ MTK_PIN(PINCTRL_PIN(64, "MSDC1_DAT3"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 79),
+ MTK_FUNCTION(0, "GPIO64"),
+ MTK_FUNCTION(1, "MSDC1_DAT3"),
+ MTK_FUNCTION(2, "UDI_TDI")
+ ),
+ MTK_PIN(PINCTRL_PIN(65, "MSDC1_DAT1"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 80),
+ MTK_FUNCTION(0, "GPIO65"),
+ MTK_FUNCTION(1, "MSDC1_DAT1"),
+ MTK_FUNCTION(2, "UDI_TMS")
+ ),
+ MTK_PIN(PINCTRL_PIN(66, "MSDC1_DAT2"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 81),
+ MTK_FUNCTION(0, "GPIO66"),
+ MTK_FUNCTION(1, "MSDC1_DAT2"),
+ MTK_FUNCTION(2, "UDI_TDO")
+ ),
+ MTK_PIN(PINCTRL_PIN(67, "MSDC1_PSW"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 82),
+ MTK_FUNCTION(0, "GPIO67"),
+ MTK_FUNCTION(2, "UDI_NTRST")
+ ),
+ MTK_PIN(PINCTRL_PIN(68, "MSDC1_DAT0"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 83),
+ MTK_FUNCTION(0, "GPIO68"),
+ MTK_FUNCTION(1, "MSDC1_DAT0")
+ ),
+ MTK_PIN(PINCTRL_PIN(69, "MSDC1_CMD"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 84),
+ MTK_FUNCTION(0, "GPIO69"),
+ MTK_FUNCTION(1, "MSDC1_CMD")
+ ),
+ MTK_PIN(PINCTRL_PIN(70, "MSDC1_INS"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 85),
+ MTK_FUNCTION(0, "GPIO70")
+ ),
+ MTK_PIN(PINCTRL_PIN(71, "GBE_TXD3"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 86),
+ MTK_FUNCTION(0, "GPIO71"),
+ MTK_FUNCTION(1, "GBE_TXD3"),
+ MTK_FUNCTION(7, "DBG_MON_B_0_")
+ ),
+ MTK_PIN(PINCTRL_PIN(72, "GBE_TXD2"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 87),
+ MTK_FUNCTION(0, "GPIO72"),
+ MTK_FUNCTION(1, "GBE_TXD2"),
+ MTK_FUNCTION(7, "DBG_MON_B_1_")
+ ),
+ MTK_PIN(PINCTRL_PIN(73, "GBE_TXD1"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 88),
+ MTK_FUNCTION(0, "GPIO73"),
+ MTK_FUNCTION(1, "GBE_TXD1"),
+ MTK_FUNCTION(7, "DBG_MON_B_2_")
+ ),
+ MTK_PIN(PINCTRL_PIN(74, "GBE_TXD0"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 89),
+ MTK_FUNCTION(0, "GPIO74"),
+ MTK_FUNCTION(1, "GBE_TXD0"),
+ MTK_FUNCTION(7, "DBG_MON_B_3_")
+ ),
+ MTK_PIN(PINCTRL_PIN(75, "GBE_TXC"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 90),
+ MTK_FUNCTION(0, "GPIO75"),
+ MTK_FUNCTION(1, "GBE_TXC"),
+ MTK_FUNCTION(7, "DBG_MON_B_4_")
+ ),
+ MTK_PIN(PINCTRL_PIN(76, "GBE_TXEN"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 91),
+ MTK_FUNCTION(0, "GPIO76"),
+ MTK_FUNCTION(1, "GBE_TXEN"),
+ MTK_FUNCTION(7, "DBG_MON_B_5_")
+ ),
+ MTK_PIN(PINCTRL_PIN(77, "GBE_TXER"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 92),
+ MTK_FUNCTION(0, "GPIO77"),
+ MTK_FUNCTION(1, "GBE_TXER"),
+ MTK_FUNCTION(7, "DBG_MON_B_6_")
+ ),
+ MTK_PIN(PINCTRL_PIN(78, "GBE_RXD3"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 93),
+ MTK_FUNCTION(0, "GPIO78"),
+ MTK_FUNCTION(1, "GBE_RXD3"),
+ MTK_FUNCTION(7, "DBG_MON_B_7_")
+ ),
+ MTK_PIN(PINCTRL_PIN(79, "GBE_RXD2"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 94),
+ MTK_FUNCTION(0, "GPIO79"),
+ MTK_FUNCTION(1, "GBE_RXD2"),
+ MTK_FUNCTION(7, "DBG_MON_B_8_")
+ ),
+ MTK_PIN(PINCTRL_PIN(80, "GBE_RXD1"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 95),
+ MTK_FUNCTION(0, "GPIO80"),
+ MTK_FUNCTION(1, "GBE_RXD1"),
+ MTK_FUNCTION(7, "DBG_MON_B_9_")
+ ),
+ MTK_PIN(PINCTRL_PIN(81, "GBE_RXD0"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 96),
+ MTK_FUNCTION(0, "GPIO81"),
+ MTK_FUNCTION(1, "GBE_RXD0"),
+ MTK_FUNCTION(7, "DBG_MON_B_10_")
+ ),
+ MTK_PIN(PINCTRL_PIN(82, "GBE_RXDV"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 97),
+ MTK_FUNCTION(0, "GPIO82"),
+ MTK_FUNCTION(1, "GBE_RXDV"),
+ MTK_FUNCTION(7, "DBG_MON_B_11_")
+ ),
+ MTK_PIN(PINCTRL_PIN(83, "GBE_RXER"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 98),
+ MTK_FUNCTION(0, "GPIO83"),
+ MTK_FUNCTION(1, "GBE_RXER"),
+ MTK_FUNCTION(7, "DBG_MON_B_12_")
+ ),
+ MTK_PIN(PINCTRL_PIN(84, "GBE_RXC"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 99),
+ MTK_FUNCTION(0, "GPIO84"),
+ MTK_FUNCTION(1, "GBE_RXC"),
+ MTK_FUNCTION(7, "DBG_MON_B_13_")
+ ),
+ MTK_PIN(PINCTRL_PIN(85, "GBE_MDC"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 100),
+ MTK_FUNCTION(0, "GPIO85"),
+ MTK_FUNCTION(1, "GBE_MDC"),
+ MTK_FUNCTION(7, "DBG_MON_B_14_")
+ ),
+ MTK_PIN(PINCTRL_PIN(86, "GBE_MDIO"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 101),
+ MTK_FUNCTION(0, "GPIO86"),
+ MTK_FUNCTION(1, "GBE_MDIO"),
+ MTK_FUNCTION(7, "DBG_MON_B_15_")
+ ),
+ MTK_PIN(PINCTRL_PIN(87, "GBE_COL"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 102),
+ MTK_FUNCTION(0, "GPIO87"),
+ MTK_FUNCTION(1, "GBE_COL"),
+ MTK_FUNCTION(7, "DBG_MON_B_16_")
+ ),
+ MTK_PIN(PINCTRL_PIN(88, "GBE_INTR"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 21),
+ MTK_FUNCTION(0, "GPIO88"),
+ MTK_FUNCTION(1, "GBE_INTR"),
+ MTK_FUNCTION(2, "GBE_CRS"),
+ MTK_FUNCTION(7, "DBG_MON_B_17_")
+ ),
+ MTK_PIN(PINCTRL_PIN(89, "MSDC2_CLK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 103),
+ MTK_FUNCTION(0, "GPIO89"),
+ MTK_FUNCTION(1, "MSDC2_CLK"),
+ MTK_FUNCTION(7, "DBG_MON_B_18_")
+ ),
+ MTK_PIN(PINCTRL_PIN(90, "MSDC2_DAT3"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 104),
+ MTK_FUNCTION(0, "GPIO90"),
+ MTK_FUNCTION(1, "MSDC2_DAT3"),
+ MTK_FUNCTION(7, "DBG_MON_B_19_")
+ ),
+ MTK_PIN(PINCTRL_PIN(91, "MSDC2_DAT2"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 105),
+ MTK_FUNCTION(0, "GPIO91"),
+ MTK_FUNCTION(1, "MSDC2_DAT2"),
+ MTK_FUNCTION(7, "DBG_MON_B_20_")
+ ),
+ MTK_PIN(PINCTRL_PIN(92, "MSDC2_DAT1"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 106),
+ MTK_FUNCTION(0, "GPIO92"),
+ MTK_FUNCTION(1, "MSDC2_DAT1"),
+ MTK_FUNCTION(7, "DBG_MON_B_21_")
+ ),
+ MTK_PIN(PINCTRL_PIN(93, "MSDC2_DAT0"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 107),
+ MTK_FUNCTION(0, "GPIO93"),
+ MTK_FUNCTION(1, "MSDC2_DAT0"),
+ MTK_FUNCTION(7, "DBG_MON_B_22_")
+ ),
+ MTK_PIN(PINCTRL_PIN(94, "MSDC2_INS"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 108),
+ MTK_FUNCTION(0, "GPIO94"),
+ MTK_FUNCTION(7, "DBG_MON_B_23_")
+ ),
+ MTK_PIN(PINCTRL_PIN(95, "MSDC2_CMD"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 109),
+ MTK_FUNCTION(0, "GPIO95"),
+ MTK_FUNCTION(1, "MSDC2_CMD"),
+ MTK_FUNCTION(7, "DBG_MON_B_24_")
+ ),
+ MTK_PIN(PINCTRL_PIN(96, "MSDC2_PSW"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 110),
+ MTK_FUNCTION(0, "GPIO96"),
+ MTK_FUNCTION(7, "DBG_MON_B_25_")
+ ),
+ MTK_PIN(PINCTRL_PIN(97, "URXD4"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 111),
+ MTK_FUNCTION(0, "GPIO97"),
+ MTK_FUNCTION(1, "URXD4"),
+ MTK_FUNCTION(2, "UTXD4"),
+ MTK_FUNCTION(3, "MRG_CLK"),
+ MTK_FUNCTION(4, "PCM1_CLK"),
+ MTK_FUNCTION(5, "I2S_IQ2_SDQB"),
+ MTK_FUNCTION(6, "I2SO1_WS"),
+ MTK_FUNCTION(7, "DBG_MON_B_26_")
+ ),
+ MTK_PIN(PINCTRL_PIN(98, "URTS4"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 112),
+ MTK_FUNCTION(0, "GPIO98"),
+ MTK_FUNCTION(1, "URTS4"),
+ MTK_FUNCTION(2, "UCTS4"),
+ MTK_FUNCTION(3, "MRG_RX"),
+ MTK_FUNCTION(4, "PCM1_DI"),
+ MTK_FUNCTION(5, "I2S_IQ1_SDIB"),
+ MTK_FUNCTION(6, "I2SO1_MCK"),
+ MTK_FUNCTION(7, "DBG_MON_B_27_")
+ ),
+ MTK_PIN(PINCTRL_PIN(99, "UTXD4"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 113),
+ MTK_FUNCTION(0, "GPIO99"),
+ MTK_FUNCTION(1, "UTXD4"),
+ MTK_FUNCTION(2, "URXD4"),
+ MTK_FUNCTION(3, "MRG_SYNC"),
+ MTK_FUNCTION(4, "PCM1_SYNC"),
+ MTK_FUNCTION(5, "I2S_IQ0_SDQB"),
+ MTK_FUNCTION(6, "I2SO1_BCK"),
+ MTK_FUNCTION(7, "DBG_MON_B_28_")
+ ),
+ MTK_PIN(PINCTRL_PIN(100, "UCTS4"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 114),
+ MTK_FUNCTION(0, "GPIO100"),
+ MTK_FUNCTION(1, "UCTS4"),
+ MTK_FUNCTION(2, "URTS4"),
+ MTK_FUNCTION(3, "MRG_TX"),
+ MTK_FUNCTION(4, "PCM1_DO"),
+ MTK_FUNCTION(5, "I2S_IQ0_SDIB"),
+ MTK_FUNCTION(6, "I2SO1_DO"),
+ MTK_FUNCTION(7, "DBG_MON_B_29_")
+ ),
+ MTK_PIN(PINCTRL_PIN(101, "URXD5"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 30),
+ MTK_FUNCTION(0, "GPIO101"),
+ MTK_FUNCTION(1, "URXD5"),
+ MTK_FUNCTION(2, "UTXD5"),
+ MTK_FUNCTION(3, "I2SO3_WS"),
+ MTK_FUNCTION(4, "TDMIN_LRCK"),
+ MTK_FUNCTION(6, "I2SO0_WS"),
+ MTK_FUNCTION(7, "DBG_MON_B_30_")
+ ),
+ MTK_PIN(PINCTRL_PIN(102, "URTS5"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 31),
+ MTK_FUNCTION(0, "GPIO102"),
+ MTK_FUNCTION(1, "URTS5"),
+ MTK_FUNCTION(2, "UCTS5"),
+ MTK_FUNCTION(3, "I2SO3_MCK"),
+ MTK_FUNCTION(4, "TDMIN_MCLK"),
+ MTK_FUNCTION(5, "IR_IN"),
+ MTK_FUNCTION(6, "I2SO0_MCK"),
+ MTK_FUNCTION(7, "DBG_MON_B_31_")
+ ),
+ MTK_PIN(PINCTRL_PIN(103, "UTXD5"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 32),
+ MTK_FUNCTION(0, "GPIO103"),
+ MTK_FUNCTION(1, "UTXD5"),
+ MTK_FUNCTION(2, "URXD5"),
+ MTK_FUNCTION(3, "I2SO3_BCK"),
+ MTK_FUNCTION(4, "TDMIN_BCK"),
+ MTK_FUNCTION(6, "I2SO0_BCK"),
+ MTK_FUNCTION(7, "DBG_MON_B_32_")
+ ),
+ MTK_PIN(PINCTRL_PIN(104, "UCTS5"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 33),
+ MTK_FUNCTION(0, "GPIO104"),
+ MTK_FUNCTION(1, "UCTS5"),
+ MTK_FUNCTION(2, "URTS5"),
+ MTK_FUNCTION(3, "I2SO0_DO1"),
+ MTK_FUNCTION(4, "TDMIN_DI"),
+ MTK_FUNCTION(5, "IR_IN"),
+ MTK_FUNCTION(6, "I2SO0_DO0")
+ ),
+ MTK_PIN(PINCTRL_PIN(105, "I2C_SDA0"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 115),
+ MTK_FUNCTION(0, "GPIO105"),
+ MTK_FUNCTION(1, "SDA0")
+ ),
+ MTK_PIN(PINCTRL_PIN(106, "I2C_SDA1"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 116),
+ MTK_FUNCTION(0, "GPIO106"),
+ MTK_FUNCTION(1, "SDA1")
+ ),
+ MTK_PIN(PINCTRL_PIN(107, "I2C_SDA2"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 117),
+ MTK_FUNCTION(0, "GPIO107"),
+ MTK_FUNCTION(1, "SDA2")
+ ),
+ MTK_PIN(PINCTRL_PIN(108, "I2C_SDA3"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 118),
+ MTK_FUNCTION(0, "GPIO108"),
+ MTK_FUNCTION(1, "SDA3")
+ ),
+ MTK_PIN(PINCTRL_PIN(109, "I2C_SDA4"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 119),
+ MTK_FUNCTION(0, "GPIO109"),
+ MTK_FUNCTION(1, "SDA4")
+ ),
+ MTK_PIN(PINCTRL_PIN(110, "I2C_SDA5"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 34),
+ MTK_FUNCTION(0, "GPIO110"),
+ MTK_FUNCTION(1, "SDA5")
+ ),
+ MTK_PIN(PINCTRL_PIN(111, "I2C_SCL0"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 120),
+ MTK_FUNCTION(0, "GPIO111"),
+ MTK_FUNCTION(1, "SCL0")
+ ),
+ MTK_PIN(PINCTRL_PIN(112, "I2C_SCL1"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 121),
+ MTK_FUNCTION(0, "GPIO112"),
+ MTK_FUNCTION(1, "SCL1")
+ ),
+ MTK_PIN(PINCTRL_PIN(113, "I2C_SCL2"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 122),
+ MTK_FUNCTION(0, "GPIO113"),
+ MTK_FUNCTION(1, "SCL2")
+ ),
+ MTK_PIN(PINCTRL_PIN(114, "I2C_SCL3"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 123),
+ MTK_FUNCTION(0, "GPIO114"),
+ MTK_FUNCTION(1, "SCL3")
+ ),
+ MTK_PIN(PINCTRL_PIN(115, "I2C_SCL4"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 124),
+ MTK_FUNCTION(0, "GPIO115"),
+ MTK_FUNCTION(1, "SCL4")
+ ),
+ MTK_PIN(PINCTRL_PIN(116, "I2C_SCL5"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 35),
+ MTK_FUNCTION(0, "GPIO116"),
+ MTK_FUNCTION(1, "SCL5")
+ ),
+ MTK_PIN(PINCTRL_PIN(117, "URXD0"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 125),
+ MTK_FUNCTION(0, "GPIO117"),
+ MTK_FUNCTION(1, "URXD0"),
+ MTK_FUNCTION(2, "UTXD0")
+ ),
+ MTK_PIN(PINCTRL_PIN(118, "URXD1"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 126),
+ MTK_FUNCTION(0, "GPIO118"),
+ MTK_FUNCTION(1, "URXD1"),
+ MTK_FUNCTION(2, "UTXD1")
+ ),
+ MTK_PIN(PINCTRL_PIN(119, "URXD2"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 127),
+ MTK_FUNCTION(0, "GPIO119"),
+ MTK_FUNCTION(1, "URXD2"),
+ MTK_FUNCTION(2, "UTXD2")
+ ),
+ MTK_PIN(PINCTRL_PIN(120, "UTXD0"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 128),
+ MTK_FUNCTION(0, "GPIO120"),
+ MTK_FUNCTION(1, "UTXD0"),
+ MTK_FUNCTION(2, "URXD0")
+ ),
+ MTK_PIN(PINCTRL_PIN(121, "UTXD1"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 129),
+ MTK_FUNCTION(0, "GPIO121"),
+ MTK_FUNCTION(1, "UTXD1"),
+ MTK_FUNCTION(2, "URXD1")
+ ),
+ MTK_PIN(PINCTRL_PIN(122, "UTXD2"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 130),
+ MTK_FUNCTION(0, "GPIO122"),
+ MTK_FUNCTION(1, "UTXD2"),
+ MTK_FUNCTION(2, "URXD2")
+ ),
+ MTK_PIN(PINCTRL_PIN(123, "URXD3"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 131),
+ MTK_FUNCTION(0, "GPIO123"),
+ MTK_FUNCTION(1, "URXD3"),
+ MTK_FUNCTION(2, "UTXD3"),
+ MTK_FUNCTION(3, "PURE_HW_PROTECT")
+ ),
+ MTK_PIN(PINCTRL_PIN(124, "UTXD3"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 132),
+ MTK_FUNCTION(0, "GPIO124"),
+ MTK_FUNCTION(1, "UTXD3"),
+ MTK_FUNCTION(2, "URXD3"),
+ MTK_FUNCTION(3, "PURE_HW_PROTECT")
+ ),
+ MTK_PIN(PINCTRL_PIN(125, "URTS3"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 133),
+ MTK_FUNCTION(0, "GPIO125"),
+ MTK_FUNCTION(1, "URTS3"),
+ MTK_FUNCTION(2, "UCTS3"),
+ MTK_FUNCTION(3, "WATCH_DOG")
+ ),
+ MTK_PIN(PINCTRL_PIN(126, "UCTS3"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 134),
+ MTK_FUNCTION(0, "GPIO126"),
+ MTK_FUNCTION(1, "UCTS3"),
+ MTK_FUNCTION(2, "URTS3"),
+ MTK_FUNCTION(3, "SRCLKENA0")
+ ),
+ MTK_PIN(PINCTRL_PIN(127, "SPI2_CSN"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 135),
+ MTK_FUNCTION(0, "GPIO127"),
+ MTK_FUNCTION(1, "SPI_CS_2_"),
+ MTK_FUNCTION(2, "SPI_CS_1_")
+ ),
+ MTK_PIN(PINCTRL_PIN(128, "SPI2_MO"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 136),
+ MTK_FUNCTION(0, "GPIO128"),
+ MTK_FUNCTION(1, "SPI_MO_2_"),
+ MTK_FUNCTION(2, "SPI_SO_1_")
+ ),
+ MTK_PIN(PINCTRL_PIN(129, "SPI2_MI"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 137),
+ MTK_FUNCTION(0, "GPIO129"),
+ MTK_FUNCTION(1, "SPI_MI_2_"),
+ MTK_FUNCTION(2, "SPI_SI_1_")
+ ),
+ MTK_PIN(PINCTRL_PIN(130, "SPI2_CK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 138),
+ MTK_FUNCTION(0, "GPIO130"),
+ MTK_FUNCTION(1, "SPI_CK_2_"),
+ MTK_FUNCTION(2, "SPI_CK_1_")
+ ),
+ MTK_PIN(PINCTRL_PIN(131, "SPI3_CSN"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 139),
+ MTK_FUNCTION(0, "GPIO131"),
+ MTK_FUNCTION(1, "SPI_CS_3_")
+ ),
+ MTK_PIN(PINCTRL_PIN(132, "SPI3_MO"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 143),
+ MTK_FUNCTION(0, "GPIO132"),
+ MTK_FUNCTION(1, "SPI_MO_3_")
+ ),
+ MTK_PIN(PINCTRL_PIN(133, "SPI3_MI"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 144),
+ MTK_FUNCTION(0, "GPIO133"),
+ MTK_FUNCTION(1, "SPI_MI_3_")
+ ),
+ MTK_PIN(PINCTRL_PIN(134, "SPI3_CK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 145),
+ MTK_FUNCTION(0, "GPIO134"),
+ MTK_FUNCTION(1, "SPI_CK_3_")
+ ),
+ MTK_PIN(PINCTRL_PIN(135, "KPROW3"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 146),
+ MTK_FUNCTION(0, "GPIO135"),
+ MTK_FUNCTION(1, "KROW3"),
+ MTK_FUNCTION(2, "DSIC_TE")
+ ),
+ MTK_PIN(PINCTRL_PIN(136, "KPROW4"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 36),
+ MTK_FUNCTION(0, "GPIO136"),
+ MTK_FUNCTION(1, "KROW4"),
+ MTK_FUNCTION(2, "DSID_TE")
+ ),
+ MTK_PIN(PINCTRL_PIN(137, "KPCOL3"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 147),
+ MTK_FUNCTION(0, "GPIO137"),
+ MTK_FUNCTION(1, "KCOL3"),
+ MTK_FUNCTION(2, "DISP2_PWM")
+ ),
+ MTK_PIN(PINCTRL_PIN(138, "KPCOL4"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 37),
+ MTK_FUNCTION(0, "GPIO138"),
+ MTK_FUNCTION(1, "KCOL4"),
+ MTK_FUNCTION(2, "LCM_RST2")
+ ),
+ MTK_PIN(PINCTRL_PIN(139, "KPCOL5"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 38),
+ MTK_FUNCTION(0, "GPIO139"),
+ MTK_FUNCTION(1, "KCOL5"),
+ MTK_FUNCTION(3, "DSIA_TE"),
+ MTK_FUNCTION(4, "PURE_HW_PROTECT")
+ ),
+ MTK_PIN(PINCTRL_PIN(140, "KPCOL6"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 39),
+ MTK_FUNCTION(0, "GPIO140"),
+ MTK_FUNCTION(1, "KCOL6"),
+ MTK_FUNCTION(2, "WATCH_DOG"),
+ MTK_FUNCTION(3, "LCM_RST1")
+ ),
+ MTK_PIN(PINCTRL_PIN(141, "KPROW5"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 40),
+ MTK_FUNCTION(0, "GPIO141"),
+ MTK_FUNCTION(1, "KROW5"),
+ MTK_FUNCTION(3, "LCM_RST0"),
+ MTK_FUNCTION(4, "PURE_HW_PROTECT")
+ ),
+ MTK_PIN(PINCTRL_PIN(142, "KPROW6"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 41),
+ MTK_FUNCTION(0, "GPIO142"),
+ MTK_FUNCTION(1, "KROW6"),
+ MTK_FUNCTION(2, "SRCLKENA0"),
+ MTK_FUNCTION(3, "DSIB_TE")
+ ),
+ MTK_PIN(PINCTRL_PIN(143, "JTDO_ICE"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 148),
+ MTK_FUNCTION(0, "GPIO143"),
+ MTK_FUNCTION(1, "JTDO_ICE"),
+ MTK_FUNCTION(3, "DFD_TDO")
+ ),
+ MTK_PIN(PINCTRL_PIN(144, "JTCK_ICE"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 149),
+ MTK_FUNCTION(0, "GPIO144"),
+ MTK_FUNCTION(1, "JTCK_ICE"),
+ MTK_FUNCTION(3, "DFD_TCK")
+ ),
+ MTK_PIN(PINCTRL_PIN(145, "JTDI_ICE"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 150),
+ MTK_FUNCTION(0, "GPIO145"),
+ MTK_FUNCTION(1, "JTDI_ICE"),
+ MTK_FUNCTION(3, "DFD_TDI")
+ ),
+ MTK_PIN(PINCTRL_PIN(146, "JTMS_ICE"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 151),
+ MTK_FUNCTION(0, "GPIO146"),
+ MTK_FUNCTION(1, "JTMS_ICE"),
+ MTK_FUNCTION(3, "DFD_TMS")
+ ),
+ MTK_PIN(PINCTRL_PIN(147, "JTRSTB_ICE"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 152),
+ MTK_FUNCTION(0, "GPIO147"),
+ MTK_FUNCTION(1, "JTRST_B_ICE"),
+ MTK_FUNCTION(3, "DFD_NTRST")
+ ),
+ MTK_PIN(PINCTRL_PIN(148, "GPIO148"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 153),
+ MTK_FUNCTION(0, "GPIO148"),
+ MTK_FUNCTION(1, "JTRSTB_CM4"),
+ MTK_FUNCTION(3, "DFD_NTRST")
+ ),
+ MTK_PIN(PINCTRL_PIN(149, "GPIO149"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 154),
+ MTK_FUNCTION(0, "GPIO149"),
+ MTK_FUNCTION(1, "JTCK_CM4"),
+ MTK_FUNCTION(3, "DFD_TCK")
+ ),
+ MTK_PIN(PINCTRL_PIN(150, "GPIO150"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 155),
+ MTK_FUNCTION(0, "GPIO150"),
+ MTK_FUNCTION(1, "JTMS_CM4"),
+ MTK_FUNCTION(3, "DFD_TMS")
+ ),
+ MTK_PIN(PINCTRL_PIN(151, "GPIO151"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 156),
+ MTK_FUNCTION(0, "GPIO151"),
+ MTK_FUNCTION(1, "JTDI_CM4"),
+ MTK_FUNCTION(3, "DFD_TDI")
+ ),
+ MTK_PIN(PINCTRL_PIN(152, "GPIO152"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 157),
+ MTK_FUNCTION(0, "GPIO152"),
+ MTK_FUNCTION(1, "JTDO_CM4"),
+ MTK_FUNCTION(3, "DFD_TDO")
+ ),
+ MTK_PIN(PINCTRL_PIN(153, "SPI0_CSN"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 158),
+ MTK_FUNCTION(0, "GPIO153"),
+ MTK_FUNCTION(1, "SPI_CS_0_"),
+ MTK_FUNCTION(2, "SRCLKENA0"),
+ MTK_FUNCTION(3, "UTXD0"),
+ MTK_FUNCTION(4, "I2SO0_DO1"),
+ MTK_FUNCTION(6, "TDMO0_DATA1"),
+ MTK_FUNCTION(7, "I2S_IQ2_SDQB")
+ ),
+ MTK_PIN(PINCTRL_PIN(154, "SPI0_MI"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 159),
+ MTK_FUNCTION(0, "GPIO154"),
+ MTK_FUNCTION(1, "SPI_MI_0_"),
+ MTK_FUNCTION(2, "SRCLKENA0"),
+ MTK_FUNCTION(3, "URXD0"),
+ MTK_FUNCTION(4, "I2SO0_DO0"),
+ MTK_FUNCTION(5, "I2SO1_DO"),
+ MTK_FUNCTION(6, "TDMO0_DATA"),
+ MTK_FUNCTION(7, "I2S_IQ1_SDIB")
+ ),
+ MTK_PIN(PINCTRL_PIN(155, "SPI0_CK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 160),
+ MTK_FUNCTION(0, "GPIO155"),
+ MTK_FUNCTION(1, "SPI_CK_0_"),
+ MTK_FUNCTION(2, "SC_APBIAS_OFF"),
+ MTK_FUNCTION(3, "UTXD1"),
+ MTK_FUNCTION(4, "I2SO0_BCK"),
+ MTK_FUNCTION(5, "I2SO1_BCK"),
+ MTK_FUNCTION(6, "TDMO0_BCK"),
+ MTK_FUNCTION(7, "I2S_IQ0_SDQB")
+ ),
+ MTK_PIN(PINCTRL_PIN(156, "SPI0_MO"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 161),
+ MTK_FUNCTION(0, "GPIO156"),
+ MTK_FUNCTION(1, "SPI_MO_0_"),
+ MTK_FUNCTION(2, "SC_APBIAS_OFF"),
+ MTK_FUNCTION(3, "URXD1"),
+ MTK_FUNCTION(4, "I2SO0_WS"),
+ MTK_FUNCTION(5, "I2SO1_WS"),
+ MTK_FUNCTION(6, "TDMO0_LRCK"),
+ MTK_FUNCTION(7, "I2S_IQ0_SDIB")
+ ),
+ MTK_PIN(PINCTRL_PIN(157, "SPI5_CSN"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 162),
+ MTK_FUNCTION(0, "GPIO157"),
+ MTK_FUNCTION(1, "SPI_CS_5_"),
+ MTK_FUNCTION(2, "LCM_RST0"),
+ MTK_FUNCTION(3, "UTXD2"),
+ MTK_FUNCTION(4, "I2SO0_MCK"),
+ MTK_FUNCTION(5, "I2SO1_MCK"),
+ MTK_FUNCTION(6, "TDMO0_MCLK")
+ ),
+ MTK_PIN(PINCTRL_PIN(158, "SPI5_MI"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 163),
+ MTK_FUNCTION(0, "GPIO158"),
+ MTK_FUNCTION(1, "SPI_MI_5_"),
+ MTK_FUNCTION(2, "DSIA_TE"),
+ MTK_FUNCTION(3, "URXD2")
+ ),
+ MTK_PIN(PINCTRL_PIN(159, "SPI5_MO"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 164),
+ MTK_FUNCTION(0, "GPIO159"),
+ MTK_FUNCTION(1, "SPI_MO_5_"),
+ MTK_FUNCTION(2, "DSIB_TE"),
+ MTK_FUNCTION(3, "UTXD3")
+ ),
+ MTK_PIN(PINCTRL_PIN(160, "SPI5_CK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 165),
+ MTK_FUNCTION(0, "GPIO160"),
+ MTK_FUNCTION(1, "SPI_CK_5_"),
+ MTK_FUNCTION(2, "LCM_RST1"),
+ MTK_FUNCTION(3, "URXD3")
+ ),
+ MTK_PIN(PINCTRL_PIN(161, "SPI1_CSN"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 166),
+ MTK_FUNCTION(0, "GPIO161"),
+ MTK_FUNCTION(1, "SPI_CS_1_"),
+ MTK_FUNCTION(2, "SPI_CS_4_"),
+ MTK_FUNCTION(4, "I2S_IQ2_SDQB"),
+ MTK_FUNCTION(5, "I2SO2_DO"),
+ MTK_FUNCTION(6, "TDMO0_DATA1"),
+ MTK_FUNCTION(7, "I2SO0_DO1")
+ ),
+ MTK_PIN(PINCTRL_PIN(162, "SPI1_SI"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 167),
+ MTK_FUNCTION(0, "GPIO162"),
+ MTK_FUNCTION(1, "SPI_SI_1_"),
+ MTK_FUNCTION(2, "SPI_MI_4_"),
+ MTK_FUNCTION(4, "I2S_IQ1_SDIB"),
+ MTK_FUNCTION(5, "I2SO2_BCK"),
+ MTK_FUNCTION(6, "TDMO0_DATA"),
+ MTK_FUNCTION(7, "I2SO0_DO0")
+ ),
+ MTK_PIN(PINCTRL_PIN(163, "SPI1_CK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 168),
+ MTK_FUNCTION(0, "GPIO163"),
+ MTK_FUNCTION(1, "SPI_CK_1_"),
+ MTK_FUNCTION(2, "SPI_CK_4_"),
+ MTK_FUNCTION(4, "I2S_IQ0_SDQB"),
+ MTK_FUNCTION(5, "I2SO2_WS"),
+ MTK_FUNCTION(6, "TDMO0_BCK"),
+ MTK_FUNCTION(7, "I2SO0_BCK")
+ ),
+ MTK_PIN(PINCTRL_PIN(164, "SPI1_SO"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 169),
+ MTK_FUNCTION(0, "GPIO164"),
+ MTK_FUNCTION(1, "SPI_SO_1_"),
+ MTK_FUNCTION(2, "SPI_MO_4_"),
+ MTK_FUNCTION(4, "I2S_IQ0_SDIB"),
+ MTK_FUNCTION(5, "I2SO2_MCK"),
+ MTK_FUNCTION(6, "TDMO0_LRCK"),
+ MTK_FUNCTION(7, "I2SO0_WS")
+ ),
+ MTK_PIN(PINCTRL_PIN(165, "SPI4_CSN"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 170),
+ MTK_FUNCTION(0, "GPIO165"),
+ MTK_FUNCTION(1, "SPI_CS_4_"),
+ MTK_FUNCTION(2, "LCM_RST0"),
+ MTK_FUNCTION(3, "SPI_CS_1_"),
+ MTK_FUNCTION(4, "UTXD4"),
+ MTK_FUNCTION(5, "I2SO1_DO"),
+ MTK_FUNCTION(6, "TDMO0_MCLK"),
+ MTK_FUNCTION(7, "I2SO0_MCK")
+ ),
+ MTK_PIN(PINCTRL_PIN(166, "SPI4_MI"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 171),
+ MTK_FUNCTION(0, "GPIO166"),
+ MTK_FUNCTION(1, "SPI_MI_4_"),
+ MTK_FUNCTION(2, "DSIA_TE"),
+ MTK_FUNCTION(3, "SPI_SI_1_"),
+ MTK_FUNCTION(4, "URXD4"),
+ MTK_FUNCTION(5, "I2SO1_BCK")
+ ),
+ MTK_PIN(PINCTRL_PIN(167, "SPI4_MO"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 172),
+ MTK_FUNCTION(0, "GPIO167"),
+ MTK_FUNCTION(1, "SPI_MO_4_"),
+ MTK_FUNCTION(2, "DSIB_TE"),
+ MTK_FUNCTION(3, "SPI_SO_1_"),
+ MTK_FUNCTION(4, "UTXD5"),
+ MTK_FUNCTION(5, "I2SO1_WS")
+ ),
+ MTK_PIN(PINCTRL_PIN(168, "SPI4_CK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 173),
+ MTK_FUNCTION(0, "GPIO168"),
+ MTK_FUNCTION(1, "SPI_CK_4_"),
+ MTK_FUNCTION(2, "LCM_RST1"),
+ MTK_FUNCTION(3, "SPI_CK_1_"),
+ MTK_FUNCTION(4, "URXD5"),
+ MTK_FUNCTION(5, "I2SO1_MCK")
+ ),
+ MTK_PIN(PINCTRL_PIN(169, "I2SI0_DATA"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 174),
+ MTK_FUNCTION(0, "GPIO169"),
+ MTK_FUNCTION(1, "I2SI0_DI"),
+ MTK_FUNCTION(2, "I2SI1_DI"),
+ MTK_FUNCTION(3, "I2SI2_DI"),
+ MTK_FUNCTION(4, "TDMIN_DI")
+ ),
+ MTK_PIN(PINCTRL_PIN(170, "I2SI0_LRCK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 175),
+ MTK_FUNCTION(0, "GPIO170"),
+ MTK_FUNCTION(1, "I2SI0_WS"),
+ MTK_FUNCTION(2, "I2SI1_WS"),
+ MTK_FUNCTION(3, "I2SI2_WS"),
+ MTK_FUNCTION(4, "TDMIN_LRCK"),
+ MTK_FUNCTION(5, "TDMO0_DATA3"),
+ MTK_FUNCTION(6, "TDMO1_DATA3")
+ ),
+ MTK_PIN(PINCTRL_PIN(171, "I2SI0_MCLK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 176),
+ MTK_FUNCTION(0, "GPIO171"),
+ MTK_FUNCTION(1, "I2SI0_MCK"),
+ MTK_FUNCTION(2, "I2SI1_MCK"),
+ MTK_FUNCTION(3, "I2SI2_MCK"),
+ MTK_FUNCTION(4, "TDMIN_MCLK"),
+ MTK_FUNCTION(5, "TDMO0_DATA2"),
+ MTK_FUNCTION(6, "TDMO1_DATA2")
+ ),
+ MTK_PIN(PINCTRL_PIN(172, "I2SI0_BCK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 177),
+ MTK_FUNCTION(0, "GPIO172"),
+ MTK_FUNCTION(1, "I2SI0_BCK"),
+ MTK_FUNCTION(2, "I2SI1_BCK"),
+ MTK_FUNCTION(3, "I2SI2_BCK"),
+ MTK_FUNCTION(4, "TDMIN_BCK"),
+ MTK_FUNCTION(5, "TDMO0_DATA1"),
+ MTK_FUNCTION(6, "TDMO1_DATA1")
+ ),
+ MTK_PIN(PINCTRL_PIN(173, "I2SI2_DATA"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 178),
+ MTK_FUNCTION(0, "GPIO173"),
+ MTK_FUNCTION(1, "I2SI2_DI"),
+ MTK_FUNCTION(2, "I2SI0_DI"),
+ MTK_FUNCTION(3, "I2SI1_DI"),
+ MTK_FUNCTION(4, "PCM1_DI"),
+ MTK_FUNCTION(5, "TDMIN_DI"),
+ MTK_FUNCTION(6, "PCM1_DO")
+ ),
+ MTK_PIN(PINCTRL_PIN(174, "I2SI2_MCLK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 179),
+ MTK_FUNCTION(0, "GPIO174"),
+ MTK_FUNCTION(1, "I2SI2_MCK"),
+ MTK_FUNCTION(2, "I2SI0_MCK"),
+ MTK_FUNCTION(3, "I2SI1_MCK"),
+ MTK_FUNCTION(4, "PCM1_DO"),
+ MTK_FUNCTION(5, "TDMIN_MCLK"),
+ MTK_FUNCTION(6, "PCM1_DI"),
+ MTK_FUNCTION(7, "I2S_IQ2_SDQB")
+ ),
+ MTK_PIN(PINCTRL_PIN(175, "I2SI2_BCK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 180),
+ MTK_FUNCTION(0, "GPIO175"),
+ MTK_FUNCTION(1, "I2SI2_BCK"),
+ MTK_FUNCTION(2, "I2SI0_BCK"),
+ MTK_FUNCTION(3, "I2SI1_BCK"),
+ MTK_FUNCTION(4, "PCM1_CLK"),
+ MTK_FUNCTION(5, "TDMIN_BCK")
+ ),
+ MTK_PIN(PINCTRL_PIN(176, "I2SI2_LRCK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 181),
+ MTK_FUNCTION(0, "GPIO176"),
+ MTK_FUNCTION(1, "I2SI2_WS"),
+ MTK_FUNCTION(2, "I2SI0_WS"),
+ MTK_FUNCTION(3, "I2SI1_WS"),
+ MTK_FUNCTION(4, "PCM1_SYNC"),
+ MTK_FUNCTION(5, "TDMIN_LRCK")
+ ),
+ MTK_PIN(PINCTRL_PIN(177, "I2SI1_DATA"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 182),
+ MTK_FUNCTION(0, "GPIO177"),
+ MTK_FUNCTION(1, "I2SI1_DI"),
+ MTK_FUNCTION(2, "I2SI0_DI"),
+ MTK_FUNCTION(3, "I2SI2_DI"),
+ MTK_FUNCTION(4, "TDMIN_DI")
+ ),
+ MTK_PIN(PINCTRL_PIN(178, "I2SI1_BCK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 183),
+ MTK_FUNCTION(0, "GPIO178"),
+ MTK_FUNCTION(1, "I2SI1_BCK"),
+ MTK_FUNCTION(2, "I2SI0_BCK"),
+ MTK_FUNCTION(3, "I2SI2_BCK"),
+ MTK_FUNCTION(4, "TDMIN_BCK"),
+ MTK_FUNCTION(5, "TDMO0_DATA3"),
+ MTK_FUNCTION(6, "TDMO1_DATA3")
+ ),
+ MTK_PIN(PINCTRL_PIN(179, "I2SI1_LRCK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 184),
+ MTK_FUNCTION(0, "GPIO179"),
+ MTK_FUNCTION(1, "I2SI1_WS"),
+ MTK_FUNCTION(2, "I2SI0_WS"),
+ MTK_FUNCTION(3, "I2SI2_WS"),
+ MTK_FUNCTION(4, "TDMIN_LRCK"),
+ MTK_FUNCTION(5, "TDMO0_DATA2"),
+ MTK_FUNCTION(6, "TDMO1_DATA2")
+ ),
+ MTK_PIN(PINCTRL_PIN(180, "I2SI1_MCLK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 185),
+ MTK_FUNCTION(0, "GPIO180"),
+ MTK_FUNCTION(1, "I2SI1_MCK"),
+ MTK_FUNCTION(2, "I2SI0_MCK"),
+ MTK_FUNCTION(3, "I2SI2_MCK"),
+ MTK_FUNCTION(4, "TDMIN_MCLK"),
+ MTK_FUNCTION(5, "TDMO0_DATA1"),
+ MTK_FUNCTION(6, "TDMO1_DATA1"),
+ MTK_FUNCTION(7, "I2S_IQ2_SDIB")
+ ),
+ MTK_PIN(PINCTRL_PIN(181, "I2SO1_DATA0"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 186),
+ MTK_FUNCTION(0, "GPIO181"),
+ MTK_FUNCTION(1, "I2SO1_DO"),
+ MTK_FUNCTION(2, "I2SO0_DO0"),
+ MTK_FUNCTION(3, "I2SO2_DO"),
+ MTK_FUNCTION(4, "DAI_TX"),
+ MTK_FUNCTION(5, "TDMIN_MCLK"),
+ MTK_FUNCTION(7, "I2S_IQ2_SDIA")
+ ),
+ MTK_PIN(PINCTRL_PIN(182, "I2SO1_BCK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 187),
+ MTK_FUNCTION(0, "GPIO182"),
+ MTK_FUNCTION(1, "I2SO1_BCK"),
+ MTK_FUNCTION(2, "I2SO0_BCK"),
+ MTK_FUNCTION(3, "I2SO2_BCK"),
+ MTK_FUNCTION(4, "DAI_SYNC"),
+ MTK_FUNCTION(5, "TDMIN_BCK"),
+ MTK_FUNCTION(6, "TDMO0_DATA3"),
+ MTK_FUNCTION(7, "I2S_IQ2_BCK")
+ ),
+ MTK_PIN(PINCTRL_PIN(183, "I2SO1_LRCK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 188),
+ MTK_FUNCTION(0, "GPIO183"),
+ MTK_FUNCTION(1, "I2SO1_WS"),
+ MTK_FUNCTION(2, "I2SO0_WS"),
+ MTK_FUNCTION(3, "I2SO2_WS"),
+ MTK_FUNCTION(4, "DAI_CLK"),
+ MTK_FUNCTION(5, "TDMIN_DI"),
+ MTK_FUNCTION(6, "TDMO0_DATA2"),
+ MTK_FUNCTION(7, "I2S_IQ2_WS")
+ ),
+ MTK_PIN(PINCTRL_PIN(184, "I2SO1_MCLK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 189),
+ MTK_FUNCTION(0, "GPIO184"),
+ MTK_FUNCTION(1, "I2SO1_MCK"),
+ MTK_FUNCTION(2, "I2SO0_MCK"),
+ MTK_FUNCTION(3, "I2SO2_MCK"),
+ MTK_FUNCTION(4, "DAI_RX"),
+ MTK_FUNCTION(5, "TDMIN_LRCK"),
+ MTK_FUNCTION(6, "TDMO0_DATA1"),
+ MTK_FUNCTION(7, "I2S_IQ2_SDQA")
+ ),
+ MTK_PIN(PINCTRL_PIN(185, "AUD_EXT_CK2"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 190),
+ MTK_FUNCTION(0, "GPIO185"),
+ MTK_FUNCTION(1, "AUD_EXT_CK2"),
+ MTK_FUNCTION(2, "AUD_EXT_CK1"),
+ MTK_FUNCTION(3, "I2SO1_DO"),
+ MTK_FUNCTION(4, "I2SI2_DI"),
+ MTK_FUNCTION(5, "MRG_RX"),
+ MTK_FUNCTION(6, "PCM1_DI"),
+ MTK_FUNCTION(7, "I2S_IQ0_SDQB")
+ ),
+ MTK_PIN(PINCTRL_PIN(186, "AUD_EXT_CK1"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 191),
+ MTK_FUNCTION(0, "GPIO186"),
+ MTK_FUNCTION(1, "AUD_EXT_CK1"),
+ MTK_FUNCTION(2, "AUD_EXT_CK2"),
+ MTK_FUNCTION(3, "I2SO0_DO1"),
+ MTK_FUNCTION(4, "I2SI1_DI"),
+ MTK_FUNCTION(5, "MRG_TX"),
+ MTK_FUNCTION(6, "PCM1_DO"),
+ MTK_FUNCTION(7, "I2S_IQ0_SDIB")
+ ),
+ MTK_PIN(PINCTRL_PIN(187, "I2SO2_BCK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 192),
+ MTK_FUNCTION(0, "GPIO187"),
+ MTK_FUNCTION(1, "I2SO2_BCK"),
+ MTK_FUNCTION(2, "I2SO0_BCK"),
+ MTK_FUNCTION(3, "I2SO1_BCK"),
+ MTK_FUNCTION(4, "PCM1_CLK"),
+ MTK_FUNCTION(5, "MRG_SYNC"),
+ MTK_FUNCTION(6, "TDMO1_DATA3"),
+ MTK_FUNCTION(7, "I2S_IQ0_BCK")
+ ),
+ MTK_PIN(PINCTRL_PIN(188, "I2SO2_LRCK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 193),
+ MTK_FUNCTION(0, "GPIO188"),
+ MTK_FUNCTION(1, "I2SO2_WS"),
+ MTK_FUNCTION(2, "I2SO0_WS"),
+ MTK_FUNCTION(3, "I2SO1_WS"),
+ MTK_FUNCTION(4, "PCM1_SYNC"),
+ MTK_FUNCTION(5, "MRG_CLK"),
+ MTK_FUNCTION(6, "TDMO1_DATA2"),
+ MTK_FUNCTION(7, "I2S_IQ0_WS")
+ ),
+ MTK_PIN(PINCTRL_PIN(189, "I2SO2_MCLK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 194),
+ MTK_FUNCTION(0, "GPIO189"),
+ MTK_FUNCTION(1, "I2SO2_MCK"),
+ MTK_FUNCTION(2, "I2SO0_MCK"),
+ MTK_FUNCTION(3, "I2SO1_MCK"),
+ MTK_FUNCTION(4, "PCM1_DO"),
+ MTK_FUNCTION(5, "MRG_RX"),
+ MTK_FUNCTION(6, "TDMO1_DATA1"),
+ MTK_FUNCTION(7, "I2S_IQ0_SDQA")
+ ),
+ MTK_PIN(PINCTRL_PIN(190, "I2SO2_DATA0"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 195),
+ MTK_FUNCTION(0, "GPIO190"),
+ MTK_FUNCTION(1, "I2SO2_DO"),
+ MTK_FUNCTION(2, "I2SO0_DO0"),
+ MTK_FUNCTION(3, "I2SO1_DO"),
+ MTK_FUNCTION(4, "PCM1_DI"),
+ MTK_FUNCTION(5, "MRG_TX"),
+ MTK_FUNCTION(6, "PCM1_DO"),
+ MTK_FUNCTION(7, "I2S_IQ0_SDIA")
+ ),
+ MTK_PIN(PINCTRL_PIN(191, "I2SO0_DATA1"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 196),
+ MTK_FUNCTION(0, "GPIO191"),
+ MTK_FUNCTION(1, "I2SO0_DO1"),
+ MTK_FUNCTION(2, "I2SI0_DI"),
+ MTK_FUNCTION(3, "I2SI1_DI"),
+ MTK_FUNCTION(4, "I2SI2_DI"),
+ MTK_FUNCTION(5, "DAI_TX"),
+ MTK_FUNCTION(6, "I2S_IQ0_SDQB"),
+ MTK_FUNCTION(7, "I2S_IQ1_SDQB")
+ ),
+ MTK_PIN(PINCTRL_PIN(192, "I2SO0_MCLK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 197),
+ MTK_FUNCTION(0, "GPIO192"),
+ MTK_FUNCTION(1, "I2SO0_MCK"),
+ MTK_FUNCTION(2, "I2SO1_MCK"),
+ MTK_FUNCTION(3, "I2SO2_MCK"),
+ MTK_FUNCTION(4, "USB4_FT_SCL"),
+ MTK_FUNCTION(5, "TDMO1_DATA3"),
+ MTK_FUNCTION(6, "I2S_IQ0_SDIB"),
+ MTK_FUNCTION(7, "I2S_IQ1_SDQA")
+ ),
+ MTK_PIN(PINCTRL_PIN(193, "I2SO0_DATA0"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 198),
+ MTK_FUNCTION(0, "GPIO193"),
+ MTK_FUNCTION(1, "I2SO0_DO0"),
+ MTK_FUNCTION(2, "I2SO1_DO"),
+ MTK_FUNCTION(3, "I2SO2_DO"),
+ MTK_FUNCTION(4, "USB4_FT_SDA"),
+ MTK_FUNCTION(7, "I2S_IQ1_SDIA")
+ ),
+ MTK_PIN(PINCTRL_PIN(194, "I2SO0_LRCK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 199),
+ MTK_FUNCTION(0, "GPIO194"),
+ MTK_FUNCTION(1, "I2SO0_WS"),
+ MTK_FUNCTION(2, "I2SO1_WS"),
+ MTK_FUNCTION(3, "I2SO2_WS"),
+ MTK_FUNCTION(4, "USB5_FT_SCL"),
+ MTK_FUNCTION(5, "TDMO1_DATA2"),
+ MTK_FUNCTION(7, "I2S_IQ1_WS")
+ ),
+ MTK_PIN(PINCTRL_PIN(195, "I2SO0_BCK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 200),
+ MTK_FUNCTION(0, "GPIO195"),
+ MTK_FUNCTION(1, "I2SO0_BCK"),
+ MTK_FUNCTION(2, "I2SO1_BCK"),
+ MTK_FUNCTION(3, "I2SO2_BCK"),
+ MTK_FUNCTION(4, "USB5_FT_SDA"),
+ MTK_FUNCTION(5, "TDMO1_DATA1"),
+ MTK_FUNCTION(7, "I2S_IQ1_BCK")
+ ),
+ MTK_PIN(PINCTRL_PIN(196, "TDMO1_MCLK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 201),
+ MTK_FUNCTION(0, "GPIO196"),
+ MTK_FUNCTION(1, "TDMO1_MCLK"),
+ MTK_FUNCTION(2, "TDMO0_MCLK"),
+ MTK_FUNCTION(3, "TDMIN_MCLK"),
+ MTK_FUNCTION(6, "I2SO0_DO1"),
+ MTK_FUNCTION(7, "I2S_IQ1_SDIB")
+ ),
+ MTK_PIN(PINCTRL_PIN(197, "TDMO1_LRCK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 202),
+ MTK_FUNCTION(0, "GPIO197"),
+ MTK_FUNCTION(1, "TDMO1_LRCK"),
+ MTK_FUNCTION(2, "TDMO0_LRCK"),
+ MTK_FUNCTION(3, "TDMIN_LRCK"),
+ MTK_FUNCTION(4, "TDMO0_DATA3"),
+ MTK_FUNCTION(5, "TDMO1_DATA3"),
+ MTK_FUNCTION(6, "I2SO3_MCK"),
+ MTK_FUNCTION(7, "TDMO1_DATA2")
+ ),
+ MTK_PIN(PINCTRL_PIN(198, "TDMO1_BCK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 203),
+ MTK_FUNCTION(0, "GPIO198"),
+ MTK_FUNCTION(1, "TDMO1_BCK"),
+ MTK_FUNCTION(2, "TDMO0_BCK"),
+ MTK_FUNCTION(3, "TDMIN_BCK"),
+ MTK_FUNCTION(4, "TDMO0_DATA2"),
+ MTK_FUNCTION(5, "TDMO1_DATA2"),
+ MTK_FUNCTION(6, "I2SO3_BCK"),
+ MTK_FUNCTION(7, "TDMO1_DATA1")
+ ),
+ MTK_PIN(PINCTRL_PIN(199, "TDMO1_DATA"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 204),
+ MTK_FUNCTION(0, "GPIO199"),
+ MTK_FUNCTION(1, "TDMO1_DATA"),
+ MTK_FUNCTION(2, "TDMO0_DATA"),
+ MTK_FUNCTION(3, "TDMIN_DI"),
+ MTK_FUNCTION(4, "TDMO0_DATA1"),
+ MTK_FUNCTION(5, "TDMO1_DATA1"),
+ MTK_FUNCTION(6, "I2SO3_WS")
+ ),
+ MTK_PIN(PINCTRL_PIN(200, "TDMO0_MCLK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 205),
+ MTK_FUNCTION(0, "GPIO200"),
+ MTK_FUNCTION(1, "TDMO0_MCLK"),
+ MTK_FUNCTION(2, "TDMO1_MCLK"),
+ MTK_FUNCTION(3, "PCM1_DI"),
+ MTK_FUNCTION(4, "TDMO0_MCLK"),
+ MTK_FUNCTION(5, "TDMO1_MCLK"),
+ MTK_FUNCTION(6, "MRG_TX"),
+ MTK_FUNCTION(7, "I2SO2_MCK")
+ ),
+ MTK_PIN(PINCTRL_PIN(201, "TDMO0_LRCK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 206),
+ MTK_FUNCTION(0, "GPIO201"),
+ MTK_FUNCTION(1, "TDMO0_LRCK"),
+ MTK_FUNCTION(2, "TDMO1_LRCK"),
+ MTK_FUNCTION(3, "PCM1_SYNC"),
+ MTK_FUNCTION(4, "TDMO0_LRCK"),
+ MTK_FUNCTION(5, "TDMO1_LRCK"),
+ MTK_FUNCTION(6, "MRG_RX"),
+ MTK_FUNCTION(7, "I2SO2_WS")
+ ),
+ MTK_PIN(PINCTRL_PIN(202, "TDMO0_BCK"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 207),
+ MTK_FUNCTION(0, "GPIO202"),
+ MTK_FUNCTION(1, "TDMO0_BCK"),
+ MTK_FUNCTION(2, "TDMO1_BCK"),
+ MTK_FUNCTION(3, "PCM1_CLK"),
+ MTK_FUNCTION(4, "TDMO0_BCK"),
+ MTK_FUNCTION(5, "TDMO1_BCK"),
+ MTK_FUNCTION(6, "MRG_SYNC"),
+ MTK_FUNCTION(7, "I2SO2_BCK")
+ ),
+ MTK_PIN(PINCTRL_PIN(203, "TDMO0_DATA"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 208),
+ MTK_FUNCTION(0, "GPIO203"),
+ MTK_FUNCTION(1, "TDMO0_DATA"),
+ MTK_FUNCTION(2, "TDMO1_DATA"),
+ MTK_FUNCTION(3, "PCM1_DO"),
+ MTK_FUNCTION(4, "TDMO0_DATA"),
+ MTK_FUNCTION(5, "TDMO1_DATA"),
+ MTK_FUNCTION(6, "MRG_CLK"),
+ MTK_FUNCTION(7, "I2SO2_DO")
+ ),
+ MTK_PIN(PINCTRL_PIN(204, "PERSTB_P0"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 209),
+ MTK_FUNCTION(0, "GPIO204"),
+ MTK_FUNCTION(1, "PERST_B_P0")
+ ),
+ MTK_PIN(PINCTRL_PIN(205, "CLKREQN_P0"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 210),
+ MTK_FUNCTION(0, "GPIO205"),
+ MTK_FUNCTION(1, "CLKREQ_N_P0")
+ ),
+ MTK_PIN(PINCTRL_PIN(206, "WAKEEN_P0"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 211),
+ MTK_FUNCTION(0, "GPIO206"),
+ MTK_FUNCTION(1, "WAKE_EN_P0")
+ ),
+ MTK_PIN(PINCTRL_PIN(207, "PERSTB_P1"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 212),
+ MTK_FUNCTION(0, "GPIO207"),
+ MTK_FUNCTION(1, "PERST_B_P1")
+ ),
+ MTK_PIN(PINCTRL_PIN(208, "CLKREQN_P1"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 213),
+ MTK_FUNCTION(0, "GPIO208"),
+ MTK_FUNCTION(1, "CLKREQ_N_P1")
+ ),
+ MTK_PIN(PINCTRL_PIN(209, "WAKEEN_P1"),
+ NULL, "mt2712",
+ MTK_EINT_FUNCTION(0, 214),
+ MTK_FUNCTION(0, "GPIO209"),
+ MTK_FUNCTION(1, "WAKE_EN_P1")
+ ),
+};
+
+#endif /* __PINCTRL_MTK_MT2712_H */
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h
index 17df4cfbde4e..0622293ab7b8 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h
@@ -6,74 +6,64 @@
#include "pinctrl-mtk-common.h"
static const struct mtk_desc_pin mtk_pins_mt6397[] = {
- MTK_PIN(
- PINCTRL_PIN(0, "INT"),
+ MTK_PIN(PINCTRL_PIN(0, "INT"),
"N2", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO0"),
MTK_FUNCTION(1, "INT")
),
- MTK_PIN(
- PINCTRL_PIN(1, "SRCVOLTEN"),
+ MTK_PIN(PINCTRL_PIN(1, "SRCVOLTEN"),
"M4", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO1"),
MTK_FUNCTION(1, "SRCVOLTEN"),
MTK_FUNCTION(6, "TEST_CK1")
),
- MTK_PIN(
- PINCTRL_PIN(2, "SRCLKEN_PERI"),
+ MTK_PIN(PINCTRL_PIN(2, "SRCLKEN_PERI"),
"M2", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO2"),
MTK_FUNCTION(1, "SRCLKEN_PERI"),
MTK_FUNCTION(6, "TEST_CK2")
),
- MTK_PIN(
- PINCTRL_PIN(3, "RTC_32K1V8"),
+ MTK_PIN(PINCTRL_PIN(3, "RTC_32K1V8"),
"K3", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO3"),
MTK_FUNCTION(1, "RTC_32K1V8"),
MTK_FUNCTION(6, "TEST_CK3")
),
- MTK_PIN(
- PINCTRL_PIN(4, "WRAP_EVENT"),
+ MTK_PIN(PINCTRL_PIN(4, "WRAP_EVENT"),
"J2", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO4"),
MTK_FUNCTION(1, "WRAP_EVENT")
),
- MTK_PIN(
- PINCTRL_PIN(5, "SPI_CLK"),
+ MTK_PIN(PINCTRL_PIN(5, "SPI_CLK"),
"L4", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO5"),
MTK_FUNCTION(1, "SPI_CLK")
),
- MTK_PIN(
- PINCTRL_PIN(6, "SPI_CSN"),
+ MTK_PIN(PINCTRL_PIN(6, "SPI_CSN"),
"J3", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO6"),
MTK_FUNCTION(1, "SPI_CSN")
),
- MTK_PIN(
- PINCTRL_PIN(7, "SPI_MOSI"),
+ MTK_PIN(PINCTRL_PIN(7, "SPI_MOSI"),
"J1", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO7"),
MTK_FUNCTION(1, "SPI_MOSI")
),
- MTK_PIN(
- PINCTRL_PIN(8, "SPI_MISO"),
+ MTK_PIN(PINCTRL_PIN(8, "SPI_MISO"),
"L3", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO8"),
MTK_FUNCTION(1, "SPI_MISO")
),
- MTK_PIN(
- PINCTRL_PIN(9, "AUD_CLK_MOSI"),
+ MTK_PIN(PINCTRL_PIN(9, "AUD_CLK_MOSI"),
"H2", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO9"),
@@ -81,8 +71,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN0"),
MTK_FUNCTION(7, "TEST_OUT0")
),
- MTK_PIN(
- PINCTRL_PIN(10, "AUD_DAT_MISO"),
+ MTK_PIN(PINCTRL_PIN(10, "AUD_DAT_MISO"),
"H3", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO10"),
@@ -90,8 +79,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN1"),
MTK_FUNCTION(7, "TEST_OUT1")
),
- MTK_PIN(
- PINCTRL_PIN(11, "AUD_DAT_MOSI"),
+ MTK_PIN(PINCTRL_PIN(11, "AUD_DAT_MOSI"),
"H1", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO11"),
@@ -99,8 +87,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN2"),
MTK_FUNCTION(7, "TEST_OUT2")
),
- MTK_PIN(
- PINCTRL_PIN(12, "COL0"),
+ MTK_PIN(PINCTRL_PIN(12, "COL0"),
"F3", "mt6397",
MTK_EINT_FUNCTION(2, 10),
MTK_FUNCTION(0, "GPIO12"),
@@ -110,8 +97,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN3"),
MTK_FUNCTION(7, "TEST_OUT3")
),
- MTK_PIN(
- PINCTRL_PIN(13, "COL1"),
+ MTK_PIN(PINCTRL_PIN(13, "COL1"),
"G8", "mt6397",
MTK_EINT_FUNCTION(2, 11),
MTK_FUNCTION(0, "GPIO13"),
@@ -121,8 +107,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN4"),
MTK_FUNCTION(7, "TEST_OUT4")
),
- MTK_PIN(
- PINCTRL_PIN(14, "COL2"),
+ MTK_PIN(PINCTRL_PIN(14, "COL2"),
"H4", "mt6397",
MTK_EINT_FUNCTION(2, 12),
MTK_FUNCTION(0, "GPIO14"),
@@ -132,8 +117,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN5"),
MTK_FUNCTION(7, "TEST_OUT5")
),
- MTK_PIN(
- PINCTRL_PIN(15, "COL3"),
+ MTK_PIN(PINCTRL_PIN(15, "COL3"),
"G2", "mt6397",
MTK_EINT_FUNCTION(2, 13),
MTK_FUNCTION(0, "GPIO15"),
@@ -143,8 +127,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN6"),
MTK_FUNCTION(7, "TEST_OUT6")
),
- MTK_PIN(
- PINCTRL_PIN(16, "COL4"),
+ MTK_PIN(PINCTRL_PIN(16, "COL4"),
"F2", "mt6397",
MTK_EINT_FUNCTION(2, 14),
MTK_FUNCTION(0, "GPIO16"),
@@ -154,8 +137,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN7"),
MTK_FUNCTION(7, "TEST_OUT7")
),
- MTK_PIN(
- PINCTRL_PIN(17, "COL5"),
+ MTK_PIN(PINCTRL_PIN(17, "COL5"),
"G7", "mt6397",
MTK_EINT_FUNCTION(2, 15),
MTK_FUNCTION(0, "GPIO17"),
@@ -165,8 +147,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN8"),
MTK_FUNCTION(7, "TEST_OUT8")
),
- MTK_PIN(
- PINCTRL_PIN(18, "COL6"),
+ MTK_PIN(PINCTRL_PIN(18, "COL6"),
"J6", "mt6397",
MTK_EINT_FUNCTION(2, 16),
MTK_FUNCTION(0, "GPIO18"),
@@ -178,8 +159,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN9"),
MTK_FUNCTION(7, "TEST_OUT9")
),
- MTK_PIN(
- PINCTRL_PIN(19, "COL7"),
+ MTK_PIN(PINCTRL_PIN(19, "COL7"),
"J5", "mt6397",
MTK_EINT_FUNCTION(2, 17),
MTK_FUNCTION(0, "GPIO19"),
@@ -191,8 +171,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN10"),
MTK_FUNCTION(7, "TEST_OUT10")
),
- MTK_PIN(
- PINCTRL_PIN(20, "ROW0"),
+ MTK_PIN(PINCTRL_PIN(20, "ROW0"),
"L7", "mt6397",
MTK_EINT_FUNCTION(2, 18),
MTK_FUNCTION(0, "GPIO20"),
@@ -202,8 +181,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN11"),
MTK_FUNCTION(7, "TEST_OUT11")
),
- MTK_PIN(
- PINCTRL_PIN(21, "ROW1"),
+ MTK_PIN(PINCTRL_PIN(21, "ROW1"),
"P1", "mt6397",
MTK_EINT_FUNCTION(2, 19),
MTK_FUNCTION(0, "GPIO21"),
@@ -214,8 +192,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN12"),
MTK_FUNCTION(7, "TEST_OUT12")
),
- MTK_PIN(
- PINCTRL_PIN(22, "ROW2"),
+ MTK_PIN(PINCTRL_PIN(22, "ROW2"),
"J8", "mt6397",
MTK_EINT_FUNCTION(2, 20),
MTK_FUNCTION(0, "GPIO22"),
@@ -225,8 +202,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN13"),
MTK_FUNCTION(7, "TEST_OUT13")
),
- MTK_PIN(
- PINCTRL_PIN(23, "ROW3"),
+ MTK_PIN(PINCTRL_PIN(23, "ROW3"),
"J7", "mt6397",
MTK_EINT_FUNCTION(2, 21),
MTK_FUNCTION(0, "GPIO23"),
@@ -236,8 +212,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN14"),
MTK_FUNCTION(7, "TEST_OUT14")
),
- MTK_PIN(
- PINCTRL_PIN(24, "ROW4"),
+ MTK_PIN(PINCTRL_PIN(24, "ROW4"),
"L5", "mt6397",
MTK_EINT_FUNCTION(2, 22),
MTK_FUNCTION(0, "GPIO24"),
@@ -247,8 +222,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN15"),
MTK_FUNCTION(7, "TEST_OUT15")
),
- MTK_PIN(
- PINCTRL_PIN(25, "ROW5"),
+ MTK_PIN(PINCTRL_PIN(25, "ROW5"),
"N6", "mt6397",
MTK_EINT_FUNCTION(2, 23),
MTK_FUNCTION(0, "GPIO25"),
@@ -258,8 +232,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN16"),
MTK_FUNCTION(7, "TEST_OUT16")
),
- MTK_PIN(
- PINCTRL_PIN(26, "ROW6"),
+ MTK_PIN(PINCTRL_PIN(26, "ROW6"),
"L6", "mt6397",
MTK_EINT_FUNCTION(2, 24),
MTK_FUNCTION(0, "GPIO26"),
@@ -271,8 +244,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN17"),
MTK_FUNCTION(7, "TEST_OUT17")
),
- MTK_PIN(
- PINCTRL_PIN(27, "ROW7"),
+ MTK_PIN(PINCTRL_PIN(27, "ROW7"),
"P2", "mt6397",
MTK_EINT_FUNCTION(2, 3),
MTK_FUNCTION(0, "GPIO27"),
@@ -284,8 +256,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN18"),
MTK_FUNCTION(7, "TEST_OUT18")
),
- MTK_PIN(
- PINCTRL_PIN(28, "PWM1(VMSEL1)"),
+ MTK_PIN(PINCTRL_PIN(28, "PWM1(VMSEL1)"),
"J4", "mt6397",
MTK_EINT_FUNCTION(2, 4),
MTK_FUNCTION(0, "GPIO28"),
@@ -296,8 +267,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN19"),
MTK_FUNCTION(7, "TEST_OUT19")
),
- MTK_PIN(
- PINCTRL_PIN(29, "PWM2(VMSEL2)"),
+ MTK_PIN(PINCTRL_PIN(29, "PWM2(VMSEL2)"),
"N5", "mt6397",
MTK_EINT_FUNCTION(2, 5),
MTK_FUNCTION(0, "GPIO29"),
@@ -308,8 +278,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN20"),
MTK_FUNCTION(7, "TEST_OUT20")
),
- MTK_PIN(
- PINCTRL_PIN(30, "PWM3(PWM)"),
+ MTK_PIN(PINCTRL_PIN(30, "PWM3(PWM)"),
"R3", "mt6397",
MTK_EINT_FUNCTION(2, 6),
MTK_FUNCTION(0, "GPIO30"),
@@ -321,8 +290,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN21"),
MTK_FUNCTION(7, "TEST_OUT21")
),
- MTK_PIN(
- PINCTRL_PIN(31, "SCL0"),
+ MTK_PIN(PINCTRL_PIN(31, "SCL0"),
"N1", "mt6397",
MTK_EINT_FUNCTION(2, 7),
MTK_FUNCTION(0, "GPIO31"),
@@ -332,8 +300,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN22"),
MTK_FUNCTION(7, "TEST_OUT22")
),
- MTK_PIN(
- PINCTRL_PIN(32, "SDA0"),
+ MTK_PIN(PINCTRL_PIN(32, "SDA0"),
"N3", "mt6397",
MTK_EINT_FUNCTION(2, 8),
MTK_FUNCTION(0, "GPIO32"),
@@ -342,8 +309,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN23"),
MTK_FUNCTION(7, "TEST_OUT23")
),
- MTK_PIN(
- PINCTRL_PIN(33, "SCL1"),
+ MTK_PIN(PINCTRL_PIN(33, "SCL1"),
"T1", "mt6397",
MTK_EINT_FUNCTION(2, 9),
MTK_FUNCTION(0, "GPIO33"),
@@ -353,8 +319,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN24"),
MTK_FUNCTION(7, "TEST_OUT24")
),
- MTK_PIN(
- PINCTRL_PIN(34, "SDA1"),
+ MTK_PIN(PINCTRL_PIN(34, "SDA1"),
"T2", "mt6397",
MTK_EINT_FUNCTION(2, 0),
MTK_FUNCTION(0, "GPIO34"),
@@ -363,8 +328,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN25"),
MTK_FUNCTION(7, "TEST_OUT25")
),
- MTK_PIN(
- PINCTRL_PIN(35, "SCL2"),
+ MTK_PIN(PINCTRL_PIN(35, "SCL2"),
"T3", "mt6397",
MTK_EINT_FUNCTION(2, 1),
MTK_FUNCTION(0, "GPIO35"),
@@ -374,8 +338,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN26"),
MTK_FUNCTION(7, "TEST_OUT26")
),
- MTK_PIN(
- PINCTRL_PIN(36, "SDA2"),
+ MTK_PIN(PINCTRL_PIN(36, "SDA2"),
"U2", "mt6397",
MTK_EINT_FUNCTION(2, 2),
MTK_FUNCTION(0, "GPIO36"),
@@ -384,8 +347,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN27"),
MTK_FUNCTION(7, "TEST_OUT27")
),
- MTK_PIN(
- PINCTRL_PIN(37, "HDMISD"),
+ MTK_PIN(PINCTRL_PIN(37, "HDMISD"),
"H6", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO37"),
@@ -393,8 +355,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN28"),
MTK_FUNCTION(7, "TEST_OUT28")
),
- MTK_PIN(
- PINCTRL_PIN(38, "HDMISCK"),
+ MTK_PIN(PINCTRL_PIN(38, "HDMISCK"),
"H5", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO38"),
@@ -402,8 +363,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN29"),
MTK_FUNCTION(7, "TEST_OUT29")
),
- MTK_PIN(
- PINCTRL_PIN(39, "HTPLG"),
+ MTK_PIN(PINCTRL_PIN(39, "HTPLG"),
"H7", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO39"),
@@ -411,8 +371,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN30"),
MTK_FUNCTION(7, "TEST_OUT30")
),
- MTK_PIN(
- PINCTRL_PIN(40, "CEC"),
+ MTK_PIN(PINCTRL_PIN(40, "CEC"),
"J9", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO40"),
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h
index 850483d7d9be..0a1254f96e95 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h
@@ -6,44 +6,38 @@
#include "pinctrl-mtk-common.h"
static const struct mtk_desc_pin mtk_pins_mt8127[] = {
- MTK_PIN(
- PINCTRL_PIN(0, "PWRAP_SPI0_MI"),
+ MTK_PIN(PINCTRL_PIN(0, "PWRAP_SPI0_MI"),
"P22", "mt8127",
MTK_EINT_FUNCTION(0, 22),
MTK_FUNCTION(0, "GPIO0"),
MTK_FUNCTION(1, "PWRAP_SPIDO"),
MTK_FUNCTION(2, "PWRAP_SPIDI")
),
- MTK_PIN(
- PINCTRL_PIN(1, "PWRAP_SPI0_MO"),
+ MTK_PIN(PINCTRL_PIN(1, "PWRAP_SPI0_MO"),
"M22", "mt8127",
MTK_EINT_FUNCTION(0, 23),
MTK_FUNCTION(0, "GPIO1"),
MTK_FUNCTION(1, "PWRAP_SPIDI"),
MTK_FUNCTION(2, "PWRAP_SPIDO")
),
- MTK_PIN(
- PINCTRL_PIN(2, "PWRAP_INT"),
+ MTK_PIN(PINCTRL_PIN(2, "PWRAP_INT"),
"L23", "mt8127",
MTK_EINT_FUNCTION(0, 24),
MTK_FUNCTION(0, "GPIO2")
),
- MTK_PIN(
- PINCTRL_PIN(3, "PWRAP_SPI0_CK"),
+ MTK_PIN(PINCTRL_PIN(3, "PWRAP_SPI0_CK"),
"N23", "mt8127",
MTK_EINT_FUNCTION(0, 25),
MTK_FUNCTION(0, "GPIO3"),
MTK_FUNCTION(1, "PWRAP_SPICK_I")
),
- MTK_PIN(
- PINCTRL_PIN(4, "PWRAP_SPI0_CSN"),
+ MTK_PIN(PINCTRL_PIN(4, "PWRAP_SPI0_CSN"),
"N22", "mt8127",
MTK_EINT_FUNCTION(0, 26),
MTK_FUNCTION(0, "GPIO4"),
MTK_FUNCTION(1, "PWRAP_SPICS_B_I")
),
- MTK_PIN(
- PINCTRL_PIN(5, "PWRAP_SPI0_CK2"),
+ MTK_PIN(PINCTRL_PIN(5, "PWRAP_SPI0_CK2"),
"L19", "mt8127",
MTK_EINT_FUNCTION(0, 27),
MTK_FUNCTION(0, "GPIO5"),
@@ -52,8 +46,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(3, "VDEC_TEST_CK"),
MTK_FUNCTION(7, "DBG_MON_B[0]")
),
- MTK_PIN(
- PINCTRL_PIN(6, "PWRAP_SPI0_CSN2"),
+ MTK_PIN(PINCTRL_PIN(6, "PWRAP_SPI0_CSN2"),
"M23", "mt8127",
MTK_EINT_FUNCTION(0, 28),
MTK_FUNCTION(0, "GPIO6"),
@@ -62,16 +55,14 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(3, "MM_TEST_CK"),
MTK_FUNCTION(7, "DBG_MON_B[1]")
),
- MTK_PIN(
- PINCTRL_PIN(7, "AUD_CLK_MOSI"),
+ MTK_PIN(PINCTRL_PIN(7, "AUD_CLK_MOSI"),
"K23", "mt8127",
MTK_EINT_FUNCTION(0, 29),
MTK_FUNCTION(0, "GPIO7"),
MTK_FUNCTION(1, "AUD_CLK"),
MTK_FUNCTION(2, "ADC_CK")
),
- MTK_PIN(
- PINCTRL_PIN(8, "AUD_DAT_MISO"),
+ MTK_PIN(PINCTRL_PIN(8, "AUD_DAT_MISO"),
"K24", "mt8127",
MTK_EINT_FUNCTION(0, 30),
MTK_FUNCTION(0, "GPIO8"),
@@ -79,8 +70,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(2, "ADC_DAT_IN"),
MTK_FUNCTION(3, "AUD_MOSI")
),
- MTK_PIN(
- PINCTRL_PIN(9, "AUD_DAT_MOSI"),
+ MTK_PIN(PINCTRL_PIN(9, "AUD_DAT_MOSI"),
"K22", "mt8127",
MTK_EINT_FUNCTION(0, 31),
MTK_FUNCTION(0, "GPIO9"),
@@ -88,36 +78,31 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(2, "ADC_WS"),
MTK_FUNCTION(3, "AUD_MISO")
),
- MTK_PIN(
- PINCTRL_PIN(10, "RTC32K_CK"),
+ MTK_PIN(PINCTRL_PIN(10, "RTC32K_CK"),
"R21", "mt8127",
MTK_EINT_FUNCTION(0, 32),
MTK_FUNCTION(0, "GPIO10"),
MTK_FUNCTION(1, "RTC32K_CK")
),
- MTK_PIN(
- PINCTRL_PIN(11, "WATCHDOG"),
+ MTK_PIN(PINCTRL_PIN(11, "WATCHDOG"),
"P24", "mt8127",
MTK_EINT_FUNCTION(0, 33),
MTK_FUNCTION(0, "GPIO11"),
MTK_FUNCTION(1, "WATCHDOG")
),
- MTK_PIN(
- PINCTRL_PIN(12, "SRCLKENA"),
+ MTK_PIN(PINCTRL_PIN(12, "SRCLKENA"),
"R22", "mt8127",
MTK_EINT_FUNCTION(0, 34),
MTK_FUNCTION(0, "GPIO12"),
MTK_FUNCTION(1, "SRCLKENA")
),
- MTK_PIN(
- PINCTRL_PIN(13, "SRCLKENAI"),
+ MTK_PIN(PINCTRL_PIN(13, "SRCLKENAI"),
"P23", "mt8127",
MTK_EINT_FUNCTION(0, 35),
MTK_FUNCTION(0, "GPIO13"),
MTK_FUNCTION(1, "SRCLKENAI")
),
- MTK_PIN(
- PINCTRL_PIN(14, "URXD2"),
+ MTK_PIN(PINCTRL_PIN(14, "URXD2"),
"U19", "mt8127",
MTK_EINT_FUNCTION(0, 36),
MTK_FUNCTION(0, "GPIO14"),
@@ -127,8 +112,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(5, "SRCCLKENAI2"),
MTK_FUNCTION(6, "KROW4")
),
- MTK_PIN(
- PINCTRL_PIN(15, "UTXD2"),
+ MTK_PIN(PINCTRL_PIN(15, "UTXD2"),
"U20", "mt8127",
MTK_EINT_FUNCTION(0, 37),
MTK_FUNCTION(0, "GPIO15"),
@@ -137,8 +121,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(3, "URXD2"),
MTK_FUNCTION(6, "KROW5")
),
- MTK_PIN(
- PINCTRL_PIN(16, "URXD3"),
+ MTK_PIN(PINCTRL_PIN(16, "URXD3"),
"U18", "mt8127",
MTK_EINT_FUNCTION(0, 38),
MTK_FUNCTION(0, "GPIO16"),
@@ -149,8 +132,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(5, "PWM3"),
MTK_FUNCTION(6, "KROW6")
),
- MTK_PIN(
- PINCTRL_PIN(17, "UTXD3"),
+ MTK_PIN(PINCTRL_PIN(17, "UTXD3"),
"R18", "mt8127",
MTK_EINT_FUNCTION(0, 39),
MTK_FUNCTION(0, "GPIO17"),
@@ -161,8 +143,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(5, "PWM4"),
MTK_FUNCTION(6, "KROW7")
),
- MTK_PIN(
- PINCTRL_PIN(18, "PCM_CLK"),
+ MTK_PIN(PINCTRL_PIN(18, "PCM_CLK"),
"U22", "mt8127",
MTK_EINT_FUNCTION(0, 40),
MTK_FUNCTION(0, "GPIO18"),
@@ -174,8 +155,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "IR"),
MTK_FUNCTION(7, "DBG_MON_A[0]")
),
- MTK_PIN(
- PINCTRL_PIN(19, "PCM_SYNC"),
+ MTK_PIN(PINCTRL_PIN(19, "PCM_SYNC"),
"U23", "mt8127",
MTK_EINT_FUNCTION(0, 41),
MTK_FUNCTION(0, "GPIO19"),
@@ -187,8 +167,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "EXT_COL"),
MTK_FUNCTION(7, "DBG_MON_A[1]")
),
- MTK_PIN(
- PINCTRL_PIN(20, "PCM_RX"),
+ MTK_PIN(PINCTRL_PIN(20, "PCM_RX"),
"V22", "mt8127",
MTK_EINT_FUNCTION(0, 42),
MTK_FUNCTION(0, "GPIO20"),
@@ -200,8 +179,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "EXT_MDIO"),
MTK_FUNCTION(7, "DBG_MON_A[2]")
),
- MTK_PIN(
- PINCTRL_PIN(21, "PCM_TX"),
+ MTK_PIN(PINCTRL_PIN(21, "PCM_TX"),
"U21", "mt8127",
MTK_EINT_FUNCTION(0, 43),
MTK_FUNCTION(0, "GPIO21"),
@@ -213,8 +191,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "EXT_MDC"),
MTK_FUNCTION(7, "DBG_MON_A[3]")
),
- MTK_PIN(
- PINCTRL_PIN(22, "EINT0"),
+ MTK_PIN(PINCTRL_PIN(22, "EINT0"),
"AB19", "mt8127",
MTK_EINT_FUNCTION(0, 0),
MTK_FUNCTION(0, "GPIO22"),
@@ -224,8 +201,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(5, "CONN_DSP_JDO"),
MTK_FUNCTION(7, "DBG_MON_A[4]")
),
- MTK_PIN(
- PINCTRL_PIN(23, "EINT1"),
+ MTK_PIN(PINCTRL_PIN(23, "EINT1"),
"AA21", "mt8127",
MTK_EINT_FUNCTION(0, 1),
MTK_FUNCTION(0, "GPIO23"),
@@ -235,8 +211,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(5, "CONN_MCU_TDO"),
MTK_FUNCTION(7, "DBG_MON_A[5]")
),
- MTK_PIN(
- PINCTRL_PIN(24, "EINT2"),
+ MTK_PIN(PINCTRL_PIN(24, "EINT2"),
"AA19", "mt8127",
MTK_EINT_FUNCTION(0, 2),
MTK_FUNCTION(0, "GPIO24"),
@@ -247,8 +222,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "KCOL4"),
MTK_FUNCTION(7, "DBG_MON_A[6]")
),
- MTK_PIN(
- PINCTRL_PIN(25, "EINT3"),
+ MTK_PIN(PINCTRL_PIN(25, "EINT3"),
"Y19", "mt8127",
MTK_EINT_FUNCTION(0, 3),
MTK_FUNCTION(0, "GPIO25"),
@@ -260,8 +234,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "KCOL5"),
MTK_FUNCTION(7, "DBG_MON_A[7]")
),
- MTK_PIN(
- PINCTRL_PIN(26, "EINT4"),
+ MTK_PIN(PINCTRL_PIN(26, "EINT4"),
"V21", "mt8127",
MTK_EINT_FUNCTION(0, 4),
MTK_FUNCTION(0, "GPIO26"),
@@ -273,8 +246,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "CONN_MCU_AICE_JCKC"),
MTK_FUNCTION(7, "DBG_MON_A[8]")
),
- MTK_PIN(
- PINCTRL_PIN(27, "EINT5"),
+ MTK_PIN(PINCTRL_PIN(27, "EINT5"),
"AB22", "mt8127",
MTK_EINT_FUNCTION(0, 5),
MTK_FUNCTION(0, "GPIO27"),
@@ -286,8 +258,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "KCOL6"),
MTK_FUNCTION(7, "DBG_MON_A[9]")
),
- MTK_PIN(
- PINCTRL_PIN(28, "EINT6"),
+ MTK_PIN(PINCTRL_PIN(28, "EINT6"),
"AA23", "mt8127",
MTK_EINT_FUNCTION(0, 6),
MTK_FUNCTION(0, "GPIO28"),
@@ -299,8 +270,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "KCOL7"),
MTK_FUNCTION(7, "DBG_MON_A[10]")
),
- MTK_PIN(
- PINCTRL_PIN(29, "EINT7"),
+ MTK_PIN(PINCTRL_PIN(29, "EINT7"),
"Y23", "mt8127",
MTK_EINT_FUNCTION(0, 7),
MTK_FUNCTION(0, "GPIO29"),
@@ -312,8 +282,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "CONN_MCU_AICE_JMSC"),
MTK_FUNCTION(7, "DBG_MON_A[11]")
),
- MTK_PIN(
- PINCTRL_PIN(30, "EINT8"),
+ MTK_PIN(PINCTRL_PIN(30, "EINT8"),
"Y24", "mt8127",
MTK_EINT_FUNCTION(0, 8),
MTK_FUNCTION(0, "GPIO30"),
@@ -325,8 +294,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "DPI_D7"),
MTK_FUNCTION(7, "DBG_MON_B[2]")
),
- MTK_PIN(
- PINCTRL_PIN(31, "EINT9"),
+ MTK_PIN(PINCTRL_PIN(31, "EINT9"),
"W23", "mt8127",
MTK_EINT_FUNCTION(0, 9),
MTK_FUNCTION(0, "GPIO31"),
@@ -338,8 +306,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "DPI_D8"),
MTK_FUNCTION(7, "DBG_MON_B[3]")
),
- MTK_PIN(
- PINCTRL_PIN(32, "EINT10"),
+ MTK_PIN(PINCTRL_PIN(32, "EINT10"),
"W24", "mt8127",
MTK_EINT_FUNCTION(0, 10),
MTK_FUNCTION(0, "GPIO32"),
@@ -351,8 +318,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "DPI_D9"),
MTK_FUNCTION(7, "DBG_MON_B[4]")
),
- MTK_PIN(
- PINCTRL_PIN(33, "KPROW0"),
+ MTK_PIN(PINCTRL_PIN(33, "KPROW0"),
"AB24", "mt8127",
MTK_EINT_FUNCTION(0, 44),
MTK_FUNCTION(0, "GPIO33"),
@@ -360,8 +326,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(4, "IMG_TEST_CK"),
MTK_FUNCTION(7, "DBG_MON_A[12]")
),
- MTK_PIN(
- PINCTRL_PIN(34, "KPROW1"),
+ MTK_PIN(PINCTRL_PIN(34, "KPROW1"),
"AC24", "mt8127",
MTK_EINT_FUNCTION(0, 45),
MTK_FUNCTION(0, "GPIO34"),
@@ -371,8 +336,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(4, "MFG_TEST_CK"),
MTK_FUNCTION(7, "DBG_MON_B[5]")
),
- MTK_PIN(
- PINCTRL_PIN(35, "KPROW2"),
+ MTK_PIN(PINCTRL_PIN(35, "KPROW2"),
"AD24", "mt8127",
MTK_EINT_FUNCTION(0, 46),
MTK_FUNCTION(0, "GPIO35"),
@@ -382,24 +346,21 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(4, "CONN_TEST_CK"),
MTK_FUNCTION(7, "DBG_MON_B[6]")
),
- MTK_PIN(
- PINCTRL_PIN(36, "KPCOL0"),
+ MTK_PIN(PINCTRL_PIN(36, "KPCOL0"),
"AB23", "mt8127",
MTK_EINT_FUNCTION(0, 47),
MTK_FUNCTION(0, "GPIO36"),
MTK_FUNCTION(1, "KCOL0"),
MTK_FUNCTION(7, "DBG_MON_A[13]")
),
- MTK_PIN(
- PINCTRL_PIN(37, "KPCOL1"),
+ MTK_PIN(PINCTRL_PIN(37, "KPCOL1"),
"AC22", "mt8127",
MTK_EINT_FUNCTION(0, 48),
MTK_FUNCTION(0, "GPIO37"),
MTK_FUNCTION(1, "KCOL1"),
MTK_FUNCTION(7, "DBG_MON_B[7]")
),
- MTK_PIN(
- PINCTRL_PIN(38, "KPCOL2"),
+ MTK_PIN(PINCTRL_PIN(38, "KPCOL2"),
"AC23", "mt8127",
MTK_EINT_FUNCTION(0, 49),
MTK_FUNCTION(0, "GPIO38"),
@@ -408,8 +369,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
MTK_FUNCTION(7, "DBG_MON_B[8]")
),
- MTK_PIN(
- PINCTRL_PIN(39, "JTMS"),
+ MTK_PIN(PINCTRL_PIN(39, "JTMS"),
"V18", "mt8127",
MTK_EINT_FUNCTION(0, 50),
MTK_FUNCTION(0, "GPIO39"),
@@ -417,8 +377,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(2, "CONN_MCU_TMS"),
MTK_FUNCTION(3, "CONN_MCU_AICE_JMSC")
),
- MTK_PIN(
- PINCTRL_PIN(40, "JTCK"),
+ MTK_PIN(PINCTRL_PIN(40, "JTCK"),
"AA18", "mt8127",
MTK_EINT_FUNCTION(0, 51),
MTK_FUNCTION(0, "GPIO40"),
@@ -426,24 +385,21 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(2, "CONN_MCU_TCK1"),
MTK_FUNCTION(3, "CONN_MCU_AICE_JCKC")
),
- MTK_PIN(
- PINCTRL_PIN(41, "JTDI"),
+ MTK_PIN(PINCTRL_PIN(41, "JTDI"),
"W18", "mt8127",
MTK_EINT_FUNCTION(0, 52),
MTK_FUNCTION(0, "GPIO41"),
MTK_FUNCTION(1, "JTDI"),
MTK_FUNCTION(2, "CONN_MCU_TDI")
),
- MTK_PIN(
- PINCTRL_PIN(42, "JTDO"),
+ MTK_PIN(PINCTRL_PIN(42, "JTDO"),
"Y18", "mt8127",
MTK_EINT_FUNCTION(0, 53),
MTK_FUNCTION(0, "GPIO42"),
MTK_FUNCTION(1, "JTDO"),
MTK_FUNCTION(2, "CONN_MCU_TDO")
),
- MTK_PIN(
- PINCTRL_PIN(43, "EINT11"),
+ MTK_PIN(PINCTRL_PIN(43, "EINT11"),
"W22", "mt8127",
MTK_EINT_FUNCTION(0, 11),
MTK_FUNCTION(0, "GPIO43"),
@@ -455,8 +411,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "EXT_RXD3"),
MTK_FUNCTION(7, "DBG_MON_B[9]")
),
- MTK_PIN(
- PINCTRL_PIN(44, "EINT12"),
+ MTK_PIN(PINCTRL_PIN(44, "EINT12"),
"V23", "mt8127",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO44"),
@@ -468,8 +423,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "EXT_TXEN"),
MTK_FUNCTION(7, "DBG_MON_B[10]")
),
- MTK_PIN(
- PINCTRL_PIN(45, "EINT13"),
+ MTK_PIN(PINCTRL_PIN(45, "EINT13"),
"Y21", "mt8127",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO45"),
@@ -478,8 +432,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "SPDIF"),
MTK_FUNCTION(7, "DBG_MON_B[11]")
),
- MTK_PIN(
- PINCTRL_PIN(46, "EINT14"),
+ MTK_PIN(PINCTRL_PIN(46, "EINT14"),
"F23", "mt8127",
MTK_EINT_FUNCTION(0, 14),
MTK_FUNCTION(0, "GPIO46"),
@@ -489,8 +442,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "NCLE"),
MTK_FUNCTION(7, "DBG_MON_A[14]")
),
- MTK_PIN(
- PINCTRL_PIN(47, "EINT15"),
+ MTK_PIN(PINCTRL_PIN(47, "EINT15"),
"G23", "mt8127",
MTK_EINT_FUNCTION(0, 15),
MTK_FUNCTION(0, "GPIO47"),
@@ -500,8 +452,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "NCEB1"),
MTK_FUNCTION(7, "DBG_MON_A[15]")
),
- MTK_PIN(
- PINCTRL_PIN(48, "EINT16"),
+ MTK_PIN(PINCTRL_PIN(48, "EINT16"),
"H23", "mt8127",
MTK_EINT_FUNCTION(0, 16),
MTK_FUNCTION(0, "GPIO48"),
@@ -511,8 +462,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "NCEB0"),
MTK_FUNCTION(7, "DBG_MON_A[16]")
),
- MTK_PIN(
- PINCTRL_PIN(49, "EINT17"),
+ MTK_PIN(PINCTRL_PIN(49, "EINT17"),
"J22", "mt8127",
MTK_EINT_FUNCTION(0, 17),
MTK_FUNCTION(0, "GPIO49"),
@@ -523,8 +473,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "NREB"),
MTK_FUNCTION(7, "DBG_MON_A[17]")
),
- MTK_PIN(
- PINCTRL_PIN(50, "EINT18"),
+ MTK_PIN(PINCTRL_PIN(50, "EINT18"),
"AD20", "mt8127",
MTK_EINT_FUNCTION(0, 18),
MTK_FUNCTION(0, "GPIO50"),
@@ -536,8 +485,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "ADC_CK"),
MTK_FUNCTION(7, "DBG_MON_B[12]")
),
- MTK_PIN(
- PINCTRL_PIN(51, "EINT19"),
+ MTK_PIN(PINCTRL_PIN(51, "EINT19"),
"AC21", "mt8127",
MTK_EINT_FUNCTION(0, 19),
MTK_FUNCTION(0, "GPIO51"),
@@ -548,8 +496,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "ADC_DAT_IN"),
MTK_FUNCTION(7, "DBG_MON_B[13]")
),
- MTK_PIN(
- PINCTRL_PIN(52, "EINT20"),
+ MTK_PIN(PINCTRL_PIN(52, "EINT20"),
"V20", "mt8127",
MTK_EINT_FUNCTION(0, 20),
MTK_FUNCTION(0, "GPIO52"),
@@ -561,8 +508,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "ADC_WS"),
MTK_FUNCTION(7, "DBG_MON_B[14]")
),
- MTK_PIN(
- PINCTRL_PIN(53, "SPI_CS"),
+ MTK_PIN(PINCTRL_PIN(53, "SPI_CS"),
"AD19", "mt8127",
MTK_EINT_FUNCTION(0, 54),
MTK_FUNCTION(0, "GPIO53"),
@@ -571,8 +517,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(4, "ADC_CK"),
MTK_FUNCTION(7, "DBG_MON_B[15]")
),
- MTK_PIN(
- PINCTRL_PIN(54, "SPI_CK"),
+ MTK_PIN(PINCTRL_PIN(54, "SPI_CK"),
"AC18", "mt8127",
MTK_EINT_FUNCTION(0, 55),
MTK_FUNCTION(0, "GPIO54"),
@@ -581,8 +526,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(4, "ADC_DAT_IN"),
MTK_FUNCTION(7, "DBG_MON_B[16]")
),
- MTK_PIN(
- PINCTRL_PIN(55, "SPI_MI"),
+ MTK_PIN(PINCTRL_PIN(55, "SPI_MI"),
"AC19", "mt8127",
MTK_EINT_FUNCTION(0, 56),
MTK_FUNCTION(0, "GPIO55"),
@@ -592,8 +536,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(4, "ADC_WS"),
MTK_FUNCTION(7, "DBG_MON_B[17]")
),
- MTK_PIN(
- PINCTRL_PIN(56, "SPI_MO"),
+ MTK_PIN(PINCTRL_PIN(56, "SPI_MO"),
"AD18", "mt8127",
MTK_EINT_FUNCTION(0, 57),
MTK_FUNCTION(0, "GPIO56"),
@@ -601,22 +544,19 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(2, "SPI_MI"),
MTK_FUNCTION(7, "DBG_MON_B[18]")
),
- MTK_PIN(
- PINCTRL_PIN(57, "SDA1"),
+ MTK_PIN(PINCTRL_PIN(57, "SDA1"),
"AE23", "mt8127",
MTK_EINT_FUNCTION(0, 58),
MTK_FUNCTION(0, "GPIO57"),
MTK_FUNCTION(1, "SDA1")
),
- MTK_PIN(
- PINCTRL_PIN(58, "SCL1"),
+ MTK_PIN(PINCTRL_PIN(58, "SCL1"),
"AD23", "mt8127",
MTK_EINT_FUNCTION(0, 59),
MTK_FUNCTION(0, "GPIO58"),
MTK_FUNCTION(1, "SCL1")
),
- MTK_PIN(
- PINCTRL_PIN(59, "DISP_PWM"),
+ MTK_PIN(PINCTRL_PIN(59, "DISP_PWM"),
"AC20", "mt8127",
MTK_EINT_FUNCTION(0, 60),
MTK_FUNCTION(0, "GPIO59"),
@@ -624,56 +564,49 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(2, "PWM1"),
MTK_FUNCTION(7, "DBG_MON_A[18]")
),
- MTK_PIN(
- PINCTRL_PIN(60, "WB_RSTB"),
+ MTK_PIN(PINCTRL_PIN(60, "WB_RSTB"),
"AD7", "mt8127",
MTK_EINT_FUNCTION(0, 61),
MTK_FUNCTION(0, "GPIO60"),
MTK_FUNCTION(1, "WB_RSTB"),
MTK_FUNCTION(7, "DBG_MON_A[19]")
),
- MTK_PIN(
- PINCTRL_PIN(61, "F2W_DATA"),
+ MTK_PIN(PINCTRL_PIN(61, "F2W_DATA"),
"Y10", "mt8127",
MTK_EINT_FUNCTION(0, 62),
MTK_FUNCTION(0, "GPIO61"),
MTK_FUNCTION(1, "F2W_DATA"),
MTK_FUNCTION(7, "DBG_MON_A[20]")
),
- MTK_PIN(
- PINCTRL_PIN(62, "F2W_CLK"),
+ MTK_PIN(PINCTRL_PIN(62, "F2W_CLK"),
"W10", "mt8127",
MTK_EINT_FUNCTION(0, 63),
MTK_FUNCTION(0, "GPIO62"),
MTK_FUNCTION(1, "F2W_CK"),
MTK_FUNCTION(7, "DBG_MON_A[21]")
),
- MTK_PIN(
- PINCTRL_PIN(63, "WB_SCLK"),
+ MTK_PIN(PINCTRL_PIN(63, "WB_SCLK"),
"AB7", "mt8127",
MTK_EINT_FUNCTION(0, 64),
MTK_FUNCTION(0, "GPIO63"),
MTK_FUNCTION(1, "WB_SCLK"),
MTK_FUNCTION(7, "DBG_MON_A[22]")
),
- MTK_PIN(
- PINCTRL_PIN(64, "WB_SDATA"),
+ MTK_PIN(PINCTRL_PIN(64, "WB_SDATA"),
"AA7", "mt8127",
MTK_EINT_FUNCTION(0, 65),
MTK_FUNCTION(0, "GPIO64"),
MTK_FUNCTION(1, "WB_SDATA"),
MTK_FUNCTION(7, "DBG_MON_A[23]")
),
- MTK_PIN(
- PINCTRL_PIN(65, "WB_SEN"),
+ MTK_PIN(PINCTRL_PIN(65, "WB_SEN"),
"Y7", "mt8127",
MTK_EINT_FUNCTION(0, 66),
MTK_FUNCTION(0, "GPIO65"),
MTK_FUNCTION(1, "WB_SEN"),
MTK_FUNCTION(7, "DBG_MON_A[24]")
),
- MTK_PIN(
- PINCTRL_PIN(66, "WB_CRTL0"),
+ MTK_PIN(PINCTRL_PIN(66, "WB_CRTL0"),
"AA1", "mt8127",
MTK_EINT_FUNCTION(0, 67),
MTK_FUNCTION(0, "GPIO66"),
@@ -681,8 +614,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(2, "DFD_NTRST_XI"),
MTK_FUNCTION(7, "DBG_MON_A[25]")
),
- MTK_PIN(
- PINCTRL_PIN(67, "WB_CRTL1"),
+ MTK_PIN(PINCTRL_PIN(67, "WB_CRTL1"),
"AA2", "mt8127",
MTK_EINT_FUNCTION(0, 68),
MTK_FUNCTION(0, "GPIO67"),
@@ -690,8 +622,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(2, "DFD_TMS_XI"),
MTK_FUNCTION(7, "DBG_MON_A[26]")
),
- MTK_PIN(
- PINCTRL_PIN(68, "WB_CRTL2"),
+ MTK_PIN(PINCTRL_PIN(68, "WB_CRTL2"),
"Y1", "mt8127",
MTK_EINT_FUNCTION(0, 69),
MTK_FUNCTION(0, "GPIO68"),
@@ -699,8 +630,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(2, "DFD_TCK_XI"),
MTK_FUNCTION(7, "DBG_MON_A[27]")
),
- MTK_PIN(
- PINCTRL_PIN(69, "WB_CRTL3"),
+ MTK_PIN(PINCTRL_PIN(69, "WB_CRTL3"),
"Y2", "mt8127",
MTK_EINT_FUNCTION(0, 70),
MTK_FUNCTION(0, "GPIO69"),
@@ -708,8 +638,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(2, "DFD_TDI_XI"),
MTK_FUNCTION(7, "DBG_MON_A[28]")
),
- MTK_PIN(
- PINCTRL_PIN(70, "WB_CRTL4"),
+ MTK_PIN(PINCTRL_PIN(70, "WB_CRTL4"),
"Y3", "mt8127",
MTK_EINT_FUNCTION(0, 71),
MTK_FUNCTION(0, "GPIO70"),
@@ -717,16 +646,14 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(2, "DFD_TDO"),
MTK_FUNCTION(7, "DBG_MON_A[29]")
),
- MTK_PIN(
- PINCTRL_PIN(71, "WB_CRTL5"),
+ MTK_PIN(PINCTRL_PIN(71, "WB_CRTL5"),
"Y4", "mt8127",
MTK_EINT_FUNCTION(0, 72),
MTK_FUNCTION(0, "GPIO71"),
MTK_FUNCTION(1, "WB_CRTL5"),
MTK_FUNCTION(7, "DBG_MON_A[30]")
),
- MTK_PIN(
- PINCTRL_PIN(72, "I2S_DATA_IN"),
+ MTK_PIN(PINCTRL_PIN(72, "I2S_DATA_IN"),
"K21", "mt8127",
MTK_EINT_FUNCTION(0, 73),
MTK_FUNCTION(0, "GPIO72"),
@@ -738,8 +665,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "ADC_CK"),
MTK_FUNCTION(7, "DBG_MON_B[19]")
),
- MTK_PIN(
- PINCTRL_PIN(73, "I2S_LRCK"),
+ MTK_PIN(PINCTRL_PIN(73, "I2S_LRCK"),
"L21", "mt8127",
MTK_EINT_FUNCTION(0, 74),
MTK_FUNCTION(0, "GPIO73"),
@@ -751,8 +677,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "ADC_DAT_IN"),
MTK_FUNCTION(7, "DBG_MON_B[20]")
),
- MTK_PIN(
- PINCTRL_PIN(74, "I2S_BCK"),
+ MTK_PIN(PINCTRL_PIN(74, "I2S_BCK"),
"L20", "mt8127",
MTK_EINT_FUNCTION(0, 75),
MTK_FUNCTION(0, "GPIO74"),
@@ -764,70 +689,61 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "ADC_WS"),
MTK_FUNCTION(7, "DBG_MON_B[21]")
),
- MTK_PIN(
- PINCTRL_PIN(75, "SDA0"),
+ MTK_PIN(PINCTRL_PIN(75, "SDA0"),
"W3", "mt8127",
MTK_EINT_FUNCTION(0, 76),
MTK_FUNCTION(0, "GPIO75"),
MTK_FUNCTION(1, "SDA0")
),
- MTK_PIN(
- PINCTRL_PIN(76, "SCL0"),
+ MTK_PIN(PINCTRL_PIN(76, "SCL0"),
"W4", "mt8127",
MTK_EINT_FUNCTION(0, 77),
MTK_FUNCTION(0, "GPIO76"),
MTK_FUNCTION(1, "SCL0")
),
- MTK_PIN(
- PINCTRL_PIN(77, "SDA2"),
+ MTK_PIN(PINCTRL_PIN(77, "SDA2"),
"K19", "mt8127",
MTK_EINT_FUNCTION(0, 78),
MTK_FUNCTION(0, "GPIO77"),
MTK_FUNCTION(1, "SDA2"),
MTK_FUNCTION(2, "PWM1")
),
- MTK_PIN(
- PINCTRL_PIN(78, "SCL2"),
+ MTK_PIN(PINCTRL_PIN(78, "SCL2"),
"K20", "mt8127",
MTK_EINT_FUNCTION(0, 79),
MTK_FUNCTION(0, "GPIO78"),
MTK_FUNCTION(1, "SCL2"),
MTK_FUNCTION(2, "PWM2")
),
- MTK_PIN(
- PINCTRL_PIN(79, "URXD0"),
+ MTK_PIN(PINCTRL_PIN(79, "URXD0"),
"K18", "mt8127",
MTK_EINT_FUNCTION(0, 80),
MTK_FUNCTION(0, "GPIO79"),
MTK_FUNCTION(1, "URXD0"),
MTK_FUNCTION(2, "UTXD0")
),
- MTK_PIN(
- PINCTRL_PIN(80, "UTXD0"),
+ MTK_PIN(PINCTRL_PIN(80, "UTXD0"),
"K17", "mt8127",
MTK_EINT_FUNCTION(0, 81),
MTK_FUNCTION(0, "GPIO80"),
MTK_FUNCTION(1, "UTXD0"),
MTK_FUNCTION(2, "URXD0")
),
- MTK_PIN(
- PINCTRL_PIN(81, "URXD1"),
+ MTK_PIN(PINCTRL_PIN(81, "URXD1"),
"L17", "mt8127",
MTK_EINT_FUNCTION(0, 82),
MTK_FUNCTION(0, "GPIO81"),
MTK_FUNCTION(1, "URXD1"),
MTK_FUNCTION(2, "UTXD1")
),
- MTK_PIN(
- PINCTRL_PIN(82, "UTXD1"),
+ MTK_PIN(PINCTRL_PIN(82, "UTXD1"),
"L18", "mt8127",
MTK_EINT_FUNCTION(0, 83),
MTK_FUNCTION(0, "GPIO82"),
MTK_FUNCTION(1, "UTXD1"),
MTK_FUNCTION(2, "URXD1")
),
- MTK_PIN(
- PINCTRL_PIN(83, "LCM_RST"),
+ MTK_PIN(PINCTRL_PIN(83, "LCM_RST"),
"W5", "mt8127",
MTK_EINT_FUNCTION(0, 84),
MTK_FUNCTION(0, "GPIO83"),
@@ -835,16 +751,14 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(2, "VDAC_CK_XI"),
MTK_FUNCTION(7, "DBG_MON_A[31]")
),
- MTK_PIN(
- PINCTRL_PIN(84, "DSI_TE"),
+ MTK_PIN(PINCTRL_PIN(84, "DSI_TE"),
"W6", "mt8127",
MTK_EINT_FUNCTION(0, 85),
MTK_FUNCTION(0, "GPIO84"),
MTK_FUNCTION(1, "DSI_TE"),
MTK_FUNCTION(7, "DBG_MON_A[32]")
),
- MTK_PIN(
- PINCTRL_PIN(85, "MSDC2_CMD"),
+ MTK_PIN(PINCTRL_PIN(85, "MSDC2_CMD"),
"U7", "mt8127",
MTK_EINT_FUNCTION(0, 86),
MTK_FUNCTION(0, "GPIO85"),
@@ -854,8 +768,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "I2SOUT_BCK"),
MTK_FUNCTION(7, "DBG_MON_B[22]")
),
- MTK_PIN(
- PINCTRL_PIN(86, "MSDC2_CLK"),
+ MTK_PIN(PINCTRL_PIN(86, "MSDC2_CLK"),
"T8", "mt8127",
MTK_EINT_FUNCTION(0, 87),
MTK_FUNCTION(0, "GPIO86"),
@@ -865,8 +778,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "I2SOUT_LRCK"),
MTK_FUNCTION(7, "DBG_MON_B[23]")
),
- MTK_PIN(
- PINCTRL_PIN(87, "MSDC2_DAT0"),
+ MTK_PIN(PINCTRL_PIN(87, "MSDC2_DAT0"),
"V3", "mt8127",
MTK_EINT_FUNCTION(0, 88),
MTK_FUNCTION(0, "GPIO87"),
@@ -876,8 +788,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "I2SOUT_DATA_OUT"),
MTK_FUNCTION(7, "DBG_MON_B[24]")
),
- MTK_PIN(
- PINCTRL_PIN(88, "MSDC2_DAT1"),
+ MTK_PIN(PINCTRL_PIN(88, "MSDC2_DAT1"),
"V4", "mt8127",
MTK_EINT_FUNCTION(0, 89),
MTK_FUNCTION(0, "GPIO88"),
@@ -888,8 +799,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "PWM1"),
MTK_FUNCTION(7, "DBG_MON_B[25]")
),
- MTK_PIN(
- PINCTRL_PIN(89, "MSDC2_DAT2"),
+ MTK_PIN(PINCTRL_PIN(89, "MSDC2_DAT2"),
"U5", "mt8127",
MTK_EINT_FUNCTION(0, 90),
MTK_FUNCTION(0, "GPIO89"),
@@ -900,8 +810,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "PWM2"),
MTK_FUNCTION(7, "DBG_MON_B[26]")
),
- MTK_PIN(
- PINCTRL_PIN(90, "MSDC2_DAT3"),
+ MTK_PIN(PINCTRL_PIN(90, "MSDC2_DAT3"),
"U6", "mt8127",
MTK_EINT_FUNCTION(0, 91),
MTK_FUNCTION(0, "GPIO90"),
@@ -913,168 +822,145 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(6, "PWM3"),
MTK_FUNCTION(7, "DBG_MON_B[27]")
),
- MTK_PIN(
- PINCTRL_PIN(91, "TDN3"),
+ MTK_PIN(PINCTRL_PIN(91, "TDN3"),
"U2", "mt8127",
MTK_EINT_FUNCTION(0, 92),
MTK_FUNCTION(0, "GPI91"),
MTK_FUNCTION(1, "TDN3")
),
- MTK_PIN(
- PINCTRL_PIN(92, "TDP3"),
+ MTK_PIN(PINCTRL_PIN(92, "TDP3"),
"U1", "mt8127",
MTK_EINT_FUNCTION(0, 93),
MTK_FUNCTION(0, "GPI92"),
MTK_FUNCTION(1, "TDP3")
),
- MTK_PIN(
- PINCTRL_PIN(93, "TDN2"),
+ MTK_PIN(PINCTRL_PIN(93, "TDN2"),
"T2", "mt8127",
MTK_EINT_FUNCTION(0, 94),
MTK_FUNCTION(0, "GPI93"),
MTK_FUNCTION(1, "TDN2")
),
- MTK_PIN(
- PINCTRL_PIN(94, "TDP2"),
+ MTK_PIN(PINCTRL_PIN(94, "TDP2"),
"T1", "mt8127",
MTK_EINT_FUNCTION(0, 95),
MTK_FUNCTION(0, "GPI94"),
MTK_FUNCTION(1, "TDP2")
),
- MTK_PIN(
- PINCTRL_PIN(95, "TCN"),
+ MTK_PIN(PINCTRL_PIN(95, "TCN"),
"R5", "mt8127",
MTK_EINT_FUNCTION(0, 96),
MTK_FUNCTION(0, "GPI95"),
MTK_FUNCTION(1, "TCN")
),
- MTK_PIN(
- PINCTRL_PIN(96, "TCP"),
+ MTK_PIN(PINCTRL_PIN(96, "TCP"),
"R4", "mt8127",
MTK_EINT_FUNCTION(0, 97),
MTK_FUNCTION(0, "GPI96"),
MTK_FUNCTION(1, "TCP")
),
- MTK_PIN(
- PINCTRL_PIN(97, "TDN1"),
+ MTK_PIN(PINCTRL_PIN(97, "TDN1"),
"R3", "mt8127",
MTK_EINT_FUNCTION(0, 98),
MTK_FUNCTION(0, "GPI97"),
MTK_FUNCTION(1, "TDN1")
),
- MTK_PIN(
- PINCTRL_PIN(98, "TDP1"),
+ MTK_PIN(PINCTRL_PIN(98, "TDP1"),
"R2", "mt8127",
MTK_EINT_FUNCTION(0, 99),
MTK_FUNCTION(0, "GPI98"),
MTK_FUNCTION(1, "TDP1")
),
- MTK_PIN(
- PINCTRL_PIN(99, "TDN0"),
+ MTK_PIN(PINCTRL_PIN(99, "TDN0"),
"P3", "mt8127",
MTK_EINT_FUNCTION(0, 100),
MTK_FUNCTION(0, "GPI99"),
MTK_FUNCTION(1, "TDN0")
),
- MTK_PIN(
- PINCTRL_PIN(100, "TDP0"),
+ MTK_PIN(PINCTRL_PIN(100, "TDP0"),
"P2", "mt8127",
MTK_EINT_FUNCTION(0, 101),
MTK_FUNCTION(0, "GPI100"),
MTK_FUNCTION(1, "TDP0")
),
- MTK_PIN(
- PINCTRL_PIN(101, "RDN0"),
+ MTK_PIN(PINCTRL_PIN(101, "RDN0"),
"K1", "mt8127",
MTK_EINT_FUNCTION(0, 102),
MTK_FUNCTION(0, "GPI101"),
MTK_FUNCTION(1, "RDN0")
),
- MTK_PIN(
- PINCTRL_PIN(102, "RDP0"),
+ MTK_PIN(PINCTRL_PIN(102, "RDP0"),
"K2", "mt8127",
MTK_EINT_FUNCTION(0, 103),
MTK_FUNCTION(0, "GPI102"),
MTK_FUNCTION(1, "RDP0")
),
- MTK_PIN(
- PINCTRL_PIN(103, "RDN1"),
+ MTK_PIN(PINCTRL_PIN(103, "RDN1"),
"L2", "mt8127",
MTK_EINT_FUNCTION(0, 104),
MTK_FUNCTION(0, "GPI103"),
MTK_FUNCTION(1, "RDN1")
),
- MTK_PIN(
- PINCTRL_PIN(104, "RDP1"),
+ MTK_PIN(PINCTRL_PIN(104, "RDP1"),
"L3", "mt8127",
MTK_EINT_FUNCTION(0, 105),
MTK_FUNCTION(0, "GPI104"),
MTK_FUNCTION(1, "RDP1")
),
- MTK_PIN(
- PINCTRL_PIN(105, "RCN"),
+ MTK_PIN(PINCTRL_PIN(105, "RCN"),
"M4", "mt8127",
MTK_EINT_FUNCTION(0, 106),
MTK_FUNCTION(0, "GPI105"),
MTK_FUNCTION(1, "RCN")
),
- MTK_PIN(
- PINCTRL_PIN(106, "RCP"),
+ MTK_PIN(PINCTRL_PIN(106, "RCP"),
"M5", "mt8127",
MTK_EINT_FUNCTION(0, 107),
MTK_FUNCTION(0, "GPI106"),
MTK_FUNCTION(1, "RCP")
),
- MTK_PIN(
- PINCTRL_PIN(107, "RDN2"),
+ MTK_PIN(PINCTRL_PIN(107, "RDN2"),
"M2", "mt8127",
MTK_EINT_FUNCTION(0, 108),
MTK_FUNCTION(0, "GPI107"),
MTK_FUNCTION(1, "RDN2"),
MTK_FUNCTION(2, "CMDAT8")
),
- MTK_PIN(
- PINCTRL_PIN(108, "RDP2"),
+ MTK_PIN(PINCTRL_PIN(108, "RDP2"),
"M3", "mt8127",
MTK_EINT_FUNCTION(0, 109),
MTK_FUNCTION(0, "GPI108"),
MTK_FUNCTION(1, "RDP2"),
MTK_FUNCTION(2, "CMDAT9")
),
- MTK_PIN(
- PINCTRL_PIN(109, "RDN3"),
+ MTK_PIN(PINCTRL_PIN(109, "RDN3"),
"N2", "mt8127",
MTK_EINT_FUNCTION(0, 110),
MTK_FUNCTION(0, "GPI109"),
MTK_FUNCTION(1, "RDN3"),
MTK_FUNCTION(2, "CMDAT4")
),
- MTK_PIN(
- PINCTRL_PIN(110, "RDP3"),
+ MTK_PIN(PINCTRL_PIN(110, "RDP3"),
"N3", "mt8127",
MTK_EINT_FUNCTION(0, 111),
MTK_FUNCTION(0, "GPI110"),
MTK_FUNCTION(1, "RDP3"),
MTK_FUNCTION(2, "CMDAT5")
),
- MTK_PIN(
- PINCTRL_PIN(111, "RCN_A"),
+ MTK_PIN(PINCTRL_PIN(111, "RCN_A"),
"J5", "mt8127",
MTK_EINT_FUNCTION(0, 112),
MTK_FUNCTION(0, "GPI111"),
MTK_FUNCTION(1, "RCN_A"),
MTK_FUNCTION(2, "CMDAT6")
),
- MTK_PIN(
- PINCTRL_PIN(112, "RCP_A"),
+ MTK_PIN(PINCTRL_PIN(112, "RCP_A"),
"J4", "mt8127",
MTK_EINT_FUNCTION(0, 113),
MTK_FUNCTION(0, "GPI112"),
MTK_FUNCTION(1, "RCP_A"),
MTK_FUNCTION(2, "CMDAT7")
),
- MTK_PIN(
- PINCTRL_PIN(113, "RDN1_A"),
+ MTK_PIN(PINCTRL_PIN(113, "RDN1_A"),
"J2", "mt8127",
MTK_EINT_FUNCTION(0, 114),
MTK_FUNCTION(0, "GPI113"),
@@ -1082,8 +968,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(2, "CMDAT2"),
MTK_FUNCTION(3, "CMCSD2")
),
- MTK_PIN(
- PINCTRL_PIN(114, "RDP1_A"),
+ MTK_PIN(PINCTRL_PIN(114, "RDP1_A"),
"J3", "mt8127",
MTK_EINT_FUNCTION(0, 115),
MTK_FUNCTION(0, "GPI114"),
@@ -1091,24 +976,21 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(2, "CMDAT3"),
MTK_FUNCTION(3, "CMCSD3")
),
- MTK_PIN(
- PINCTRL_PIN(115, "RDN0_A"),
+ MTK_PIN(PINCTRL_PIN(115, "RDN0_A"),
"H2", "mt8127",
MTK_EINT_FUNCTION(0, 116),
MTK_FUNCTION(0, "GPI115"),
MTK_FUNCTION(1, "RDN0_A"),
MTK_FUNCTION(2, "CMHSYNC")
),
- MTK_PIN(
- PINCTRL_PIN(116, "RDP0_A"),
+ MTK_PIN(PINCTRL_PIN(116, "RDP0_A"),
"H3", "mt8127",
MTK_EINT_FUNCTION(0, 117),
MTK_FUNCTION(0, "GPI116"),
MTK_FUNCTION(1, "RDP0_A"),
MTK_FUNCTION(2, "CMVSYNC")
),
- MTK_PIN(
- PINCTRL_PIN(117, "CMDAT0"),
+ MTK_PIN(PINCTRL_PIN(117, "CMDAT0"),
"G5", "mt8127",
MTK_EINT_FUNCTION(0, 118),
MTK_FUNCTION(0, "GPIO117"),
@@ -1117,8 +999,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(3, "ANT_SEL2"),
MTK_FUNCTION(7, "DBG_MON_B[28]")
),
- MTK_PIN(
- PINCTRL_PIN(118, "CMDAT1"),
+ MTK_PIN(PINCTRL_PIN(118, "CMDAT1"),
"G4", "mt8127",
MTK_EINT_FUNCTION(0, 119),
MTK_FUNCTION(0, "GPIO118"),
@@ -1127,8 +1008,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(3, "ANT_SEL3"),
MTK_FUNCTION(7, "DBG_MON_B[29]")
),
- MTK_PIN(
- PINCTRL_PIN(119, "CMMCLK"),
+ MTK_PIN(PINCTRL_PIN(119, "CMMCLK"),
"F3", "mt8127",
MTK_EINT_FUNCTION(0, 120),
MTK_FUNCTION(0, "GPIO119"),
@@ -1136,8 +1016,7 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(3, "ANT_SEL4"),
MTK_FUNCTION(7, "DBG_MON_B[30]")
),
- MTK_PIN(
- PINCTRL_PIN(120, "CMPCLK"),
+ MTK_PIN(PINCTRL_PIN(120, "CMPCLK"),
"G6", "mt8127",
MTK_EINT_FUNCTION(0, 121),
MTK_FUNCTION(0, "GPIO120"),
@@ -1146,130 +1025,113 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(3, "ANT_SEL5"),
MTK_FUNCTION(7, "DBG_MON_B[31]")
),
- MTK_PIN(
- PINCTRL_PIN(121, "MSDC1_CMD"),
+ MTK_PIN(PINCTRL_PIN(121, "MSDC1_CMD"),
"E3", "mt8127",
MTK_EINT_FUNCTION(0, 122),
MTK_FUNCTION(0, "GPIO121"),
MTK_FUNCTION(1, "MSDC1_CMD")
),
- MTK_PIN(
- PINCTRL_PIN(122, "MSDC1_CLK"),
+ MTK_PIN(PINCTRL_PIN(122, "MSDC1_CLK"),
"D1", "mt8127",
MTK_EINT_FUNCTION(0, 123),
MTK_FUNCTION(0, "GPIO122"),
MTK_FUNCTION(1, "MSDC1_CLK")
),
- MTK_PIN(
- PINCTRL_PIN(123, "MSDC1_DAT0"),
+ MTK_PIN(PINCTRL_PIN(123, "MSDC1_DAT0"),
"D2", "mt8127",
MTK_EINT_FUNCTION(0, 124),
MTK_FUNCTION(0, "GPIO123"),
MTK_FUNCTION(1, "MSDC1_DAT0")
),
- MTK_PIN(
- PINCTRL_PIN(124, "MSDC1_DAT1"),
+ MTK_PIN(PINCTRL_PIN(124, "MSDC1_DAT1"),
"D3", "mt8127",
MTK_EINT_FUNCTION(0, 125),
MTK_FUNCTION(0, "GPIO124"),
MTK_FUNCTION(1, "MSDC1_DAT1")
),
- MTK_PIN(
- PINCTRL_PIN(125, "MSDC1_DAT2"),
+ MTK_PIN(PINCTRL_PIN(125, "MSDC1_DAT2"),
"F2", "mt8127",
MTK_EINT_FUNCTION(0, 126),
MTK_FUNCTION(0, "GPIO125"),
MTK_FUNCTION(1, "MSDC1_DAT2")
),
- MTK_PIN(
- PINCTRL_PIN(126, "MSDC1_DAT3"),
+ MTK_PIN(PINCTRL_PIN(126, "MSDC1_DAT3"),
"E2", "mt8127",
MTK_EINT_FUNCTION(0, 127),
MTK_FUNCTION(0, "GPIO126"),
MTK_FUNCTION(1, "MSDC1_DAT3")
),
- MTK_PIN(
- PINCTRL_PIN(127, "MSDC0_DAT7"),
+ MTK_PIN(PINCTRL_PIN(127, "MSDC0_DAT7"),
"C23", "mt8127",
MTK_EINT_FUNCTION(0, 128),
MTK_FUNCTION(0, "GPIO127"),
MTK_FUNCTION(1, "MSDC0_DAT7"),
MTK_FUNCTION(4, "NLD7")
),
- MTK_PIN(
- PINCTRL_PIN(128, "MSDC0_DAT6"),
+ MTK_PIN(PINCTRL_PIN(128, "MSDC0_DAT6"),
"C24", "mt8127",
MTK_EINT_FUNCTION(0, 129),
MTK_FUNCTION(0, "GPIO128"),
MTK_FUNCTION(1, "MSDC0_DAT6"),
MTK_FUNCTION(4, "NLD6")
),
- MTK_PIN(
- PINCTRL_PIN(129, "MSDC0_DAT5"),
+ MTK_PIN(PINCTRL_PIN(129, "MSDC0_DAT5"),
"D22", "mt8127",
MTK_EINT_FUNCTION(0, 130),
MTK_FUNCTION(0, "GPIO129"),
MTK_FUNCTION(1, "MSDC0_DAT5"),
MTK_FUNCTION(4, "NLD4")
),
- MTK_PIN(
- PINCTRL_PIN(130, "MSDC0_DAT4"),
+ MTK_PIN(PINCTRL_PIN(130, "MSDC0_DAT4"),
"D24", "mt8127",
MTK_EINT_FUNCTION(0, 131),
MTK_FUNCTION(0, "GPIO130"),
MTK_FUNCTION(1, "MSDC0_DAT4"),
MTK_FUNCTION(4, "NLD3")
),
- MTK_PIN(
- PINCTRL_PIN(131, "MSDC0_RSTB"),
+ MTK_PIN(PINCTRL_PIN(131, "MSDC0_RSTB"),
"F24", "mt8127",
MTK_EINT_FUNCTION(0, 132),
MTK_FUNCTION(0, "GPIO131"),
MTK_FUNCTION(1, "MSDC0_RSTB"),
MTK_FUNCTION(4, "NLD0")
),
- MTK_PIN(
- PINCTRL_PIN(132, "MSDC0_CMD"),
+ MTK_PIN(PINCTRL_PIN(132, "MSDC0_CMD"),
"G20", "mt8127",
MTK_EINT_FUNCTION(0, 133),
MTK_FUNCTION(0, "GPIO132"),
MTK_FUNCTION(1, "MSDC0_CMD"),
MTK_FUNCTION(4, "NALE")
),
- MTK_PIN(
- PINCTRL_PIN(133, "MSDC0_CLK"),
+ MTK_PIN(PINCTRL_PIN(133, "MSDC0_CLK"),
"G21", "mt8127",
MTK_EINT_FUNCTION(0, 134),
MTK_FUNCTION(0, "GPIO133"),
MTK_FUNCTION(1, "MSDC0_CLK"),
MTK_FUNCTION(4, "NWEB")
),
- MTK_PIN(
- PINCTRL_PIN(134, "MSDC0_DAT3"),
+ MTK_PIN(PINCTRL_PIN(134, "MSDC0_DAT3"),
"D23", "mt8127",
MTK_EINT_FUNCTION(0, 135),
MTK_FUNCTION(0, "GPIO134"),
MTK_FUNCTION(1, "MSDC0_DAT3"),
MTK_FUNCTION(4, "NLD1")
),
- MTK_PIN(
- PINCTRL_PIN(135, "MSDC0_DAT2"),
+ MTK_PIN(PINCTRL_PIN(135, "MSDC0_DAT2"),
"E22", "mt8127",
MTK_EINT_FUNCTION(0, 136),
MTK_FUNCTION(0, "GPIO135"),
MTK_FUNCTION(1, "MSDC0_DAT2"),
MTK_FUNCTION(4, "NLD5")
),
- MTK_PIN(
- PINCTRL_PIN(136, "MSDC0_DAT1"),
+ MTK_PIN(PINCTRL_PIN(136, "MSDC0_DAT1"),
"E23", "mt8127",
MTK_EINT_FUNCTION(0, 137),
MTK_FUNCTION(0, "GPIO136"),
MTK_FUNCTION(1, "MSDC0_DAT1"),
MTK_FUNCTION(4, "NLD8")
),
- MTK_PIN(
- PINCTRL_PIN(137, "MSDC0_DAT0"),
+ MTK_PIN(PINCTRL_PIN(137, "MSDC0_DAT0"),
"F22", "mt8127",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO137"),
@@ -1277,36 +1139,31 @@ static const struct mtk_desc_pin mtk_pins_mt8127[] = {
MTK_FUNCTION(4, "WATCHDOG"),
MTK_FUNCTION(5, "NLD2")
),
- MTK_PIN(
- PINCTRL_PIN(138, "CEC"),
+ MTK_PIN(PINCTRL_PIN(138, "CEC"),
"AE21", "mt8127",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO138"),
MTK_FUNCTION(1, "CEC")
),
- MTK_PIN(
- PINCTRL_PIN(139, "HTPLG"),
+ MTK_PIN(PINCTRL_PIN(139, "HTPLG"),
"AD21", "mt8127",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO139"),
MTK_FUNCTION(1, "HTPLG")
),
- MTK_PIN(
- PINCTRL_PIN(140, "HDMISCK"),
+ MTK_PIN(PINCTRL_PIN(140, "HDMISCK"),
"AE22", "mt8127",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO140"),
MTK_FUNCTION(1, "HDMISCK")
),
- MTK_PIN(
- PINCTRL_PIN(141, "HDMISD"),
+ MTK_PIN(PINCTRL_PIN(141, "HDMISD"),
"AD22", "mt8127",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO141"),
MTK_FUNCTION(1, "HDMISD")
),
- MTK_PIN(
- PINCTRL_PIN(142, "EINT21"),
+ MTK_PIN(PINCTRL_PIN(142, "EINT21"),
"J23", "mt8127",
MTK_EINT_FUNCTION(0, 21),
MTK_FUNCTION(0, "GPIO142"),
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h
index e17aedb73c8d..b2b390da6597 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h
@@ -19,8 +19,7 @@
#include "pinctrl-mtk-common.h"
static const struct mtk_desc_pin mtk_pins_mt8135[] = {
- MTK_PIN(
- PINCTRL_PIN(0, "MSDC0_DAT7"),
+ MTK_PIN(PINCTRL_PIN(0, "MSDC0_DAT7"),
"D21", "mt8135",
MTK_EINT_FUNCTION(2, 49),
MTK_FUNCTION(0, "GPIO0"),
@@ -32,8 +31,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "SPI1_MO"),
MTK_FUNCTION(7, "NALE")
),
- MTK_PIN(
- PINCTRL_PIN(1, "MSDC0_DAT6"),
+ MTK_PIN(PINCTRL_PIN(1, "MSDC0_DAT6"),
"D22", "mt8135",
MTK_EINT_FUNCTION(2, 48),
MTK_FUNCTION(0, "GPIO1"),
@@ -45,8 +43,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "SPI1_CSN"),
MTK_FUNCTION(7, "NCLE")
),
- MTK_PIN(
- PINCTRL_PIN(2, "MSDC0_DAT5"),
+ MTK_PIN(PINCTRL_PIN(2, "MSDC0_DAT5"),
"E22", "mt8135",
MTK_EINT_FUNCTION(2, 47),
MTK_FUNCTION(0, "GPIO2"),
@@ -58,8 +55,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "SPI1_CLK"),
MTK_FUNCTION(7, "NLD4")
),
- MTK_PIN(
- PINCTRL_PIN(3, "MSDC0_DAT4"),
+ MTK_PIN(PINCTRL_PIN(3, "MSDC0_DAT4"),
"F21", "mt8135",
MTK_EINT_FUNCTION(2, 46),
MTK_FUNCTION(0, "GPIO3"),
@@ -69,8 +65,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "LSCE1B_2X"),
MTK_FUNCTION(7, "NLD5")
),
- MTK_PIN(
- PINCTRL_PIN(4, "MSDC0_CMD"),
+ MTK_PIN(PINCTRL_PIN(4, "MSDC0_CMD"),
"F20", "mt8135",
MTK_EINT_FUNCTION(2, 41),
MTK_FUNCTION(0, "GPIO4"),
@@ -81,8 +76,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "LRSTB_2X"),
MTK_FUNCTION(7, "NRNB")
),
- MTK_PIN(
- PINCTRL_PIN(5, "MSDC0_CLK"),
+ MTK_PIN(PINCTRL_PIN(5, "MSDC0_CLK"),
"G18", "mt8135",
MTK_EINT_FUNCTION(2, 40),
MTK_FUNCTION(0, "GPIO5"),
@@ -93,8 +87,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "LPTE"),
MTK_FUNCTION(7, "NREB")
),
- MTK_PIN(
- PINCTRL_PIN(6, "MSDC0_DAT3"),
+ MTK_PIN(PINCTRL_PIN(6, "MSDC0_DAT3"),
"G21", "mt8135",
MTK_EINT_FUNCTION(2, 45),
MTK_FUNCTION(0, "GPIO6"),
@@ -105,8 +98,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "LSCE0B_2X"),
MTK_FUNCTION(7, "NLD7")
),
- MTK_PIN(
- PINCTRL_PIN(7, "MSDC0_DAT2"),
+ MTK_PIN(PINCTRL_PIN(7, "MSDC0_DAT2"),
"E21", "mt8135",
MTK_EINT_FUNCTION(2, 44),
MTK_FUNCTION(0, "GPIO7"),
@@ -117,8 +109,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "LSA0_2X"),
MTK_FUNCTION(7, "NLD14")
),
- MTK_PIN(
- PINCTRL_PIN(8, "MSDC0_DAT1"),
+ MTK_PIN(PINCTRL_PIN(8, "MSDC0_DAT1"),
"E23", "mt8135",
MTK_EINT_FUNCTION(2, 43),
MTK_FUNCTION(0, "GPIO8"),
@@ -128,8 +119,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "LSCK_2X"),
MTK_FUNCTION(7, "NLD11")
),
- MTK_PIN(
- PINCTRL_PIN(9, "MSDC0_DAT0"),
+ MTK_PIN(PINCTRL_PIN(9, "MSDC0_DAT0"),
"F22", "mt8135",
MTK_EINT_FUNCTION(2, 42),
MTK_FUNCTION(0, "GPIO9"),
@@ -138,8 +128,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "USB_TEST_IO[5]"),
MTK_FUNCTION(6, "LSDA_2X")
),
- MTK_PIN(
- PINCTRL_PIN(10, "NCEB0"),
+ MTK_PIN(PINCTRL_PIN(10, "NCEB0"),
"G20", "mt8135",
MTK_EINT_FUNCTION(2, 139),
MTK_FUNCTION(0, "GPIO10"),
@@ -147,8 +136,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(2, "EINT139"),
MTK_FUNCTION(7, "TESTA_OUT4")
),
- MTK_PIN(
- PINCTRL_PIN(11, "NCEB1"),
+ MTK_PIN(PINCTRL_PIN(11, "NCEB1"),
"L17", "mt8135",
MTK_EINT_FUNCTION(2, 140),
MTK_FUNCTION(0, "GPIO11"),
@@ -157,8 +145,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "USB_DRVVBUS"),
MTK_FUNCTION(7, "TESTA_OUT5")
),
- MTK_PIN(
- PINCTRL_PIN(12, "NRNB"),
+ MTK_PIN(PINCTRL_PIN(12, "NRNB"),
"G19", "mt8135",
MTK_EINT_FUNCTION(2, 141),
MTK_FUNCTION(0, "GPIO12"),
@@ -167,8 +154,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(3, "A_FUNC_DOUT[4]"),
MTK_FUNCTION(7, "TESTA_OUT6")
),
- MTK_PIN(
- PINCTRL_PIN(13, "NCLE"),
+ MTK_PIN(PINCTRL_PIN(13, "NCLE"),
"J18", "mt8135",
MTK_EINT_FUNCTION(2, 142),
MTK_FUNCTION(0, "GPIO13"),
@@ -179,8 +165,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "NALE"),
MTK_FUNCTION(7, "TESTA_OUT7")
),
- MTK_PIN(
- PINCTRL_PIN(14, "NALE"),
+ MTK_PIN(PINCTRL_PIN(14, "NALE"),
"J19", "mt8135",
MTK_EINT_FUNCTION(2, 143),
MTK_FUNCTION(0, "GPIO14"),
@@ -192,8 +177,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "NCLE"),
MTK_FUNCTION(7, "TESTA_OUT8")
),
- MTK_PIN(
- PINCTRL_PIN(15, "NREB"),
+ MTK_PIN(PINCTRL_PIN(15, "NREB"),
"L18", "mt8135",
MTK_EINT_FUNCTION(2, 144),
MTK_FUNCTION(0, "GPIO15"),
@@ -204,8 +188,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "IRDA_TXD"),
MTK_FUNCTION(7, "TESTA_OUT9")
),
- MTK_PIN(
- PINCTRL_PIN(16, "NWEB"),
+ MTK_PIN(PINCTRL_PIN(16, "NWEB"),
"J20", "mt8135",
MTK_EINT_FUNCTION(2, 145),
MTK_FUNCTION(0, "GPIO16"),
@@ -216,8 +199,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "IRDA_PDN"),
MTK_FUNCTION(7, "TESTA_OUT10")
),
- MTK_PIN(
- PINCTRL_PIN(17, "NLD0"),
+ MTK_PIN(PINCTRL_PIN(17, "NLD0"),
"K21", "mt8135",
MTK_EINT_FUNCTION(2, 146),
MTK_FUNCTION(0, "GPIO17"),
@@ -229,8 +211,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "DAC_CK"),
MTK_FUNCTION(7, "TESTA_OUT11")
),
- MTK_PIN(
- PINCTRL_PIN(18, "NLD1"),
+ MTK_PIN(PINCTRL_PIN(18, "NLD1"),
"K22", "mt8135",
MTK_EINT_FUNCTION(2, 147),
MTK_FUNCTION(0, "GPIO18"),
@@ -242,8 +223,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "DAC_WS"),
MTK_FUNCTION(7, "TESTA_OUT12")
),
- MTK_PIN(
- PINCTRL_PIN(19, "NLD2"),
+ MTK_PIN(PINCTRL_PIN(19, "NLD2"),
"J21", "mt8135",
MTK_EINT_FUNCTION(2, 148),
MTK_FUNCTION(0, "GPIO19"),
@@ -255,8 +235,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "DAC_DAT_OUT"),
MTK_FUNCTION(7, "TESTA_OUT13")
),
- MTK_PIN(
- PINCTRL_PIN(20, "NLD3"),
+ MTK_PIN(PINCTRL_PIN(20, "NLD3"),
"J23", "mt8135",
MTK_EINT_FUNCTION(2, 149),
MTK_FUNCTION(0, "GPIO20"),
@@ -266,8 +245,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "CM2DAT_1X[3]"),
MTK_FUNCTION(7, "TESTA_OUT14")
),
- MTK_PIN(
- PINCTRL_PIN(21, "NLD4"),
+ MTK_PIN(PINCTRL_PIN(21, "NLD4"),
"J22", "mt8135",
MTK_EINT_FUNCTION(2, 150),
MTK_FUNCTION(0, "GPIO21"),
@@ -277,8 +255,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "CM2DAT_1X[4]"),
MTK_FUNCTION(7, "TESTA_OUT15")
),
- MTK_PIN(
- PINCTRL_PIN(22, "NLD5"),
+ MTK_PIN(PINCTRL_PIN(22, "NLD5"),
"H21", "mt8135",
MTK_EINT_FUNCTION(2, 151),
MTK_FUNCTION(0, "GPIO22"),
@@ -288,8 +265,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "CM2DAT_1X[5]"),
MTK_FUNCTION(7, "TESTA_OUT16")
),
- MTK_PIN(
- PINCTRL_PIN(23, "NLD6"),
+ MTK_PIN(PINCTRL_PIN(23, "NLD6"),
"H22", "mt8135",
MTK_EINT_FUNCTION(2, 152),
MTK_FUNCTION(0, "GPIO23"),
@@ -299,8 +275,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "CM2DAT_1X[6]"),
MTK_FUNCTION(7, "TESTA_OUT17")
),
- MTK_PIN(
- PINCTRL_PIN(24, "NLD7"),
+ MTK_PIN(PINCTRL_PIN(24, "NLD7"),
"H20", "mt8135",
MTK_EINT_FUNCTION(2, 153),
MTK_FUNCTION(0, "GPIO24"),
@@ -310,8 +285,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "CM2DAT_1X[7]"),
MTK_FUNCTION(7, "TESTA_OUT18")
),
- MTK_PIN(
- PINCTRL_PIN(25, "NLD8"),
+ MTK_PIN(PINCTRL_PIN(25, "NLD8"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 154),
MTK_FUNCTION(0, "GPIO25"),
@@ -319,8 +293,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(2, "EINT154"),
MTK_FUNCTION(4, "CM2DAT_1X[8]")
),
- MTK_PIN(
- PINCTRL_PIN(26, "NLD9"),
+ MTK_PIN(PINCTRL_PIN(26, "NLD9"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 155),
MTK_FUNCTION(0, "GPIO26"),
@@ -329,8 +302,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "CM2DAT_1X[9]"),
MTK_FUNCTION(5, "PWM1")
),
- MTK_PIN(
- PINCTRL_PIN(27, "NLD10"),
+ MTK_PIN(PINCTRL_PIN(27, "NLD10"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 156),
MTK_FUNCTION(0, "GPIO27"),
@@ -339,8 +311,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "CM2VSYNC_1X"),
MTK_FUNCTION(5, "PWM2")
),
- MTK_PIN(
- PINCTRL_PIN(28, "NLD11"),
+ MTK_PIN(PINCTRL_PIN(28, "NLD11"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 157),
MTK_FUNCTION(0, "GPIO28"),
@@ -349,8 +320,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "CM2HSYNC_1X"),
MTK_FUNCTION(5, "PWM3")
),
- MTK_PIN(
- PINCTRL_PIN(29, "NLD12"),
+ MTK_PIN(PINCTRL_PIN(29, "NLD12"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 158),
MTK_FUNCTION(0, "GPIO29"),
@@ -360,8 +330,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "DAC_CK"),
MTK_FUNCTION(5, "PCM1_CK")
),
- MTK_PIN(
- PINCTRL_PIN(30, "NLD13"),
+ MTK_PIN(PINCTRL_PIN(30, "NLD13"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 159),
MTK_FUNCTION(0, "GPIO30"),
@@ -371,8 +340,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "DAC_WS"),
MTK_FUNCTION(5, "PCM1_WS")
),
- MTK_PIN(
- PINCTRL_PIN(31, "NLD14"),
+ MTK_PIN(PINCTRL_PIN(31, "NLD14"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 160),
MTK_FUNCTION(0, "GPIO31"),
@@ -382,8 +350,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "DAC_DAT_OUT"),
MTK_FUNCTION(5, "PCM1_DO")
),
- MTK_PIN(
- PINCTRL_PIN(32, "NLD15"),
+ MTK_PIN(PINCTRL_PIN(32, "NLD15"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 161),
MTK_FUNCTION(0, "GPIO32"),
@@ -393,8 +360,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "PWM4"),
MTK_FUNCTION(5, "PCM1_DI")
),
- MTK_PIN(
- PINCTRL_PIN(33, "MSDC0_RSTB"),
+ MTK_PIN(PINCTRL_PIN(33, "MSDC0_RSTB"),
"G22", "mt8135",
MTK_EINT_FUNCTION(2, 50),
MTK_FUNCTION(0, "GPIO33"),
@@ -405,16 +371,14 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "SPI1_MI"),
MTK_FUNCTION(7, "NLD10")
),
- MTK_PIN(
- PINCTRL_PIN(34, "IDDIG"),
+ MTK_PIN(PINCTRL_PIN(34, "IDDIG"),
"N17", "mt8135",
MTK_EINT_FUNCTION(2, 34),
MTK_FUNCTION(0, "GPIO34"),
MTK_FUNCTION(1, "IDDIG"),
MTK_FUNCTION(2, "EINT34")
),
- MTK_PIN(
- PINCTRL_PIN(35, "SCL3"),
+ MTK_PIN(PINCTRL_PIN(35, "SCL3"),
"L19", "mt8135",
MTK_EINT_FUNCTION(2, 96),
MTK_FUNCTION(0, "GPIO35"),
@@ -423,16 +387,14 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(3, "CLKM6"),
MTK_FUNCTION(4, "PWM6")
),
- MTK_PIN(
- PINCTRL_PIN(36, "SDA3"),
+ MTK_PIN(PINCTRL_PIN(36, "SDA3"),
"L20", "mt8135",
MTK_EINT_FUNCTION(2, 97),
MTK_FUNCTION(0, "GPIO36"),
MTK_FUNCTION(1, "SDA3"),
MTK_FUNCTION(2, "EINT97")
),
- MTK_PIN(
- PINCTRL_PIN(37, "AUD_CLK_MOSI"),
+ MTK_PIN(PINCTRL_PIN(37, "AUD_CLK_MOSI"),
"L21", "mt8135",
MTK_EINT_FUNCTION(4, 19),
MTK_FUNCTION(0, "GPIO37"),
@@ -443,8 +405,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "USB_TEST_IO[6]"),
MTK_FUNCTION(7, "TESTA_OUT19")
),
- MTK_PIN(
- PINCTRL_PIN(38, "AUD_DAT_MOSI"),
+ MTK_PIN(PINCTRL_PIN(38, "AUD_DAT_MOSI"),
"L23", "mt8135",
MTK_EINT_FUNCTION(4, 21),
MTK_FUNCTION(0, "GPIO38"),
@@ -455,8 +416,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "USB_TEST_IO[7]"),
MTK_FUNCTION(7, "TESTA_OUT20")
),
- MTK_PIN(
- PINCTRL_PIN(39, "AUD_DAT_MISO"),
+ MTK_PIN(PINCTRL_PIN(39, "AUD_DAT_MISO"),
"L22", "mt8135",
MTK_EINT_FUNCTION(4, 20),
MTK_FUNCTION(0, "GPIO39"),
@@ -467,8 +427,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "USB_TEST_IO[8]"),
MTK_FUNCTION(7, "TESTA_OUT21")
),
- MTK_PIN(
- PINCTRL_PIN(40, "DAC_CLK"),
+ MTK_PIN(PINCTRL_PIN(40, "DAC_CLK"),
"P21", "mt8135",
MTK_EINT_FUNCTION(2, 22),
MTK_FUNCTION(0, "GPIO40"),
@@ -478,8 +437,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "USB_TEST_IO[9]"),
MTK_FUNCTION(7, "TESTA_OUT22")
),
- MTK_PIN(
- PINCTRL_PIN(41, "DAC_WS"),
+ MTK_PIN(PINCTRL_PIN(41, "DAC_WS"),
"N18", "mt8135",
MTK_EINT_FUNCTION(2, 24),
MTK_FUNCTION(0, "GPIO41"),
@@ -489,8 +447,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "USB_TEST_IO[10]"),
MTK_FUNCTION(7, "TESTA_OUT23")
),
- MTK_PIN(
- PINCTRL_PIN(42, "DAC_DAT_OUT"),
+ MTK_PIN(PINCTRL_PIN(42, "DAC_DAT_OUT"),
"N22", "mt8135",
MTK_EINT_FUNCTION(2, 23),
MTK_FUNCTION(0, "GPIO42"),
@@ -500,40 +457,35 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "USB_TEST_IO[11]"),
MTK_FUNCTION(7, "TESTA_OUT24")
),
- MTK_PIN(
- PINCTRL_PIN(43, "PWRAP_SPI0_MO"),
+ MTK_PIN(PINCTRL_PIN(43, "PWRAP_SPI0_MO"),
"M22", "mt8135",
MTK_EINT_FUNCTION(2, 29),
MTK_FUNCTION(0, "GPIO43"),
MTK_FUNCTION(1, "PWRAP_SPIDI"),
MTK_FUNCTION(2, "EINT29")
),
- MTK_PIN(
- PINCTRL_PIN(44, "PWRAP_SPI0_MI"),
+ MTK_PIN(PINCTRL_PIN(44, "PWRAP_SPI0_MI"),
"P23", "mt8135",
MTK_EINT_FUNCTION(2, 28),
MTK_FUNCTION(0, "GPIO44"),
MTK_FUNCTION(1, "PWRAP_SPIDO"),
MTK_FUNCTION(2, "EINT28")
),
- MTK_PIN(
- PINCTRL_PIN(45, "PWRAP_SPI0_CSN"),
+ MTK_PIN(PINCTRL_PIN(45, "PWRAP_SPI0_CSN"),
"M21", "mt8135",
MTK_EINT_FUNCTION(2, 27),
MTK_FUNCTION(0, "GPIO45"),
MTK_FUNCTION(1, "PWRAP_SPICS_B_I"),
MTK_FUNCTION(2, "EINT27")
),
- MTK_PIN(
- PINCTRL_PIN(46, "PWRAP_SPI0_CLK"),
+ MTK_PIN(PINCTRL_PIN(46, "PWRAP_SPI0_CLK"),
"P22", "mt8135",
MTK_EINT_FUNCTION(2, 26),
MTK_FUNCTION(0, "GPIO46"),
MTK_FUNCTION(1, "PWRAP_SPICK_I"),
MTK_FUNCTION(2, "EINT26")
),
- MTK_PIN(
- PINCTRL_PIN(47, "PWRAP_EVENT"),
+ MTK_PIN(PINCTRL_PIN(47, "PWRAP_EVENT"),
"M23", "mt8135",
MTK_EINT_FUNCTION(2, 25),
MTK_FUNCTION(0, "GPIO47"),
@@ -541,39 +493,34 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(2, "EINT25"),
MTK_FUNCTION(7, "TESTA_OUT2")
),
- MTK_PIN(
- PINCTRL_PIN(48, "RTC32K_CK"),
+ MTK_PIN(PINCTRL_PIN(48, "RTC32K_CK"),
"N20", "mt8135",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO48"),
MTK_FUNCTION(1, "RTC32K_CK")
),
- MTK_PIN(
- PINCTRL_PIN(49, "WATCHDOG"),
+ MTK_PIN(PINCTRL_PIN(49, "WATCHDOG"),
"R22", "mt8135",
MTK_EINT_FUNCTION(2, 36),
MTK_FUNCTION(0, "GPIO49"),
MTK_FUNCTION(1, "WATCHDOG"),
MTK_FUNCTION(2, "EINT36")
),
- MTK_PIN(
- PINCTRL_PIN(50, "SRCLKENA"),
+ MTK_PIN(PINCTRL_PIN(50, "SRCLKENA"),
"T22", "mt8135",
MTK_EINT_FUNCTION(2, 38),
MTK_FUNCTION(0, "GPIO50"),
MTK_FUNCTION(1, "SRCLKENA"),
MTK_FUNCTION(2, "EINT38")
),
- MTK_PIN(
- PINCTRL_PIN(51, "SRCVOLTEN"),
+ MTK_PIN(PINCTRL_PIN(51, "SRCVOLTEN"),
"T23", "mt8135",
MTK_EINT_FUNCTION(2, 37),
MTK_FUNCTION(0, "GPIO51"),
MTK_FUNCTION(1, "SRCVOLTEN"),
MTK_FUNCTION(2, "EINT37")
),
- MTK_PIN(
- PINCTRL_PIN(52, "EINT0"),
+ MTK_PIN(PINCTRL_PIN(52, "EINT0"),
"T21", "mt8135",
MTK_EINT_FUNCTION(1, 0),
MTK_FUNCTION(0, "GPIO52"),
@@ -584,8 +531,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "USB_TEST_IO[12]"),
MTK_FUNCTION(7, "USB_SCL")
),
- MTK_PIN(
- PINCTRL_PIN(53, "URXD2"),
+ MTK_PIN(PINCTRL_PIN(53, "URXD2"),
"R18", "mt8135",
MTK_EINT_FUNCTION(2, 83),
MTK_FUNCTION(0, "GPIO53"),
@@ -595,8 +541,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "CLKM3"),
MTK_FUNCTION(7, "UTXD2")
),
- MTK_PIN(
- PINCTRL_PIN(54, "UTXD2"),
+ MTK_PIN(PINCTRL_PIN(54, "UTXD2"),
"R17", "mt8135",
MTK_EINT_FUNCTION(2, 82),
MTK_FUNCTION(0, "GPIO54"),
@@ -606,8 +551,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "CLKM2"),
MTK_FUNCTION(7, "URXD2")
),
- MTK_PIN(
- PINCTRL_PIN(55, "UCTS2"),
+ MTK_PIN(PINCTRL_PIN(55, "UCTS2"),
"R20", "mt8135",
MTK_EINT_FUNCTION(2, 84),
MTK_FUNCTION(0, "GPIO55"),
@@ -616,8 +560,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "PWM1"),
MTK_FUNCTION(7, "URTS2")
),
- MTK_PIN(
- PINCTRL_PIN(56, "URTS2"),
+ MTK_PIN(PINCTRL_PIN(56, "URTS2"),
"R19", "mt8135",
MTK_EINT_FUNCTION(2, 85),
MTK_FUNCTION(0, "GPIO56"),
@@ -626,8 +569,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "PWM2"),
MTK_FUNCTION(7, "UCTS2")
),
- MTK_PIN(
- PINCTRL_PIN(57, "JTCK"),
+ MTK_PIN(PINCTRL_PIN(57, "JTCK"),
"V17", "mt8135",
MTK_EINT_FUNCTION(2, 188),
MTK_FUNCTION(0, "GPIO57"),
@@ -635,8 +577,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(2, "EINT188"),
MTK_FUNCTION(3, "DSP1_ICK")
),
- MTK_PIN(
- PINCTRL_PIN(58, "JTDO"),
+ MTK_PIN(PINCTRL_PIN(58, "JTDO"),
"T16", "mt8135",
MTK_EINT_FUNCTION(2, 190),
MTK_FUNCTION(0, "GPIO58"),
@@ -644,8 +585,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(2, "EINT190"),
MTK_FUNCTION(3, "DSP2_IMS")
),
- MTK_PIN(
- PINCTRL_PIN(59, "JTRST_B"),
+ MTK_PIN(PINCTRL_PIN(59, "JTRST_B"),
"T19", "mt8135",
MTK_EINT_FUNCTION(2, 0),
MTK_FUNCTION(0, "GPIO59"),
@@ -653,8 +593,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(2, "EINT0"),
MTK_FUNCTION(3, "DSP2_ICK")
),
- MTK_PIN(
- PINCTRL_PIN(60, "JTDI"),
+ MTK_PIN(PINCTRL_PIN(60, "JTDI"),
"T18", "mt8135",
MTK_EINT_FUNCTION(2, 189),
MTK_FUNCTION(0, "GPIO60"),
@@ -662,8 +601,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(2, "EINT189"),
MTK_FUNCTION(3, "DSP1_IMS")
),
- MTK_PIN(
- PINCTRL_PIN(61, "JRTCK"),
+ MTK_PIN(PINCTRL_PIN(61, "JRTCK"),
"T20", "mt8135",
MTK_EINT_FUNCTION(2, 187),
MTK_FUNCTION(0, "GPIO61"),
@@ -671,8 +609,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(2, "EINT187"),
MTK_FUNCTION(3, "DSP1_ID")
),
- MTK_PIN(
- PINCTRL_PIN(62, "JTMS"),
+ MTK_PIN(PINCTRL_PIN(62, "JTMS"),
"T17", "mt8135",
MTK_EINT_FUNCTION(2, 191),
MTK_FUNCTION(0, "GPIO62"),
@@ -680,8 +617,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(2, "EINT191"),
MTK_FUNCTION(3, "DSP2_ID")
),
- MTK_PIN(
- PINCTRL_PIN(63, "MSDC1_INSI"),
+ MTK_PIN(PINCTRL_PIN(63, "MSDC1_INSI"),
"V18", "mt8135",
MTK_EINT_FUNCTION(1, 15),
MTK_FUNCTION(0, "GPIO63"),
@@ -691,8 +627,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "CLKM5"),
MTK_FUNCTION(7, "TESTB_OUT6")
),
- MTK_PIN(
- PINCTRL_PIN(64, "MSDC1_SDWPI"),
+ MTK_PIN(PINCTRL_PIN(64, "MSDC1_SDWPI"),
"W18", "mt8135",
MTK_EINT_FUNCTION(2, 58),
MTK_FUNCTION(0, "GPIO64"),
@@ -703,8 +638,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "CLKM6"),
MTK_FUNCTION(7, "TESTB_OUT7")
),
- MTK_PIN(
- PINCTRL_PIN(65, "MSDC2_INSI"),
+ MTK_PIN(PINCTRL_PIN(65, "MSDC2_INSI"),
"U22", "mt8135",
MTK_EINT_FUNCTION(1, 14),
MTK_FUNCTION(0, "GPIO65"),
@@ -712,8 +646,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "USB_TEST_IO[27]"),
MTK_FUNCTION(7, "TESTA_OUT3")
),
- MTK_PIN(
- PINCTRL_PIN(66, "MSDC2_SDWPI"),
+ MTK_PIN(PINCTRL_PIN(66, "MSDC2_SDWPI"),
"U21", "mt8135",
MTK_EINT_FUNCTION(2, 66),
MTK_FUNCTION(0, "GPIO66"),
@@ -721,8 +654,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(2, "EINT66"),
MTK_FUNCTION(5, "USB_TEST_IO[28]")
),
- MTK_PIN(
- PINCTRL_PIN(67, "URXD4"),
+ MTK_PIN(PINCTRL_PIN(67, "URXD4"),
"V23", "mt8135",
MTK_EINT_FUNCTION(2, 89),
MTK_FUNCTION(0, "GPIO67"),
@@ -732,8 +664,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "UTXD4"),
MTK_FUNCTION(7, "TESTB_OUT10")
),
- MTK_PIN(
- PINCTRL_PIN(68, "UTXD4"),
+ MTK_PIN(PINCTRL_PIN(68, "UTXD4"),
"V22", "mt8135",
MTK_EINT_FUNCTION(2, 88),
MTK_FUNCTION(0, "GPIO68"),
@@ -743,8 +674,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "URXD4"),
MTK_FUNCTION(7, "TESTB_OUT11")
),
- MTK_PIN(
- PINCTRL_PIN(69, "URXD1"),
+ MTK_PIN(PINCTRL_PIN(69, "URXD1"),
"W22", "mt8135",
MTK_EINT_FUNCTION(2, 79),
MTK_FUNCTION(0, "GPIO69"),
@@ -754,8 +684,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "UTXD1"),
MTK_FUNCTION(7, "TESTB_OUT24")
),
- MTK_PIN(
- PINCTRL_PIN(70, "UTXD1"),
+ MTK_PIN(PINCTRL_PIN(70, "UTXD1"),
"V21", "mt8135",
MTK_EINT_FUNCTION(2, 78),
MTK_FUNCTION(0, "GPIO70"),
@@ -765,8 +694,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "URXD1"),
MTK_FUNCTION(7, "TESTB_OUT25")
),
- MTK_PIN(
- PINCTRL_PIN(71, "UCTS1"),
+ MTK_PIN(PINCTRL_PIN(71, "UCTS1"),
"V19", "mt8135",
MTK_EINT_FUNCTION(2, 80),
MTK_FUNCTION(0, "GPIO71"),
@@ -776,8 +704,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "URTS1"),
MTK_FUNCTION(7, "TESTB_OUT31")
),
- MTK_PIN(
- PINCTRL_PIN(72, "URTS1"),
+ MTK_PIN(PINCTRL_PIN(72, "URTS1"),
"V20", "mt8135",
MTK_EINT_FUNCTION(2, 81),
MTK_FUNCTION(0, "GPIO72"),
@@ -787,8 +714,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "UCTS1"),
MTK_FUNCTION(7, "TESTB_OUT21")
),
- MTK_PIN(
- PINCTRL_PIN(73, "PWM1"),
+ MTK_PIN(PINCTRL_PIN(73, "PWM1"),
"W17", "mt8135",
MTK_EINT_FUNCTION(2, 73),
MTK_FUNCTION(0, "GPIO73"),
@@ -798,8 +724,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "DISP_PWM"),
MTK_FUNCTION(7, "TESTB_OUT8")
),
- MTK_PIN(
- PINCTRL_PIN(74, "PWM2"),
+ MTK_PIN(PINCTRL_PIN(74, "PWM2"),
"Y17", "mt8135",
MTK_EINT_FUNCTION(2, 74),
MTK_FUNCTION(0, "GPIO74"),
@@ -811,8 +736,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "DISP_PWM"),
MTK_FUNCTION(7, "TESTB_OUT9")
),
- MTK_PIN(
- PINCTRL_PIN(75, "PWM3"),
+ MTK_PIN(PINCTRL_PIN(75, "PWM3"),
"Y19", "mt8135",
MTK_EINT_FUNCTION(2, 75),
MTK_FUNCTION(0, "GPIO75"),
@@ -824,8 +748,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "DISP_PWM"),
MTK_FUNCTION(7, "TESTB_OUT12")
),
- MTK_PIN(
- PINCTRL_PIN(76, "PWM4"),
+ MTK_PIN(PINCTRL_PIN(76, "PWM4"),
"W19", "mt8135",
MTK_EINT_FUNCTION(2, 76),
MTK_FUNCTION(0, "GPIO76"),
@@ -836,8 +759,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "DISP_PWM"),
MTK_FUNCTION(7, "TESTB_OUT13")
),
- MTK_PIN(
- PINCTRL_PIN(77, "MSDC2_DAT2"),
+ MTK_PIN(PINCTRL_PIN(77, "MSDC2_DAT2"),
"W21", "mt8135",
MTK_EINT_FUNCTION(2, 63),
MTK_FUNCTION(0, "GPIO77"),
@@ -847,8 +769,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "DPI33_D6"),
MTK_FUNCTION(7, "TESTA_OUT25")
),
- MTK_PIN(
- PINCTRL_PIN(78, "MSDC2_DAT3"),
+ MTK_PIN(PINCTRL_PIN(78, "MSDC2_DAT3"),
"AA23", "mt8135",
MTK_EINT_FUNCTION(2, 64),
MTK_FUNCTION(0, "GPIO78"),
@@ -858,8 +779,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "DPI33_D7"),
MTK_FUNCTION(7, "TESTA_OUT26")
),
- MTK_PIN(
- PINCTRL_PIN(79, "MSDC2_CMD"),
+ MTK_PIN(PINCTRL_PIN(79, "MSDC2_CMD"),
"Y22", "mt8135",
MTK_EINT_FUNCTION(2, 60),
MTK_FUNCTION(0, "GPIO79"),
@@ -870,8 +790,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "DPI33_D3"),
MTK_FUNCTION(7, "TESTA_OUT0")
),
- MTK_PIN(
- PINCTRL_PIN(80, "MSDC2_CLK"),
+ MTK_PIN(PINCTRL_PIN(80, "MSDC2_CLK"),
"AA22", "mt8135",
MTK_EINT_FUNCTION(2, 59),
MTK_FUNCTION(0, "GPIO80"),
@@ -882,8 +801,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "DPI33_D2"),
MTK_FUNCTION(7, "TESTA_OUT1")
),
- MTK_PIN(
- PINCTRL_PIN(81, "MSDC2_DAT1"),
+ MTK_PIN(PINCTRL_PIN(81, "MSDC2_DAT1"),
"Y21", "mt8135",
MTK_EINT_FUNCTION(2, 62),
MTK_FUNCTION(0, "GPIO81"),
@@ -893,8 +811,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "PCM1_DO"),
MTK_FUNCTION(6, "DPI33_D5")
),
- MTK_PIN(
- PINCTRL_PIN(82, "MSDC2_DAT0"),
+ MTK_PIN(PINCTRL_PIN(82, "MSDC2_DAT0"),
"AB22", "mt8135",
MTK_EINT_FUNCTION(2, 61),
MTK_FUNCTION(0, "GPIO82"),
@@ -904,8 +821,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "PCM1_DI"),
MTK_FUNCTION(6, "DPI33_D4")
),
- MTK_PIN(
- PINCTRL_PIN(83, "MSDC1_DAT0"),
+ MTK_PIN(PINCTRL_PIN(83, "MSDC1_DAT0"),
"AC19", "mt8135",
MTK_EINT_FUNCTION(2, 53),
MTK_FUNCTION(0, "GPIO83"),
@@ -916,8 +832,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "CLKM1"),
MTK_FUNCTION(7, "TESTB_OUT2")
),
- MTK_PIN(
- PINCTRL_PIN(84, "MSDC1_DAT1"),
+ MTK_PIN(PINCTRL_PIN(84, "MSDC1_DAT1"),
"AA19", "mt8135",
MTK_EINT_FUNCTION(2, 54),
MTK_FUNCTION(0, "GPIO84"),
@@ -928,8 +843,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "CLKM2"),
MTK_FUNCTION(7, "TESTB_OUT3")
),
- MTK_PIN(
- PINCTRL_PIN(85, "MSDC1_CMD"),
+ MTK_PIN(PINCTRL_PIN(85, "MSDC1_CMD"),
"AA20", "mt8135",
MTK_EINT_FUNCTION(2, 52),
MTK_FUNCTION(0, "GPIO85"),
@@ -940,8 +854,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "CLKM0"),
MTK_FUNCTION(7, "TESTB_OUT1")
),
- MTK_PIN(
- PINCTRL_PIN(86, "MSDC1_CLK"),
+ MTK_PIN(PINCTRL_PIN(86, "MSDC1_CLK"),
"AB19", "mt8135",
MTK_EINT_FUNCTION(2, 51),
MTK_FUNCTION(0, "GPIO86"),
@@ -951,8 +864,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "DISP_PWM"),
MTK_FUNCTION(7, "TESTB_OUT0")
),
- MTK_PIN(
- PINCTRL_PIN(87, "MSDC1_DAT2"),
+ MTK_PIN(PINCTRL_PIN(87, "MSDC1_DAT2"),
"AA21", "mt8135",
MTK_EINT_FUNCTION(2, 55),
MTK_FUNCTION(0, "GPIO87"),
@@ -963,8 +875,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "CLKM3"),
MTK_FUNCTION(7, "TESTB_OUT4")
),
- MTK_PIN(
- PINCTRL_PIN(88, "MSDC1_DAT3"),
+ MTK_PIN(PINCTRL_PIN(88, "MSDC1_DAT3"),
"AB20", "mt8135",
MTK_EINT_FUNCTION(2, 56),
MTK_FUNCTION(0, "GPIO88"),
@@ -975,8 +886,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "CLKM4"),
MTK_FUNCTION(7, "TESTB_OUT5")
),
- MTK_PIN(
- PINCTRL_PIN(89, "MSDC4_DAT0"),
+ MTK_PIN(PINCTRL_PIN(89, "MSDC4_DAT0"),
"AB8", "mt8135",
MTK_EINT_FUNCTION(2, 133),
MTK_FUNCTION(0, "GPIO89"),
@@ -987,8 +897,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "A_FUNC_DIN[9]"),
MTK_FUNCTION(7, "LPTE")
),
- MTK_PIN(
- PINCTRL_PIN(90, "MSDC4_DAT1"),
+ MTK_PIN(PINCTRL_PIN(90, "MSDC4_DAT1"),
"AB7", "mt8135",
MTK_EINT_FUNCTION(2, 134),
MTK_FUNCTION(0, "GPIO90"),
@@ -997,8 +906,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "A_FUNC_DIN[10]"),
MTK_FUNCTION(7, "LRSTB_1X")
),
- MTK_PIN(
- PINCTRL_PIN(91, "MSDC4_DAT5"),
+ MTK_PIN(PINCTRL_PIN(91, "MSDC4_DAT5"),
"AA8", "mt8135",
MTK_EINT_FUNCTION(2, 136),
MTK_FUNCTION(0, "GPIO91"),
@@ -1010,8 +918,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "A_FUNC_DIN[11]"),
MTK_FUNCTION(7, "SPI1_CSN")
),
- MTK_PIN(
- PINCTRL_PIN(92, "MSDC4_DAT6"),
+ MTK_PIN(PINCTRL_PIN(92, "MSDC4_DAT6"),
"AC4", "mt8135",
MTK_EINT_FUNCTION(2, 137),
MTK_FUNCTION(0, "GPIO92"),
@@ -1023,8 +930,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "A_FUNC_DIN[12]"),
MTK_FUNCTION(7, "SPI1_MO")
),
- MTK_PIN(
- PINCTRL_PIN(93, "MSDC4_DAT7"),
+ MTK_PIN(PINCTRL_PIN(93, "MSDC4_DAT7"),
"AC6", "mt8135",
MTK_EINT_FUNCTION(2, 138),
MTK_FUNCTION(0, "GPIO93"),
@@ -1035,8 +941,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "A_FUNC_DIN[13]"),
MTK_FUNCTION(7, "SPI1_MI")
),
- MTK_PIN(
- PINCTRL_PIN(94, "MSDC4_DAT4"),
+ MTK_PIN(PINCTRL_PIN(94, "MSDC4_DAT4"),
"AA7", "mt8135",
MTK_EINT_FUNCTION(2, 135),
MTK_FUNCTION(0, "GPIO94"),
@@ -1048,8 +953,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "A_FUNC_DIN[14]"),
MTK_FUNCTION(7, "SPI1_CLK")
),
- MTK_PIN(
- PINCTRL_PIN(95, "MSDC4_DAT2"),
+ MTK_PIN(PINCTRL_PIN(95, "MSDC4_DAT2"),
"AB6", "mt8135",
MTK_EINT_FUNCTION(2, 131),
MTK_FUNCTION(0, "GPIO95"),
@@ -1061,8 +965,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "PCM1_WS"),
MTK_FUNCTION(7, "LSCE0B_1X")
),
- MTK_PIN(
- PINCTRL_PIN(96, "MSDC4_CLK"),
+ MTK_PIN(PINCTRL_PIN(96, "MSDC4_CLK"),
"AB5", "mt8135",
MTK_EINT_FUNCTION(2, 129),
MTK_FUNCTION(0, "GPIO96"),
@@ -1074,8 +977,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "PCM1_DI"),
MTK_FUNCTION(7, "LSCK_1X")
),
- MTK_PIN(
- PINCTRL_PIN(97, "MSDC4_DAT3"),
+ MTK_PIN(PINCTRL_PIN(97, "MSDC4_DAT3"),
"Y8", "mt8135",
MTK_EINT_FUNCTION(2, 132),
MTK_FUNCTION(0, "GPIO97"),
@@ -1087,8 +989,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "PCM1_DO"),
MTK_FUNCTION(7, "LSCE1B_1X")
),
- MTK_PIN(
- PINCTRL_PIN(98, "MSDC4_CMD"),
+ MTK_PIN(PINCTRL_PIN(98, "MSDC4_CMD"),
"AC3", "mt8135",
MTK_EINT_FUNCTION(2, 128),
MTK_FUNCTION(0, "GPIO98"),
@@ -1098,8 +999,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "PWM3"),
MTK_FUNCTION(7, "LSDA_1X")
),
- MTK_PIN(
- PINCTRL_PIN(99, "MSDC4_RSTB"),
+ MTK_PIN(PINCTRL_PIN(99, "MSDC4_RSTB"),
"AB4", "mt8135",
MTK_EINT_FUNCTION(2, 130),
MTK_FUNCTION(0, "GPIO99"),
@@ -1111,8 +1011,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "PCM1_CK"),
MTK_FUNCTION(7, "LSA0_1X")
),
- MTK_PIN(
- PINCTRL_PIN(100, "SDA0"),
+ MTK_PIN(PINCTRL_PIN(100, "SDA0"),
"W9", "mt8135",
MTK_EINT_FUNCTION(2, 91),
MTK_FUNCTION(0, "GPIO100"),
@@ -1122,8 +1021,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "PWM1"),
MTK_FUNCTION(7, "A_FUNC_DIN[15]")
),
- MTK_PIN(
- PINCTRL_PIN(101, "SCL0"),
+ MTK_PIN(PINCTRL_PIN(101, "SCL0"),
"W11", "mt8135",
MTK_EINT_FUNCTION(2, 90),
MTK_FUNCTION(0, "GPIO101"),
@@ -1133,8 +1031,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "DISP_PWM"),
MTK_FUNCTION(7, "A_FUNC_DIN[16]")
),
- MTK_PIN(
- PINCTRL_PIN(102, "EINT10_AUXIN2"),
+ MTK_PIN(PINCTRL_PIN(102, "EINT10_AUXIN2"),
"AA3", "mt8135",
MTK_EINT_FUNCTION(1, 10),
MTK_FUNCTION(0, "GPIO102"),
@@ -1143,8 +1040,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "TESTB_OUT16"),
MTK_FUNCTION(7, "A_FUNC_DIN[17]")
),
- MTK_PIN(
- PINCTRL_PIN(103, "EINT11_AUXIN3"),
+ MTK_PIN(PINCTRL_PIN(103, "EINT11_AUXIN3"),
"AB2", "mt8135",
MTK_EINT_FUNCTION(1, 11),
MTK_FUNCTION(0, "GPIO103"),
@@ -1153,8 +1049,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "TESTB_OUT17"),
MTK_FUNCTION(7, "A_FUNC_DIN[18]")
),
- MTK_PIN(
- PINCTRL_PIN(104, "EINT16_AUXIN4"),
+ MTK_PIN(PINCTRL_PIN(104, "EINT16_AUXIN4"),
"AB3", "mt8135",
MTK_EINT_FUNCTION(1, 16),
MTK_FUNCTION(0, "GPIO104"),
@@ -1163,8 +1058,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "TESTB_OUT18"),
MTK_FUNCTION(7, "A_FUNC_DIN[19]")
),
- MTK_PIN(
- PINCTRL_PIN(105, "I2S_CLK"),
+ MTK_PIN(PINCTRL_PIN(105, "I2S_CLK"),
"W6", "mt8135",
MTK_EINT_FUNCTION(2, 10),
MTK_FUNCTION(0, "GPIO105"),
@@ -1176,8 +1070,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "TESTB_OUT19"),
MTK_FUNCTION(7, "A_FUNC_DIN[20]")
),
- MTK_PIN(
- PINCTRL_PIN(106, "I2S_WS"),
+ MTK_PIN(PINCTRL_PIN(106, "I2S_WS"),
"AA6", "mt8135",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO106"),
@@ -1188,8 +1081,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "TESTB_OUT20"),
MTK_FUNCTION(7, "A_FUNC_DIN[21]")
),
- MTK_PIN(
- PINCTRL_PIN(107, "I2S_DATA_IN"),
+ MTK_PIN(PINCTRL_PIN(107, "I2S_DATA_IN"),
"AA5", "mt8135",
MTK_EINT_FUNCTION(2, 11),
MTK_FUNCTION(0, "GPIO107"),
@@ -1200,8 +1092,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "TESTB_OUT22"),
MTK_FUNCTION(7, "A_FUNC_DIN[22]")
),
- MTK_PIN(
- PINCTRL_PIN(108, "I2S_DATA_OUT"),
+ MTK_PIN(PINCTRL_PIN(108, "I2S_DATA_OUT"),
"AA4", "mt8135",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO108"),
@@ -1212,8 +1103,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "TESTB_OUT23"),
MTK_FUNCTION(7, "A_FUNC_DIN[23]")
),
- MTK_PIN(
- PINCTRL_PIN(109, "EINT5"),
+ MTK_PIN(PINCTRL_PIN(109, "EINT5"),
"W5", "mt8135",
MTK_EINT_FUNCTION(1, 5),
MTK_FUNCTION(0, "GPIO109"),
@@ -1225,8 +1115,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "TESTB_OUT26"),
MTK_FUNCTION(7, "A_FUNC_DIN[24]")
),
- MTK_PIN(
- PINCTRL_PIN(110, "EINT6"),
+ MTK_PIN(PINCTRL_PIN(110, "EINT6"),
"V5", "mt8135",
MTK_EINT_FUNCTION(1, 6),
MTK_FUNCTION(0, "GPIO110"),
@@ -1238,8 +1127,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "TESTB_OUT27"),
MTK_FUNCTION(7, "A_FUNC_DIN[25]")
),
- MTK_PIN(
- PINCTRL_PIN(111, "EINT7"),
+ MTK_PIN(PINCTRL_PIN(111, "EINT7"),
"W3", "mt8135",
MTK_EINT_FUNCTION(1, 7),
MTK_FUNCTION(0, "GPIO111"),
@@ -1251,8 +1139,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "TESTB_OUT28"),
MTK_FUNCTION(7, "A_FUNC_DIN[26]")
),
- MTK_PIN(
- PINCTRL_PIN(112, "EINT8"),
+ MTK_PIN(PINCTRL_PIN(112, "EINT8"),
"V6", "mt8135",
MTK_EINT_FUNCTION(1, 8),
MTK_FUNCTION(0, "GPIO112"),
@@ -1264,8 +1151,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "TESTB_OUT29"),
MTK_FUNCTION(7, "EXT_FRAME_SYNC")
),
- MTK_PIN(
- PINCTRL_PIN(113, "EINT9"),
+ MTK_PIN(PINCTRL_PIN(113, "EINT9"),
"W8", "mt8135",
MTK_EINT_FUNCTION(1, 9),
MTK_FUNCTION(0, "GPIO113"),
@@ -1275,8 +1161,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "TESTB_OUT30"),
MTK_FUNCTION(7, "A_FUNC_DIN[27]")
),
- MTK_PIN(
- PINCTRL_PIN(114, "LPCE1B"),
+ MTK_PIN(PINCTRL_PIN(114, "LPCE1B"),
"W4", "mt8135",
MTK_EINT_FUNCTION(2, 127),
MTK_FUNCTION(0, "GPIO114"),
@@ -1286,8 +1171,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "TESTB_OUT14"),
MTK_FUNCTION(7, "A_FUNC_DIN[28]")
),
- MTK_PIN(
- PINCTRL_PIN(115, "LPCE0B"),
+ MTK_PIN(PINCTRL_PIN(115, "LPCE0B"),
"T5", "mt8135",
MTK_EINT_FUNCTION(2, 126),
MTK_FUNCTION(0, "GPIO115"),
@@ -1297,8 +1181,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "TESTB_OUT15"),
MTK_FUNCTION(7, "A_FUNC_DIN[29]")
),
- MTK_PIN(
- PINCTRL_PIN(116, "DISP_PWM"),
+ MTK_PIN(PINCTRL_PIN(116, "DISP_PWM"),
"V4", "mt8135",
MTK_EINT_FUNCTION(2, 77),
MTK_FUNCTION(0, "GPIO116"),
@@ -1309,8 +1192,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "PWM2"),
MTK_FUNCTION(7, "PWM3")
),
- MTK_PIN(
- PINCTRL_PIN(117, "EINT1"),
+ MTK_PIN(PINCTRL_PIN(117, "EINT1"),
"T6", "mt8135",
MTK_EINT_FUNCTION(1, 1),
MTK_FUNCTION(0, "GPIO117"),
@@ -1320,8 +1202,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "USB_TEST_IO[13]"),
MTK_FUNCTION(7, "USB_SDA")
),
- MTK_PIN(
- PINCTRL_PIN(118, "EINT2"),
+ MTK_PIN(PINCTRL_PIN(118, "EINT2"),
"T4", "mt8135",
MTK_EINT_FUNCTION(1, 2),
MTK_FUNCTION(0, "GPIO118"),
@@ -1332,8 +1213,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "SRCLKENAI2"),
MTK_FUNCTION(7, "A_FUNC_DIN[30]")
),
- MTK_PIN(
- PINCTRL_PIN(119, "EINT3"),
+ MTK_PIN(PINCTRL_PIN(119, "EINT3"),
"R4", "mt8135",
MTK_EINT_FUNCTION(1, 3),
MTK_FUNCTION(0, "GPIO119"),
@@ -1342,8 +1222,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "SRCLKENAI1"),
MTK_FUNCTION(7, "EXT_26M_CK")
),
- MTK_PIN(
- PINCTRL_PIN(120, "EINT4"),
+ MTK_PIN(PINCTRL_PIN(120, "EINT4"),
"R5", "mt8135",
MTK_EINT_FUNCTION(1, 4),
MTK_FUNCTION(0, "GPIO120"),
@@ -1352,8 +1231,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "USB_DRVVBUS"),
MTK_FUNCTION(7, "A_FUNC_DIN[31]")
),
- MTK_PIN(
- PINCTRL_PIN(121, "DPIDE"),
+ MTK_PIN(PINCTRL_PIN(121, "DPIDE"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 100),
MTK_FUNCTION(0, "GPIO121"),
@@ -1364,8 +1242,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "PCM1_DO"),
MTK_FUNCTION(6, "IRDA_TXD")
),
- MTK_PIN(
- PINCTRL_PIN(122, "DPICK"),
+ MTK_PIN(PINCTRL_PIN(122, "DPICK"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 101),
MTK_FUNCTION(0, "GPIO122"),
@@ -1375,8 +1252,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "PCM1_DI"),
MTK_FUNCTION(6, "IRDA_PDN")
),
- MTK_PIN(
- PINCTRL_PIN(123, "DPIG4"),
+ MTK_PIN(PINCTRL_PIN(123, "DPIG4"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 114),
MTK_FUNCTION(0, "GPIO123"),
@@ -1385,8 +1261,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "CM2DAT_2X[0]"),
MTK_FUNCTION(5, "DSP2_ID")
),
- MTK_PIN(
- PINCTRL_PIN(124, "DPIG5"),
+ MTK_PIN(PINCTRL_PIN(124, "DPIG5"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 115),
MTK_FUNCTION(0, "GPIO124"),
@@ -1395,8 +1270,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "CM2DAT_2X[1]"),
MTK_FUNCTION(5, "DSP2_ICK")
),
- MTK_PIN(
- PINCTRL_PIN(125, "DPIR3"),
+ MTK_PIN(PINCTRL_PIN(125, "DPIR3"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 121),
MTK_FUNCTION(0, "GPIO125"),
@@ -1404,8 +1278,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(2, "EINT121"),
MTK_FUNCTION(4, "CM2DAT_2X[7]")
),
- MTK_PIN(
- PINCTRL_PIN(126, "DPIG1"),
+ MTK_PIN(PINCTRL_PIN(126, "DPIG1"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 111),
MTK_FUNCTION(0, "GPIO126"),
@@ -1413,8 +1286,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(2, "EINT111"),
MTK_FUNCTION(5, "DSP1_ICK")
),
- MTK_PIN(
- PINCTRL_PIN(127, "DPIVSYNC"),
+ MTK_PIN(PINCTRL_PIN(127, "DPIVSYNC"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 98),
MTK_FUNCTION(0, "GPIO127"),
@@ -1424,8 +1296,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "DAC_CK"),
MTK_FUNCTION(5, "PCM1_CK")
),
- MTK_PIN(
- PINCTRL_PIN(128, "DPIHSYNC"),
+ MTK_PIN(PINCTRL_PIN(128, "DPIHSYNC"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 99),
MTK_FUNCTION(0, "GPIO128"),
@@ -1436,8 +1307,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "PCM1_WS"),
MTK_FUNCTION(6, "IRDA_RXD")
),
- MTK_PIN(
- PINCTRL_PIN(129, "DPIB0"),
+ MTK_PIN(PINCTRL_PIN(129, "DPIB0"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 102),
MTK_FUNCTION(0, "GPIO129"),
@@ -1446,8 +1316,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "SCL0"),
MTK_FUNCTION(5, "DISP_PWM")
),
- MTK_PIN(
- PINCTRL_PIN(130, "DPIB1"),
+ MTK_PIN(PINCTRL_PIN(130, "DPIB1"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 103),
MTK_FUNCTION(0, "GPIO130"),
@@ -1457,8 +1326,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "SDA0"),
MTK_FUNCTION(5, "PWM1")
),
- MTK_PIN(
- PINCTRL_PIN(131, "DPIB2"),
+ MTK_PIN(PINCTRL_PIN(131, "DPIB2"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 104),
MTK_FUNCTION(0, "GPIO131"),
@@ -1468,8 +1336,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "SCL1"),
MTK_FUNCTION(5, "PWM2")
),
- MTK_PIN(
- PINCTRL_PIN(132, "DPIB3"),
+ MTK_PIN(PINCTRL_PIN(132, "DPIB3"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 105),
MTK_FUNCTION(0, "GPIO132"),
@@ -1479,8 +1346,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "SDA1"),
MTK_FUNCTION(5, "PWM3")
),
- MTK_PIN(
- PINCTRL_PIN(133, "DPIB4"),
+ MTK_PIN(PINCTRL_PIN(133, "DPIB4"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 106),
MTK_FUNCTION(0, "GPIO133"),
@@ -1490,8 +1356,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "SCL2"),
MTK_FUNCTION(5, "PWM4")
),
- MTK_PIN(
- PINCTRL_PIN(134, "DPIB5"),
+ MTK_PIN(PINCTRL_PIN(134, "DPIB5"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 107),
MTK_FUNCTION(0, "GPIO134"),
@@ -1501,8 +1366,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "SDA2"),
MTK_FUNCTION(5, "PWM5")
),
- MTK_PIN(
- PINCTRL_PIN(135, "DPIB6"),
+ MTK_PIN(PINCTRL_PIN(135, "DPIB6"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 108),
MTK_FUNCTION(0, "GPIO135"),
@@ -1512,8 +1376,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "SCL3"),
MTK_FUNCTION(5, "PWM6")
),
- MTK_PIN(
- PINCTRL_PIN(136, "DPIB7"),
+ MTK_PIN(PINCTRL_PIN(136, "DPIB7"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 109),
MTK_FUNCTION(0, "GPIO136"),
@@ -1523,8 +1386,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "SDA3"),
MTK_FUNCTION(5, "PWM7")
),
- MTK_PIN(
- PINCTRL_PIN(137, "DPIG0"),
+ MTK_PIN(PINCTRL_PIN(137, "DPIG0"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 110),
MTK_FUNCTION(0, "GPIO137"),
@@ -1532,8 +1394,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(2, "EINT110"),
MTK_FUNCTION(5, "DSP1_ID")
),
- MTK_PIN(
- PINCTRL_PIN(138, "DPIG2"),
+ MTK_PIN(PINCTRL_PIN(138, "DPIG2"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 112),
MTK_FUNCTION(0, "GPIO138"),
@@ -1541,8 +1402,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(2, "EINT112"),
MTK_FUNCTION(5, "DSP1_IMS")
),
- MTK_PIN(
- PINCTRL_PIN(139, "DPIG3"),
+ MTK_PIN(PINCTRL_PIN(139, "DPIG3"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 113),
MTK_FUNCTION(0, "GPIO139"),
@@ -1550,8 +1410,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(2, "EINT113"),
MTK_FUNCTION(5, "DSP2_IMS")
),
- MTK_PIN(
- PINCTRL_PIN(140, "DPIG6"),
+ MTK_PIN(PINCTRL_PIN(140, "DPIG6"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 116),
MTK_FUNCTION(0, "GPIO140"),
@@ -1559,8 +1418,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(2, "EINT116"),
MTK_FUNCTION(4, "CM2DAT_2X[2]")
),
- MTK_PIN(
- PINCTRL_PIN(141, "DPIG7"),
+ MTK_PIN(PINCTRL_PIN(141, "DPIG7"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 117),
MTK_FUNCTION(0, "GPIO141"),
@@ -1568,8 +1426,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(2, "EINT117"),
MTK_FUNCTION(4, "CM2DAT_2X[3]")
),
- MTK_PIN(
- PINCTRL_PIN(142, "DPIR0"),
+ MTK_PIN(PINCTRL_PIN(142, "DPIR0"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 118),
MTK_FUNCTION(0, "GPIO142"),
@@ -1577,8 +1434,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(2, "EINT118"),
MTK_FUNCTION(4, "CM2DAT_2X[4]")
),
- MTK_PIN(
- PINCTRL_PIN(143, "DPIR1"),
+ MTK_PIN(PINCTRL_PIN(143, "DPIR1"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 119),
MTK_FUNCTION(0, "GPIO143"),
@@ -1586,8 +1442,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(2, "EINT119"),
MTK_FUNCTION(4, "CM2DAT_2X[5]")
),
- MTK_PIN(
- PINCTRL_PIN(144, "DPIR2"),
+ MTK_PIN(PINCTRL_PIN(144, "DPIR2"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 120),
MTK_FUNCTION(0, "GPIO144"),
@@ -1595,8 +1450,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(2, "EINT120"),
MTK_FUNCTION(4, "CM2DAT_2X[6]")
),
- MTK_PIN(
- PINCTRL_PIN(145, "DPIR4"),
+ MTK_PIN(PINCTRL_PIN(145, "DPIR4"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 122),
MTK_FUNCTION(0, "GPIO145"),
@@ -1604,8 +1458,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(2, "EINT122"),
MTK_FUNCTION(4, "CM2DAT_2X[8]")
),
- MTK_PIN(
- PINCTRL_PIN(146, "DPIR5"),
+ MTK_PIN(PINCTRL_PIN(146, "DPIR5"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 123),
MTK_FUNCTION(0, "GPIO146"),
@@ -1613,8 +1466,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(2, "EINT123"),
MTK_FUNCTION(4, "CM2DAT_2X[9]")
),
- MTK_PIN(
- PINCTRL_PIN(147, "DPIR6"),
+ MTK_PIN(PINCTRL_PIN(147, "DPIR6"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 124),
MTK_FUNCTION(0, "GPIO147"),
@@ -1622,8 +1474,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(2, "EINT124"),
MTK_FUNCTION(4, "CM2VSYNC_2X")
),
- MTK_PIN(
- PINCTRL_PIN(148, "DPIR7"),
+ MTK_PIN(PINCTRL_PIN(148, "DPIR7"),
NULL, "mt8135",
MTK_EINT_FUNCTION(2, 125),
MTK_FUNCTION(0, "GPIO148"),
@@ -1631,192 +1482,165 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(2, "EINT125"),
MTK_FUNCTION(4, "CM2HSYNC_2X")
),
- MTK_PIN(
- PINCTRL_PIN(149, "TDN3/LVDS(TDN3)"),
+ MTK_PIN(PINCTRL_PIN(149, "TDN3/LVDS(TDN3)"),
"AA2", "mt8135",
MTK_EINT_FUNCTION(2, 36),
MTK_FUNCTION(0, "GPIO149"),
MTK_FUNCTION(2, "EINT36")
),
- MTK_PIN(
- PINCTRL_PIN(150, "TDP3/LVDS(TDP3)"),
+ MTK_PIN(PINCTRL_PIN(150, "TDP3/LVDS(TDP3)"),
"AA1", "mt8135",
MTK_EINT_FUNCTION(2, 35),
MTK_FUNCTION(0, "GPIO150"),
MTK_FUNCTION(2, "EINT35")
),
- MTK_PIN(
- PINCTRL_PIN(151, "TDN2/LVDS(TCN)"),
+ MTK_PIN(PINCTRL_PIN(151, "TDN2/LVDS(TCN)"),
"Y2", "mt8135",
MTK_EINT_FUNCTION(2, 169),
MTK_FUNCTION(0, "GPIO151"),
MTK_FUNCTION(2, "EINT169")
),
- MTK_PIN(
- PINCTRL_PIN(152, "TDP2/LVDS(TCP)"),
+ MTK_PIN(PINCTRL_PIN(152, "TDP2/LVDS(TCP)"),
"Y1", "mt8135",
MTK_EINT_FUNCTION(2, 168),
MTK_FUNCTION(0, "GPIO152"),
MTK_FUNCTION(2, "EINT168")
),
- MTK_PIN(
- PINCTRL_PIN(153, "TCN/LVDS(TDN2)"),
+ MTK_PIN(PINCTRL_PIN(153, "TCN/LVDS(TDN2)"),
"W2", "mt8135",
MTK_EINT_FUNCTION(2, 163),
MTK_FUNCTION(0, "GPIO153"),
MTK_FUNCTION(2, "EINT163")
),
- MTK_PIN(
- PINCTRL_PIN(154, "TCP/LVDS(TDP2)"),
+ MTK_PIN(PINCTRL_PIN(154, "TCP/LVDS(TDP2)"),
"W1", "mt8135",
MTK_EINT_FUNCTION(2, 162),
MTK_FUNCTION(0, "GPIO154"),
MTK_FUNCTION(2, "EINT162")
),
- MTK_PIN(
- PINCTRL_PIN(155, "TDN1/LVDS(TDN1)"),
+ MTK_PIN(PINCTRL_PIN(155, "TDN1/LVDS(TDN1)"),
"V3", "mt8135",
MTK_EINT_FUNCTION(2, 167),
MTK_FUNCTION(0, "GPIO155"),
MTK_FUNCTION(2, "EINT167")
),
- MTK_PIN(
- PINCTRL_PIN(156, "TDP1/LVDS(TDP1)"),
+ MTK_PIN(PINCTRL_PIN(156, "TDP1/LVDS(TDP1)"),
"V2", "mt8135",
MTK_EINT_FUNCTION(2, 166),
MTK_FUNCTION(0, "GPIO156"),
MTK_FUNCTION(2, "EINT166")
),
- MTK_PIN(
- PINCTRL_PIN(157, "TDN0/LVDS(TDN0)"),
+ MTK_PIN(PINCTRL_PIN(157, "TDN0/LVDS(TDN0)"),
"U3", "mt8135",
MTK_EINT_FUNCTION(2, 165),
MTK_FUNCTION(0, "GPIO157"),
MTK_FUNCTION(2, "EINT165")
),
- MTK_PIN(
- PINCTRL_PIN(158, "TDP0/LVDS(TDP0)"),
+ MTK_PIN(PINCTRL_PIN(158, "TDP0/LVDS(TDP0)"),
"U2", "mt8135",
MTK_EINT_FUNCTION(2, 164),
MTK_FUNCTION(0, "GPIO158"),
MTK_FUNCTION(2, "EINT164")
),
- MTK_PIN(
- PINCTRL_PIN(159, "RDN3"),
+ MTK_PIN(PINCTRL_PIN(159, "RDN3"),
"N5", "mt8135",
MTK_EINT_FUNCTION(2, 18),
MTK_FUNCTION(0, "GPIO159"),
MTK_FUNCTION(2, "EINT18")
),
- MTK_PIN(
- PINCTRL_PIN(160, "RDP3"),
+ MTK_PIN(PINCTRL_PIN(160, "RDP3"),
"N4", "mt8135",
MTK_EINT_FUNCTION(2, 30),
MTK_FUNCTION(0, "GPIO160"),
MTK_FUNCTION(2, "EINT30")
),
- MTK_PIN(
- PINCTRL_PIN(161, "RDN2"),
+ MTK_PIN(PINCTRL_PIN(161, "RDN2"),
"T2", "mt8135",
MTK_EINT_FUNCTION(2, 31),
MTK_FUNCTION(0, "GPIO161"),
MTK_FUNCTION(2, "EINT31")
),
- MTK_PIN(
- PINCTRL_PIN(162, "RDP2"),
+ MTK_PIN(PINCTRL_PIN(162, "RDP2"),
"T3", "mt8135",
MTK_EINT_FUNCTION(2, 32),
MTK_FUNCTION(0, "GPIO162"),
MTK_FUNCTION(2, "EINT32")
),
- MTK_PIN(
- PINCTRL_PIN(163, "RCN"),
+ MTK_PIN(PINCTRL_PIN(163, "RCN"),
"P2", "mt8135",
MTK_EINT_FUNCTION(2, 33),
MTK_FUNCTION(0, "GPIO163"),
MTK_FUNCTION(2, "EINT33")
),
- MTK_PIN(
- PINCTRL_PIN(164, "RCP"),
+ MTK_PIN(PINCTRL_PIN(164, "RCP"),
"P3", "mt8135",
MTK_EINT_FUNCTION(2, 39),
MTK_FUNCTION(0, "GPIO164"),
MTK_FUNCTION(2, "EINT39")
),
- MTK_PIN(
- PINCTRL_PIN(165, "RDN1"),
+ MTK_PIN(PINCTRL_PIN(165, "RDN1"),
"R3", "mt8135",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO165")
),
- MTK_PIN(
- PINCTRL_PIN(166, "RDP1"),
+ MTK_PIN(PINCTRL_PIN(166, "RDP1"),
"R2", "mt8135",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO166")
),
- MTK_PIN(
- PINCTRL_PIN(167, "RDN0"),
+ MTK_PIN(PINCTRL_PIN(167, "RDN0"),
"N3", "mt8135",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO167")
),
- MTK_PIN(
- PINCTRL_PIN(168, "RDP0"),
+ MTK_PIN(PINCTRL_PIN(168, "RDP0"),
"N2", "mt8135",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO168")
),
- MTK_PIN(
- PINCTRL_PIN(169, "RDN1_A"),
+ MTK_PIN(PINCTRL_PIN(169, "RDN1_A"),
"M4", "mt8135",
MTK_EINT_FUNCTION(2, 175),
MTK_FUNCTION(0, "GPIO169"),
MTK_FUNCTION(1, "CMDAT6"),
MTK_FUNCTION(2, "EINT175")
),
- MTK_PIN(
- PINCTRL_PIN(170, "RDP1_A"),
+ MTK_PIN(PINCTRL_PIN(170, "RDP1_A"),
"M3", "mt8135",
MTK_EINT_FUNCTION(2, 174),
MTK_FUNCTION(0, "GPIO170"),
MTK_FUNCTION(1, "CMDAT7"),
MTK_FUNCTION(2, "EINT174")
),
- MTK_PIN(
- PINCTRL_PIN(171, "RCN_A"),
+ MTK_PIN(PINCTRL_PIN(171, "RCN_A"),
"L3", "mt8135",
MTK_EINT_FUNCTION(2, 171),
MTK_FUNCTION(0, "GPIO171"),
MTK_FUNCTION(1, "CMDAT8"),
MTK_FUNCTION(2, "EINT171")
),
- MTK_PIN(
- PINCTRL_PIN(172, "RCP_A"),
+ MTK_PIN(PINCTRL_PIN(172, "RCP_A"),
"L2", "mt8135",
MTK_EINT_FUNCTION(2, 170),
MTK_FUNCTION(0, "GPIO172"),
MTK_FUNCTION(1, "CMDAT9"),
MTK_FUNCTION(2, "EINT170")
),
- MTK_PIN(
- PINCTRL_PIN(173, "RDN0_A"),
+ MTK_PIN(PINCTRL_PIN(173, "RDN0_A"),
"M2", "mt8135",
MTK_EINT_FUNCTION(2, 173),
MTK_FUNCTION(0, "GPIO173"),
MTK_FUNCTION(1, "CMHSYNC"),
MTK_FUNCTION(2, "EINT173")
),
- MTK_PIN(
- PINCTRL_PIN(174, "RDP0_A"),
+ MTK_PIN(PINCTRL_PIN(174, "RDP0_A"),
"M1", "mt8135",
MTK_EINT_FUNCTION(2, 172),
MTK_FUNCTION(0, "GPIO174"),
MTK_FUNCTION(1, "CMVSYNC"),
MTK_FUNCTION(2, "EINT172")
),
- MTK_PIN(
- PINCTRL_PIN(175, "RDN1_B"),
+ MTK_PIN(PINCTRL_PIN(175, "RDN1_B"),
"H2", "mt8135",
MTK_EINT_FUNCTION(2, 181),
MTK_FUNCTION(0, "GPIO175"),
@@ -1824,8 +1648,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(2, "EINT181"),
MTK_FUNCTION(3, "CMCSD2")
),
- MTK_PIN(
- PINCTRL_PIN(176, "RDP1_B"),
+ MTK_PIN(PINCTRL_PIN(176, "RDP1_B"),
"H1", "mt8135",
MTK_EINT_FUNCTION(2, 180),
MTK_FUNCTION(0, "GPIO176"),
@@ -1833,24 +1656,21 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(2, "EINT180"),
MTK_FUNCTION(3, "CMCSD3")
),
- MTK_PIN(
- PINCTRL_PIN(177, "RCN_B"),
+ MTK_PIN(PINCTRL_PIN(177, "RCN_B"),
"K3", "mt8135",
MTK_EINT_FUNCTION(2, 177),
MTK_FUNCTION(0, "GPIO177"),
MTK_FUNCTION(1, "CMDAT4"),
MTK_FUNCTION(2, "EINT177")
),
- MTK_PIN(
- PINCTRL_PIN(178, "RCP_B"),
+ MTK_PIN(PINCTRL_PIN(178, "RCP_B"),
"K2", "mt8135",
MTK_EINT_FUNCTION(2, 176),
MTK_FUNCTION(0, "GPIO178"),
MTK_FUNCTION(1, "CMDAT5"),
MTK_FUNCTION(2, "EINT176")
),
- MTK_PIN(
- PINCTRL_PIN(179, "RDN0_B"),
+ MTK_PIN(PINCTRL_PIN(179, "RDN0_B"),
"J3", "mt8135",
MTK_EINT_FUNCTION(2, 179),
MTK_FUNCTION(0, "GPIO179"),
@@ -1858,8 +1678,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(2, "EINT179"),
MTK_FUNCTION(3, "CMCSD0")
),
- MTK_PIN(
- PINCTRL_PIN(180, "RDP0_B"),
+ MTK_PIN(PINCTRL_PIN(180, "RDP0_B"),
"J2", "mt8135",
MTK_EINT_FUNCTION(2, 178),
MTK_FUNCTION(0, "GPIO180"),
@@ -1867,8 +1686,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(2, "EINT178"),
MTK_FUNCTION(3, "CMCSD1")
),
- MTK_PIN(
- PINCTRL_PIN(181, "CMPCLK"),
+ MTK_PIN(PINCTRL_PIN(181, "CMPCLK"),
"K4", "mt8135",
MTK_EINT_FUNCTION(2, 182),
MTK_FUNCTION(0, "GPIO181"),
@@ -1880,8 +1698,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "VENC_TEST_CK"),
MTK_FUNCTION(7, "TESTA_OUT27")
),
- MTK_PIN(
- PINCTRL_PIN(182, "CMMCLK"),
+ MTK_PIN(PINCTRL_PIN(182, "CMMCLK"),
"J5", "mt8135",
MTK_EINT_FUNCTION(2, 183),
MTK_FUNCTION(0, "GPIO182"),
@@ -1890,8 +1707,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "TS_AUXADC_SEL[2]"),
MTK_FUNCTION(7, "TESTA_OUT28")
),
- MTK_PIN(
- PINCTRL_PIN(183, "CMRST"),
+ MTK_PIN(PINCTRL_PIN(183, "CMRST"),
"J6", "mt8135",
MTK_EINT_FUNCTION(2, 185),
MTK_FUNCTION(0, "GPIO183"),
@@ -1900,8 +1716,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "TS_AUXADC_SEL[1]"),
MTK_FUNCTION(7, "TESTA_OUT30")
),
- MTK_PIN(
- PINCTRL_PIN(184, "CMPDN"),
+ MTK_PIN(PINCTRL_PIN(184, "CMPDN"),
"J4", "mt8135",
MTK_EINT_FUNCTION(2, 184),
MTK_FUNCTION(0, "GPIO184"),
@@ -1910,8 +1725,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "TS_AUXADC_SEL[0]"),
MTK_FUNCTION(7, "TESTA_OUT29")
),
- MTK_PIN(
- PINCTRL_PIN(185, "CMFLASH"),
+ MTK_PIN(PINCTRL_PIN(185, "CMFLASH"),
"G4", "mt8135",
MTK_EINT_FUNCTION(2, 186),
MTK_FUNCTION(0, "GPIO185"),
@@ -1921,8 +1735,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "MFG_TEST_CK_1"),
MTK_FUNCTION(7, "TESTA_OUT31")
),
- MTK_PIN(
- PINCTRL_PIN(186, "MRG_I2S_PCM_CLK"),
+ MTK_PIN(PINCTRL_PIN(186, "MRG_I2S_PCM_CLK"),
"F5", "mt8135",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO186"),
@@ -1933,8 +1746,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "IMG_TEST_CK"),
MTK_FUNCTION(7, "USB_SCL")
),
- MTK_PIN(
- PINCTRL_PIN(187, "MRG_I2S_PCM_SYNC"),
+ MTK_PIN(PINCTRL_PIN(187, "MRG_I2S_PCM_SYNC"),
"G6", "mt8135",
MTK_EINT_FUNCTION(2, 16),
MTK_FUNCTION(0, "GPIO187"),
@@ -1944,8 +1756,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "PCM0_WS"),
MTK_FUNCTION(6, "DISP_TEST_CK")
),
- MTK_PIN(
- PINCTRL_PIN(188, "MRG_I2S_PCM_RX"),
+ MTK_PIN(PINCTRL_PIN(188, "MRG_I2S_PCM_RX"),
"G3", "mt8135",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO188"),
@@ -1956,8 +1767,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(6, "MFG_TEST_CK"),
MTK_FUNCTION(7, "USB_SDA")
),
- MTK_PIN(
- PINCTRL_PIN(189, "MRG_I2S_PCM_TX"),
+ MTK_PIN(PINCTRL_PIN(189, "MRG_I2S_PCM_TX"),
"G5", "mt8135",
MTK_EINT_FUNCTION(2, 17),
MTK_FUNCTION(0, "GPIO189"),
@@ -1967,15 +1777,13 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "PCM0_DO"),
MTK_FUNCTION(6, "VDEC_TEST_CK")
),
- MTK_PIN(
- PINCTRL_PIN(190, "SRCLKENAI"),
+ MTK_PIN(PINCTRL_PIN(190, "SRCLKENAI"),
"K5", "mt8135",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO190"),
MTK_FUNCTION(1, "SRCLKENAI")
),
- MTK_PIN(
- PINCTRL_PIN(191, "URXD3"),
+ MTK_PIN(PINCTRL_PIN(191, "URXD3"),
"C3", "mt8135",
MTK_EINT_FUNCTION(2, 87),
MTK_FUNCTION(0, "GPIO191"),
@@ -1985,8 +1793,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "TS_AUX_ST"),
MTK_FUNCTION(6, "PWM4")
),
- MTK_PIN(
- PINCTRL_PIN(192, "UTXD3"),
+ MTK_PIN(PINCTRL_PIN(192, "UTXD3"),
"B2", "mt8135",
MTK_EINT_FUNCTION(2, 86),
MTK_FUNCTION(0, "GPIO192"),
@@ -1996,8 +1803,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "TS_AUX_CS_B"),
MTK_FUNCTION(6, "PWM3")
),
- MTK_PIN(
- PINCTRL_PIN(193, "SDA2"),
+ MTK_PIN(PINCTRL_PIN(193, "SDA2"),
"G2", "mt8135",
MTK_EINT_FUNCTION(2, 95),
MTK_FUNCTION(0, "GPIO193"),
@@ -2007,8 +1813,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "PWM5"),
MTK_FUNCTION(5, "TS_AUX_PWDB")
),
- MTK_PIN(
- PINCTRL_PIN(194, "SCL2"),
+ MTK_PIN(PINCTRL_PIN(194, "SCL2"),
"F4", "mt8135",
MTK_EINT_FUNCTION(2, 94),
MTK_FUNCTION(0, "GPIO194"),
@@ -2018,8 +1823,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "PWM4"),
MTK_FUNCTION(5, "TS_AUXADC_TEST_CK")
),
- MTK_PIN(
- PINCTRL_PIN(195, "SDA1"),
+ MTK_PIN(PINCTRL_PIN(195, "SDA1"),
"F2", "mt8135",
MTK_EINT_FUNCTION(2, 93),
MTK_FUNCTION(0, "GPIO195"),
@@ -2029,8 +1833,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "PWM3"),
MTK_FUNCTION(5, "TS_AUX_SCLK_PWDB")
),
- MTK_PIN(
- PINCTRL_PIN(196, "SCL1"),
+ MTK_PIN(PINCTRL_PIN(196, "SCL1"),
"F3", "mt8135",
MTK_EINT_FUNCTION(2, 92),
MTK_FUNCTION(0, "GPIO196"),
@@ -2040,8 +1843,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "PWM2"),
MTK_FUNCTION(5, "TS_AUX_DIN")
),
- MTK_PIN(
- PINCTRL_PIN(197, "MSDC3_DAT2"),
+ MTK_PIN(PINCTRL_PIN(197, "MSDC3_DAT2"),
"E1", "mt8135",
MTK_EINT_FUNCTION(2, 71),
MTK_FUNCTION(0, "GPIO197"),
@@ -2052,8 +1854,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "CLKM4"),
MTK_FUNCTION(6, "MFG_TEST_CK_2")
),
- MTK_PIN(
- PINCTRL_PIN(198, "MSDC3_DAT3"),
+ MTK_PIN(PINCTRL_PIN(198, "MSDC3_DAT3"),
"C2", "mt8135",
MTK_EINT_FUNCTION(2, 72),
MTK_FUNCTION(0, "GPIO198"),
@@ -2064,8 +1865,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "CLKM5"),
MTK_FUNCTION(6, "MFG_TEST_CK_3")
),
- MTK_PIN(
- PINCTRL_PIN(199, "MSDC3_CMD"),
+ MTK_PIN(PINCTRL_PIN(199, "MSDC3_CMD"),
"D2", "mt8135",
MTK_EINT_FUNCTION(2, 68),
MTK_FUNCTION(0, "GPIO199"),
@@ -2076,8 +1876,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(5, "CLKM1"),
MTK_FUNCTION(6, "MFG_TEST_CK_4")
),
- MTK_PIN(
- PINCTRL_PIN(200, "MSDC3_CLK"),
+ MTK_PIN(PINCTRL_PIN(200, "MSDC3_CLK"),
"E2", "mt8135",
MTK_EINT_FUNCTION(2, 67),
MTK_FUNCTION(0, "GPIO200"),
@@ -2087,8 +1886,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "PWM1"),
MTK_FUNCTION(5, "CLKM0")
),
- MTK_PIN(
- PINCTRL_PIN(201, "MSDC3_DAT1"),
+ MTK_PIN(PINCTRL_PIN(201, "MSDC3_DAT1"),
"D3", "mt8135",
MTK_EINT_FUNCTION(2, 70),
MTK_FUNCTION(0, "GPIO201"),
@@ -2098,8 +1896,7 @@ static const struct mtk_desc_pin mtk_pins_mt8135[] = {
MTK_FUNCTION(4, "PWM4"),
MTK_FUNCTION(5, "CLKM3")
),
- MTK_PIN(
- PINCTRL_PIN(202, "MSDC3_DAT0"),
+ MTK_PIN(PINCTRL_PIN(202, "MSDC3_DAT0"),
"E3", "mt8135",
MTK_EINT_FUNCTION(2, 69),
MTK_FUNCTION(0, "GPIO202"),
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8173.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8173.h
index 9b018fdbeb51..8bd0c10753f5 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8173.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8173.h
@@ -19,8 +19,7 @@
#include "pinctrl-mtk-common.h"
static const struct mtk_desc_pin mtk_pins_mt8173[] = {
- MTK_PIN(
- PINCTRL_PIN(0, "EINT0"),
+ MTK_PIN(PINCTRL_PIN(0, "EINT0"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 0),
MTK_FUNCTION(0, "GPIO0"),
@@ -30,8 +29,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(4, "UTXD0"),
MTK_FUNCTION(7, "DBG_MON_A_20_")
),
- MTK_PIN(
- PINCTRL_PIN(1, "EINT1"),
+ MTK_PIN(PINCTRL_PIN(1, "EINT1"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 1),
MTK_FUNCTION(0, "GPIO1"),
@@ -41,8 +39,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(4, "URXD0"),
MTK_FUNCTION(7, "DBG_MON_A_21_")
),
- MTK_PIN(
- PINCTRL_PIN(2, "EINT2"),
+ MTK_PIN(PINCTRL_PIN(2, "EINT2"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 2),
MTK_FUNCTION(0, "GPIO2"),
@@ -52,8 +49,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(4, "UTXD3"),
MTK_FUNCTION(7, "DBG_MON_A_22_")
),
- MTK_PIN(
- PINCTRL_PIN(3, "EINT3"),
+ MTK_PIN(PINCTRL_PIN(3, "EINT3"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 3),
MTK_FUNCTION(0, "GPIO3"),
@@ -63,8 +59,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(4, "URXD3"),
MTK_FUNCTION(7, "DBG_MON_A_23_")
),
- MTK_PIN(
- PINCTRL_PIN(4, "EINT4"),
+ MTK_PIN(PINCTRL_PIN(4, "EINT4"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 4),
MTK_FUNCTION(0, "GPIO4"),
@@ -74,8 +69,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(4, "UCTS3"),
MTK_FUNCTION(6, "SFWP_B")
),
- MTK_PIN(
- PINCTRL_PIN(5, "EINT5"),
+ MTK_PIN(PINCTRL_PIN(5, "EINT5"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 5),
MTK_FUNCTION(0, "GPIO5"),
@@ -86,8 +80,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(5, "AP_MD32_JTAG_TMS"),
MTK_FUNCTION(6, "SFOUT")
),
- MTK_PIN(
- PINCTRL_PIN(6, "EINT6"),
+ MTK_PIN(PINCTRL_PIN(6, "EINT6"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 6),
MTK_FUNCTION(0, "GPIO6"),
@@ -97,8 +90,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(5, "AP_MD32_JTAG_TCK"),
MTK_FUNCTION(6, "SFCS0")
),
- MTK_PIN(
- PINCTRL_PIN(7, "EINT7"),
+ MTK_PIN(PINCTRL_PIN(7, "EINT7"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 7),
MTK_FUNCTION(0, "GPIO7"),
@@ -108,8 +100,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(5, "AP_MD32_JTAG_TDI"),
MTK_FUNCTION(6, "SFHOLD")
),
- MTK_PIN(
- PINCTRL_PIN(8, "EINT8"),
+ MTK_PIN(PINCTRL_PIN(8, "EINT8"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 8),
MTK_FUNCTION(0, "GPIO8"),
@@ -120,8 +111,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(5, "AP_MD32_JTAG_TDO"),
MTK_FUNCTION(6, "SFIN")
),
- MTK_PIN(
- PINCTRL_PIN(9, "EINT9"),
+ MTK_PIN(PINCTRL_PIN(9, "EINT9"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 9),
MTK_FUNCTION(0, "GPIO9"),
@@ -131,8 +121,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(5, "AP_MD32_JTAG_TRST"),
MTK_FUNCTION(6, "SFCK")
),
- MTK_PIN(
- PINCTRL_PIN(10, "EINT10"),
+ MTK_PIN(PINCTRL_PIN(10, "EINT10"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 10),
MTK_FUNCTION(0, "GPIO10"),
@@ -142,8 +131,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(4, "PWM4"),
MTK_FUNCTION(5, "IRDA_RXD")
),
- MTK_PIN(
- PINCTRL_PIN(11, "EINT11"),
+ MTK_PIN(PINCTRL_PIN(11, "EINT11"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 11),
MTK_FUNCTION(0, "GPIO11"),
@@ -155,8 +143,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(6, "USB_DRVVBUS_P1"),
MTK_FUNCTION(7, "DBG_MON_B_30_")
),
- MTK_PIN(
- PINCTRL_PIN(12, "EINT12"),
+ MTK_PIN(PINCTRL_PIN(12, "EINT12"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 12),
MTK_FUNCTION(0, "GPIO12"),
@@ -166,8 +153,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(5, "I2S2_WS"),
MTK_FUNCTION(7, "DBG_MON_B_32_")
),
- MTK_PIN(
- PINCTRL_PIN(13, "EINT13"),
+ MTK_PIN(PINCTRL_PIN(13, "EINT13"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 13),
MTK_FUNCTION(0, "GPIO13"),
@@ -177,8 +163,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(5, "I2S2_BCK"),
MTK_FUNCTION(7, "DBG_MON_A_32_")
),
- MTK_PIN(
- PINCTRL_PIN(14, "EINT14"),
+ MTK_PIN(PINCTRL_PIN(14, "EINT14"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 14),
MTK_FUNCTION(0, "GPIO14"),
@@ -187,8 +172,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(4, "CLKM2"),
MTK_FUNCTION(7, "DBG_MON_B_6_")
),
- MTK_PIN(
- PINCTRL_PIN(15, "EINT15"),
+ MTK_PIN(PINCTRL_PIN(15, "EINT15"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 15),
MTK_FUNCTION(0, "GPIO15"),
@@ -198,8 +182,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(4, "CLKM3"),
MTK_FUNCTION(7, "DBG_MON_B_29_")
),
- MTK_PIN(
- PINCTRL_PIN(16, "IDDIG"),
+ MTK_PIN(PINCTRL_PIN(16, "IDDIG"),
NULL, "mt8173",
MTK_EINT_FUNCTION(1, 16),
MTK_FUNCTION(0, "GPIO16"),
@@ -207,156 +190,135 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(2, "CMFLASH"),
MTK_FUNCTION(4, "PWM5")
),
- MTK_PIN(
- PINCTRL_PIN(17, "WATCHDOG"),
+ MTK_PIN(PINCTRL_PIN(17, "WATCHDOG"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 17),
MTK_FUNCTION(0, "GPIO17"),
MTK_FUNCTION(1, "WATCHDOG_AO")
),
- MTK_PIN(
- PINCTRL_PIN(18, "CEC"),
+ MTK_PIN(PINCTRL_PIN(18, "CEC"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 18),
MTK_FUNCTION(0, "GPIO18"),
MTK_FUNCTION(1, "CEC")
),
- MTK_PIN(
- PINCTRL_PIN(19, "HDMISCK"),
+ MTK_PIN(PINCTRL_PIN(19, "HDMISCK"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 19),
MTK_FUNCTION(0, "GPIO19"),
MTK_FUNCTION(1, "HDMISCK"),
MTK_FUNCTION(2, "HDCP_SCL")
),
- MTK_PIN(
- PINCTRL_PIN(20, "HDMISD"),
+ MTK_PIN(PINCTRL_PIN(20, "HDMISD"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 20),
MTK_FUNCTION(0, "GPIO20"),
MTK_FUNCTION(1, "HDMISD"),
MTK_FUNCTION(2, "HDCP_SDA")
),
- MTK_PIN(
- PINCTRL_PIN(21, "HTPLG"),
+ MTK_PIN(PINCTRL_PIN(21, "HTPLG"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 21),
MTK_FUNCTION(0, "GPIO21"),
MTK_FUNCTION(1, "HTPLG")
),
- MTK_PIN(
- PINCTRL_PIN(22, "MSDC3_DAT0"),
+ MTK_PIN(PINCTRL_PIN(22, "MSDC3_DAT0"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 22),
MTK_FUNCTION(0, "GPIO22"),
MTK_FUNCTION(1, "MSDC3_DAT0")
),
- MTK_PIN(
- PINCTRL_PIN(23, "MSDC3_DAT1"),
+ MTK_PIN(PINCTRL_PIN(23, "MSDC3_DAT1"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 23),
MTK_FUNCTION(0, "GPIO23"),
MTK_FUNCTION(1, "MSDC3_DAT1")
),
- MTK_PIN(
- PINCTRL_PIN(24, "MSDC3_DAT2"),
+ MTK_PIN(PINCTRL_PIN(24, "MSDC3_DAT2"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 24),
MTK_FUNCTION(0, "GPIO24"),
MTK_FUNCTION(1, "MSDC3_DAT2")
),
- MTK_PIN(
- PINCTRL_PIN(25, "MSDC3_DAT3"),
+ MTK_PIN(PINCTRL_PIN(25, "MSDC3_DAT3"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 25),
MTK_FUNCTION(0, "GPIO25"),
MTK_FUNCTION(1, "MSDC3_DAT3")
),
- MTK_PIN(
- PINCTRL_PIN(26, "MSDC3_CLK"),
+ MTK_PIN(PINCTRL_PIN(26, "MSDC3_CLK"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 26),
MTK_FUNCTION(0, "GPIO26"),
MTK_FUNCTION(1, "MSDC3_CLK")
),
- MTK_PIN(
- PINCTRL_PIN(27, "MSDC3_CMD"),
+ MTK_PIN(PINCTRL_PIN(27, "MSDC3_CMD"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 27),
MTK_FUNCTION(0, "GPIO27"),
MTK_FUNCTION(1, "MSDC3_CMD")
),
- MTK_PIN(
- PINCTRL_PIN(28, "MSDC3_DSL"),
+ MTK_PIN(PINCTRL_PIN(28, "MSDC3_DSL"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 28),
MTK_FUNCTION(0, "GPIO28"),
MTK_FUNCTION(1, "MSDC3_DSL")
),
- MTK_PIN(
- PINCTRL_PIN(29, "UCTS2"),
+ MTK_PIN(PINCTRL_PIN(29, "UCTS2"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 29),
MTK_FUNCTION(0, "GPIO29"),
MTK_FUNCTION(1, "UCTS2")
),
- MTK_PIN(
- PINCTRL_PIN(30, "URTS2"),
+ MTK_PIN(PINCTRL_PIN(30, "URTS2"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 30),
MTK_FUNCTION(0, "GPIO30"),
MTK_FUNCTION(1, "URTS2")
),
- MTK_PIN(
- PINCTRL_PIN(31, "URXD2"),
+ MTK_PIN(PINCTRL_PIN(31, "URXD2"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 31),
MTK_FUNCTION(0, "GPIO31"),
MTK_FUNCTION(1, "URXD2"),
MTK_FUNCTION(2, "UTXD2")
),
- MTK_PIN(
- PINCTRL_PIN(32, "UTXD2"),
+ MTK_PIN(PINCTRL_PIN(32, "UTXD2"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 32),
MTK_FUNCTION(0, "GPIO32"),
MTK_FUNCTION(1, "UTXD2"),
MTK_FUNCTION(2, "URXD2")
),
- MTK_PIN(
- PINCTRL_PIN(33, "DAICLK"),
+ MTK_PIN(PINCTRL_PIN(33, "DAICLK"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 33),
MTK_FUNCTION(0, "GPIO33"),
MTK_FUNCTION(1, " MRG_CLK"),
MTK_FUNCTION(2, "PCM0_CLK")
),
- MTK_PIN(
- PINCTRL_PIN(34, "DAIPCMIN"),
+ MTK_PIN(PINCTRL_PIN(34, "DAIPCMIN"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 34),
MTK_FUNCTION(0, "GPIO34"),
MTK_FUNCTION(1, " MRG_DI"),
MTK_FUNCTION(2, "PCM0_DI")
),
- MTK_PIN(
- PINCTRL_PIN(35, "DAIPCMOUT"),
+ MTK_PIN(PINCTRL_PIN(35, "DAIPCMOUT"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 35),
MTK_FUNCTION(0, "GPIO35"),
MTK_FUNCTION(1, " MRG_DO"),
MTK_FUNCTION(2, "PCM0_DO")
),
- MTK_PIN(
- PINCTRL_PIN(36, "DAISYNC"),
+ MTK_PIN(PINCTRL_PIN(36, "DAISYNC"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 36),
MTK_FUNCTION(0, "GPIO36"),
MTK_FUNCTION(1, " MRG_SYNC"),
MTK_FUNCTION(2, "PCM0_SYNC")
),
- MTK_PIN(
- PINCTRL_PIN(37, "EINT16"),
+ MTK_PIN(PINCTRL_PIN(37, "EINT16"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 37),
MTK_FUNCTION(0, "GPIO37"),
@@ -367,8 +329,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(5, "PWM2"),
MTK_FUNCTION(6, "CLKM0")
),
- MTK_PIN(
- PINCTRL_PIN(38, "CONN_RST"),
+ MTK_PIN(PINCTRL_PIN(38, "CONN_RST"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 38),
MTK_FUNCTION(0, "GPIO38"),
@@ -376,8 +337,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(2, "USB_DRVVBUS_P1"),
MTK_FUNCTION(6, "CLKM1")
),
- MTK_PIN(
- PINCTRL_PIN(39, "CM2MCLK"),
+ MTK_PIN(PINCTRL_PIN(39, "CM2MCLK"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 39),
MTK_FUNCTION(0, "GPIO39"),
@@ -385,8 +345,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(2, "CMCSD0"),
MTK_FUNCTION(7, "DBG_MON_A_17_")
),
- MTK_PIN(
- PINCTRL_PIN(40, "CMPCLK"),
+ MTK_PIN(PINCTRL_PIN(40, "CMPCLK"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 40),
MTK_FUNCTION(0, "GPIO40"),
@@ -395,125 +354,108 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(3, "CMCSD2"),
MTK_FUNCTION(7, "DBG_MON_A_18_")
),
- MTK_PIN(
- PINCTRL_PIN(41, "CMMCLK"),
+ MTK_PIN(PINCTRL_PIN(41, "CMMCLK"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 41),
MTK_FUNCTION(0, "GPIO41"),
MTK_FUNCTION(1, "CMMCLK"),
MTK_FUNCTION(7, "DBG_MON_A_19_")
),
- MTK_PIN(
- PINCTRL_PIN(42, "DSI_TE"),
+ MTK_PIN(PINCTRL_PIN(42, "DSI_TE"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 42),
MTK_FUNCTION(0, "GPIO42"),
MTK_FUNCTION(1, "DSI_TE")
),
- MTK_PIN(
- PINCTRL_PIN(43, "SDA2"),
+ MTK_PIN(PINCTRL_PIN(43, "SDA2"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 43),
MTK_FUNCTION(0, "GPIO43"),
MTK_FUNCTION(1, "SDA2")
),
- MTK_PIN(
- PINCTRL_PIN(44, "SCL2"),
+ MTK_PIN(PINCTRL_PIN(44, "SCL2"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 44),
MTK_FUNCTION(0, "GPIO44"),
MTK_FUNCTION(1, "SCL2")
),
- MTK_PIN(
- PINCTRL_PIN(45, "SDA0"),
+ MTK_PIN(PINCTRL_PIN(45, "SDA0"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 45),
MTK_FUNCTION(0, "GPIO45"),
MTK_FUNCTION(1, "SDA0")
),
- MTK_PIN(
- PINCTRL_PIN(46, "SCL0"),
+ MTK_PIN(PINCTRL_PIN(46, "SCL0"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 46),
MTK_FUNCTION(0, "GPIO46"),
MTK_FUNCTION(1, "SCL0")
),
- MTK_PIN(
- PINCTRL_PIN(47, "RDN0_A"),
+ MTK_PIN(PINCTRL_PIN(47, "RDN0_A"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 47),
MTK_FUNCTION(0, "GPIO47"),
MTK_FUNCTION(1, "CMDAT2")
),
- MTK_PIN(
- PINCTRL_PIN(48, "RDP0_A"),
+ MTK_PIN(PINCTRL_PIN(48, "RDP0_A"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 48),
MTK_FUNCTION(0, "GPIO48"),
MTK_FUNCTION(1, "CMDAT3")
),
- MTK_PIN(
- PINCTRL_PIN(49, "RDN1_A"),
+ MTK_PIN(PINCTRL_PIN(49, "RDN1_A"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 49),
MTK_FUNCTION(0, "GPIO49"),
MTK_FUNCTION(1, "CMDAT4")
),
- MTK_PIN(
- PINCTRL_PIN(50, "RDP1_A"),
+ MTK_PIN(PINCTRL_PIN(50, "RDP1_A"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 50),
MTK_FUNCTION(0, "GPIO50"),
MTK_FUNCTION(1, "CMDAT5")
),
- MTK_PIN(
- PINCTRL_PIN(51, "RCN_A"),
+ MTK_PIN(PINCTRL_PIN(51, "RCN_A"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 51),
MTK_FUNCTION(0, "GPIO51"),
MTK_FUNCTION(1, "CMDAT6")
),
- MTK_PIN(
- PINCTRL_PIN(52, "RCP_A"),
+ MTK_PIN(PINCTRL_PIN(52, "RCP_A"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 52),
MTK_FUNCTION(0, "GPIO52"),
MTK_FUNCTION(1, "CMDAT7")
),
- MTK_PIN(
- PINCTRL_PIN(53, "RDN2_A"),
+ MTK_PIN(PINCTRL_PIN(53, "RDN2_A"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 53),
MTK_FUNCTION(0, "GPIO53"),
MTK_FUNCTION(1, "CMDAT8"),
MTK_FUNCTION(2, "CMCSD3")
),
- MTK_PIN(
- PINCTRL_PIN(54, "RDP2_A"),
+ MTK_PIN(PINCTRL_PIN(54, "RDP2_A"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 54),
MTK_FUNCTION(0, "GPIO54"),
MTK_FUNCTION(1, "CMDAT9"),
MTK_FUNCTION(2, "CMCSD2")
),
- MTK_PIN(
- PINCTRL_PIN(55, "RDN3_A"),
+ MTK_PIN(PINCTRL_PIN(55, "RDN3_A"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 55),
MTK_FUNCTION(0, "GPIO55"),
MTK_FUNCTION(1, "CMHSYNC"),
MTK_FUNCTION(2, "CMCSD1")
),
- MTK_PIN(
- PINCTRL_PIN(56, "RDP3_A"),
+ MTK_PIN(PINCTRL_PIN(56, "RDP3_A"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 56),
MTK_FUNCTION(0, "GPIO56"),
MTK_FUNCTION(1, "CMVSYNC"),
MTK_FUNCTION(2, "CMCSD0")
),
- MTK_PIN(
- PINCTRL_PIN(57, "MSDC0_DAT0"),
+ MTK_PIN(PINCTRL_PIN(57, "MSDC0_DAT0"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 57),
MTK_FUNCTION(0, "GPIO57"),
@@ -521,8 +463,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(2, "I2S1_WS"),
MTK_FUNCTION(7, "DBG_MON_B_7_")
),
- MTK_PIN(
- PINCTRL_PIN(58, "MSDC0_DAT1"),
+ MTK_PIN(PINCTRL_PIN(58, "MSDC0_DAT1"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 58),
MTK_FUNCTION(0, "GPIO58"),
@@ -530,8 +471,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(2, "I2S1_BCK"),
MTK_FUNCTION(7, "DBG_MON_B_8_")
),
- MTK_PIN(
- PINCTRL_PIN(59, "MSDC0_DAT2"),
+ MTK_PIN(PINCTRL_PIN(59, "MSDC0_DAT2"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 59),
MTK_FUNCTION(0, "GPIO59"),
@@ -539,8 +479,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(2, "I2S1_MCK"),
MTK_FUNCTION(7, "DBG_MON_B_9_")
),
- MTK_PIN(
- PINCTRL_PIN(60, "MSDC0_DAT3"),
+ MTK_PIN(PINCTRL_PIN(60, "MSDC0_DAT3"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 60),
MTK_FUNCTION(0, "GPIO60"),
@@ -548,8 +487,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(2, "I2S1_DO_1"),
MTK_FUNCTION(7, "DBG_MON_B_10_")
),
- MTK_PIN(
- PINCTRL_PIN(61, "MSDC0_DAT4"),
+ MTK_PIN(PINCTRL_PIN(61, "MSDC0_DAT4"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 61),
MTK_FUNCTION(0, "GPIO61"),
@@ -557,8 +495,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(2, "I2S1_DO_2"),
MTK_FUNCTION(7, "DBG_MON_B_11_")
),
- MTK_PIN(
- PINCTRL_PIN(62, "MSDC0_DAT5"),
+ MTK_PIN(PINCTRL_PIN(62, "MSDC0_DAT5"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 62),
MTK_FUNCTION(0, "GPIO62"),
@@ -566,8 +503,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(2, "I2S2_WS"),
MTK_FUNCTION(7, "DBG_MON_B_12_")
),
- MTK_PIN(
- PINCTRL_PIN(63, "MSDC0_DAT6"),
+ MTK_PIN(PINCTRL_PIN(63, "MSDC0_DAT6"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 63),
MTK_FUNCTION(0, "GPIO63"),
@@ -575,8 +511,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(2, "I2S2_BCK"),
MTK_FUNCTION(7, "DBG_MON_B_13_")
),
- MTK_PIN(
- PINCTRL_PIN(64, "MSDC0_DAT7"),
+ MTK_PIN(PINCTRL_PIN(64, "MSDC0_DAT7"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 64),
MTK_FUNCTION(0, "GPIO64"),
@@ -584,16 +519,14 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(2, "I2S2_DI_1"),
MTK_FUNCTION(7, "DBG_MON_B_14_")
),
- MTK_PIN(
- PINCTRL_PIN(65, "MSDC0_CLK"),
+ MTK_PIN(PINCTRL_PIN(65, "MSDC0_CLK"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 65),
MTK_FUNCTION(0, "GPIO65"),
MTK_FUNCTION(1, "MSDC0_CLK"),
MTK_FUNCTION(7, "DBG_MON_B_16_")
),
- MTK_PIN(
- PINCTRL_PIN(66, "MSDC0_CMD"),
+ MTK_PIN(PINCTRL_PIN(66, "MSDC0_CMD"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 66),
MTK_FUNCTION(0, "GPIO66"),
@@ -601,16 +534,14 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(2, "I2S2_DI_2"),
MTK_FUNCTION(7, "DBG_MON_B_15_")
),
- MTK_PIN(
- PINCTRL_PIN(67, "MSDC0_DSL"),
+ MTK_PIN(PINCTRL_PIN(67, "MSDC0_DSL"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 67),
MTK_FUNCTION(0, "GPIO67"),
MTK_FUNCTION(1, "MSDC0_DSL"),
MTK_FUNCTION(7, "DBG_MON_B_17_")
),
- MTK_PIN(
- PINCTRL_PIN(68, "MSDC0_RST_"),
+ MTK_PIN(PINCTRL_PIN(68, "MSDC0_RST_"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 68),
MTK_FUNCTION(0, "GPIO68"),
@@ -618,8 +549,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(2, "I2S2_MCK"),
MTK_FUNCTION(7, "DBG_MON_B_18_")
),
- MTK_PIN(
- PINCTRL_PIN(69, "SPI_CK"),
+ MTK_PIN(PINCTRL_PIN(69, "SPI_CK"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 69),
MTK_FUNCTION(0, "GPIO69"),
@@ -630,8 +560,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(5, "I2S2_MCK"),
MTK_FUNCTION(7, "DBG_MON_B_19_")
),
- MTK_PIN(
- PINCTRL_PIN(70, "SPI_MI"),
+ MTK_PIN(PINCTRL_PIN(70, "SPI_MI"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 70),
MTK_FUNCTION(0, "GPIO70"),
@@ -643,8 +572,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(6, "DSI1_TE"),
MTK_FUNCTION(7, "DBG_MON_B_20_")
),
- MTK_PIN(
- PINCTRL_PIN(71, "SPI_MO"),
+ MTK_PIN(PINCTRL_PIN(71, "SPI_MO"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 71),
MTK_FUNCTION(0, "GPIO71"),
@@ -655,8 +583,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(5, "I2S2_DI_2"),
MTK_FUNCTION(7, "DBG_MON_B_21_")
),
- MTK_PIN(
- PINCTRL_PIN(72, "SPI_CS"),
+ MTK_PIN(PINCTRL_PIN(72, "SPI_CS"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 72),
MTK_FUNCTION(0, "GPIO72"),
@@ -667,116 +594,101 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(5, "DISP_PWM1"),
MTK_FUNCTION(7, "DBG_MON_B_22_")
),
- MTK_PIN(
- PINCTRL_PIN(73, "MSDC1_DAT0"),
+ MTK_PIN(PINCTRL_PIN(73, "MSDC1_DAT0"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 73),
MTK_FUNCTION(0, "GPIO73"),
MTK_FUNCTION(1, "MSDC1_DAT0"),
MTK_FUNCTION(7, "DBG_MON_B_24_")
),
- MTK_PIN(
- PINCTRL_PIN(74, "MSDC1_DAT1"),
+ MTK_PIN(PINCTRL_PIN(74, "MSDC1_DAT1"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 74),
MTK_FUNCTION(0, "GPIO74"),
MTK_FUNCTION(1, "MSDC1_DAT1"),
MTK_FUNCTION(7, "DBG_MON_B_25_")
),
- MTK_PIN(
- PINCTRL_PIN(75, "MSDC1_DAT2"),
+ MTK_PIN(PINCTRL_PIN(75, "MSDC1_DAT2"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 75),
MTK_FUNCTION(0, "GPIO75"),
MTK_FUNCTION(1, "MSDC1_DAT2"),
MTK_FUNCTION(7, "DBG_MON_B_26_")
),
- MTK_PIN(
- PINCTRL_PIN(76, "MSDC1_DAT3"),
+ MTK_PIN(PINCTRL_PIN(76, "MSDC1_DAT3"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 76),
MTK_FUNCTION(0, "GPIO76"),
MTK_FUNCTION(1, "MSDC1_DAT3"),
MTK_FUNCTION(7, "DBG_MON_B_27_")
),
- MTK_PIN(
- PINCTRL_PIN(77, "MSDC1_CLK"),
+ MTK_PIN(PINCTRL_PIN(77, "MSDC1_CLK"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 77),
MTK_FUNCTION(0, "GPIO77"),
MTK_FUNCTION(1, "MSDC1_CLK"),
MTK_FUNCTION(7, "DBG_MON_B_28_")
),
- MTK_PIN(
- PINCTRL_PIN(78, "MSDC1_CMD"),
+ MTK_PIN(PINCTRL_PIN(78, "MSDC1_CMD"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 78),
MTK_FUNCTION(0, "GPIO78"),
MTK_FUNCTION(1, "MSDC1_CMD"),
MTK_FUNCTION(7, "DBG_MON_B_23_")
),
- MTK_PIN(
- PINCTRL_PIN(79, "PWRAP_SPI0_MI"),
+ MTK_PIN(PINCTRL_PIN(79, "PWRAP_SPI0_MI"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 79),
MTK_FUNCTION(0, "GPIO79"),
MTK_FUNCTION(1, "PWRAP_SPIMI"),
MTK_FUNCTION(2, "PWRAP_SPIMO")
),
- MTK_PIN(
- PINCTRL_PIN(80, "PWRAP_SPI0_MO"),
+ MTK_PIN(PINCTRL_PIN(80, "PWRAP_SPI0_MO"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 80),
MTK_FUNCTION(0, "GPIO80"),
MTK_FUNCTION(1, "PWRAP_SPIMO"),
MTK_FUNCTION(2, "PWRAP_SPIMI")
),
- MTK_PIN(
- PINCTRL_PIN(81, "PWRAP_SPI0_CK"),
+ MTK_PIN(PINCTRL_PIN(81, "PWRAP_SPI0_CK"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 81),
MTK_FUNCTION(0, "GPIO81"),
MTK_FUNCTION(1, "PWRAP_SPICK")
),
- MTK_PIN(
- PINCTRL_PIN(82, "PWRAP_SPI0_CSN"),
+ MTK_PIN(PINCTRL_PIN(82, "PWRAP_SPI0_CSN"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 82),
MTK_FUNCTION(0, "GPIO82"),
MTK_FUNCTION(1, "PWRAP_SPICS")
),
- MTK_PIN(
- PINCTRL_PIN(83, "AUD_CLK_MOSI"),
+ MTK_PIN(PINCTRL_PIN(83, "AUD_CLK_MOSI"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 83),
MTK_FUNCTION(0, "GPIO83"),
MTK_FUNCTION(1, "AUD_CLK_MOSI")
),
- MTK_PIN(
- PINCTRL_PIN(84, "AUD_DAT_MISO"),
+ MTK_PIN(PINCTRL_PIN(84, "AUD_DAT_MISO"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 84),
MTK_FUNCTION(0, "GPIO84"),
MTK_FUNCTION(1, "AUD_DAT_MISO"),
MTK_FUNCTION(2, "AUD_DAT_MOSI")
),
- MTK_PIN(
- PINCTRL_PIN(85, "AUD_DAT_MOSI"),
+ MTK_PIN(PINCTRL_PIN(85, "AUD_DAT_MOSI"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 85),
MTK_FUNCTION(0, "GPIO85"),
MTK_FUNCTION(1, "AUD_DAT_MOSI"),
MTK_FUNCTION(2, "AUD_DAT_MISO")
),
- MTK_PIN(
- PINCTRL_PIN(86, "RTC32K_CK"),
+ MTK_PIN(PINCTRL_PIN(86, "RTC32K_CK"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 86),
MTK_FUNCTION(0, "GPIO86"),
MTK_FUNCTION(1, "RTC32K_CK")
),
- MTK_PIN(
- PINCTRL_PIN(87, "DISP_PWM0"),
+ MTK_PIN(PINCTRL_PIN(87, "DISP_PWM0"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 87),
MTK_FUNCTION(0, "GPIO87"),
@@ -784,36 +696,31 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(2, "DISP_PWM1"),
MTK_FUNCTION(7, "DBG_MON_B_31_")
),
- MTK_PIN(
- PINCTRL_PIN(88, "SRCLKENAI"),
+ MTK_PIN(PINCTRL_PIN(88, "SRCLKENAI"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 88),
MTK_FUNCTION(0, "GPIO88"),
MTK_FUNCTION(1, "SRCLKENAI")
),
- MTK_PIN(
- PINCTRL_PIN(89, "SRCLKENAI2"),
+ MTK_PIN(PINCTRL_PIN(89, "SRCLKENAI2"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 89),
MTK_FUNCTION(0, "GPIO89"),
MTK_FUNCTION(1, "SRCLKENAI2")
),
- MTK_PIN(
- PINCTRL_PIN(90, "SRCLKENA0"),
+ MTK_PIN(PINCTRL_PIN(90, "SRCLKENA0"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 90),
MTK_FUNCTION(0, "GPIO90"),
MTK_FUNCTION(1, "SRCLKENA0")
),
- MTK_PIN(
- PINCTRL_PIN(91, "SRCLKENA1"),
+ MTK_PIN(PINCTRL_PIN(91, "SRCLKENA1"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 91),
MTK_FUNCTION(0, "GPIO91"),
MTK_FUNCTION(1, "SRCLKENA1")
),
- MTK_PIN(
- PINCTRL_PIN(92, "PCM_CLK"),
+ MTK_PIN(PINCTRL_PIN(92, "PCM_CLK"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 92),
MTK_FUNCTION(0, "GPIO92"),
@@ -821,8 +728,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(2, "I2S0_BCK"),
MTK_FUNCTION(7, "DBG_MON_A_24_")
),
- MTK_PIN(
- PINCTRL_PIN(93, "PCM_SYNC"),
+ MTK_PIN(PINCTRL_PIN(93, "PCM_SYNC"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 93),
MTK_FUNCTION(0, "GPIO93"),
@@ -830,8 +736,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(2, "I2S0_WS"),
MTK_FUNCTION(7, "DBG_MON_A_25_")
),
- MTK_PIN(
- PINCTRL_PIN(94, "PCM_RX"),
+ MTK_PIN(PINCTRL_PIN(94, "PCM_RX"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 94),
MTK_FUNCTION(0, "GPIO94"),
@@ -839,8 +744,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(2, "I2S0_DI"),
MTK_FUNCTION(7, "DBG_MON_A_26_")
),
- MTK_PIN(
- PINCTRL_PIN(95, "PCM_TX"),
+ MTK_PIN(PINCTRL_PIN(95, "PCM_TX"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 95),
MTK_FUNCTION(0, "GPIO95"),
@@ -848,8 +752,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(2, "I2S0_DO"),
MTK_FUNCTION(7, "DBG_MON_A_27_")
),
- MTK_PIN(
- PINCTRL_PIN(96, "URXD1"),
+ MTK_PIN(PINCTRL_PIN(96, "URXD1"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 96),
MTK_FUNCTION(0, "GPIO96"),
@@ -857,8 +760,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(2, "UTXD1"),
MTK_FUNCTION(7, "DBG_MON_A_28_")
),
- MTK_PIN(
- PINCTRL_PIN(97, "UTXD1"),
+ MTK_PIN(PINCTRL_PIN(97, "UTXD1"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 97),
MTK_FUNCTION(0, "GPIO97"),
@@ -866,8 +768,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(2, "URXD1"),
MTK_FUNCTION(7, "DBG_MON_A_29_")
),
- MTK_PIN(
- PINCTRL_PIN(98, "URTS1"),
+ MTK_PIN(PINCTRL_PIN(98, "URTS1"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 98),
MTK_FUNCTION(0, "GPIO98"),
@@ -875,8 +776,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(2, "UCTS1"),
MTK_FUNCTION(7, "DBG_MON_A_30_")
),
- MTK_PIN(
- PINCTRL_PIN(99, "UCTS1"),
+ MTK_PIN(PINCTRL_PIN(99, "UCTS1"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 99),
MTK_FUNCTION(0, "GPIO99"),
@@ -884,8 +784,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(2, "URTS1"),
MTK_FUNCTION(7, "DBG_MON_A_31_")
),
- MTK_PIN(
- PINCTRL_PIN(100, "MSDC2_DAT0"),
+ MTK_PIN(PINCTRL_PIN(100, "MSDC2_DAT0"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 100),
MTK_FUNCTION(0, "GPIO100"),
@@ -895,8 +794,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(5, "USB_DRVVBUS_P1"),
MTK_FUNCTION(7, "DBG_MON_B_0_")
),
- MTK_PIN(
- PINCTRL_PIN(101, "MSDC2_DAT1"),
+ MTK_PIN(PINCTRL_PIN(101, "MSDC2_DAT1"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 101),
MTK_FUNCTION(0, "GPIO101"),
@@ -905,8 +803,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(4, "SCL5"),
MTK_FUNCTION(7, "DBG_MON_B_1_")
),
- MTK_PIN(
- PINCTRL_PIN(102, "MSDC2_DAT2"),
+ MTK_PIN(PINCTRL_PIN(102, "MSDC2_DAT2"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 102),
MTK_FUNCTION(0, "GPIO102"),
@@ -916,8 +813,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(6, "SPI_CK_1_"),
MTK_FUNCTION(7, "DBG_MON_B_2_")
),
- MTK_PIN(
- PINCTRL_PIN(103, "MSDC2_DAT3"),
+ MTK_PIN(PINCTRL_PIN(103, "MSDC2_DAT3"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 103),
MTK_FUNCTION(0, "GPIO103"),
@@ -927,8 +823,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(6, "SPI_MI_1_"),
MTK_FUNCTION(7, "DBG_MON_B_3_")
),
- MTK_PIN(
- PINCTRL_PIN(104, "MSDC2_CLK"),
+ MTK_PIN(PINCTRL_PIN(104, "MSDC2_CLK"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 104),
MTK_FUNCTION(0, "GPIO104"),
@@ -939,8 +834,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(6, "SPI_MO_1_"),
MTK_FUNCTION(7, "DBG_MON_B_4_")
),
- MTK_PIN(
- PINCTRL_PIN(105, "MSDC2_CMD"),
+ MTK_PIN(PINCTRL_PIN(105, "MSDC2_CMD"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 105),
MTK_FUNCTION(0, "GPIO105"),
@@ -951,22 +845,19 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(6, "SPI_CS_1_"),
MTK_FUNCTION(7, "DBG_MON_B_5_")
),
- MTK_PIN(
- PINCTRL_PIN(106, "SDA3"),
+ MTK_PIN(PINCTRL_PIN(106, "SDA3"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 106),
MTK_FUNCTION(0, "GPIO106"),
MTK_FUNCTION(1, "SDA3")
),
- MTK_PIN(
- PINCTRL_PIN(107, "SCL3"),
+ MTK_PIN(PINCTRL_PIN(107, "SCL3"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 107),
MTK_FUNCTION(0, "GPIO107"),
MTK_FUNCTION(1, "SCL3")
),
- MTK_PIN(
- PINCTRL_PIN(108, "JTMS"),
+ MTK_PIN(PINCTRL_PIN(108, "JTMS"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 108),
MTK_FUNCTION(0, "GPIO108"),
@@ -975,8 +866,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(5, "AP_MD32_JTAG_TMS"),
MTK_FUNCTION(6, "DFD_TMS")
),
- MTK_PIN(
- PINCTRL_PIN(109, "JTCK"),
+ MTK_PIN(PINCTRL_PIN(109, "JTCK"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 109),
MTK_FUNCTION(0, "GPIO109"),
@@ -985,8 +875,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(5, "AP_MD32_JTAG_TCK"),
MTK_FUNCTION(6, "DFD_TCK")
),
- MTK_PIN(
- PINCTRL_PIN(110, "JTDI"),
+ MTK_PIN(PINCTRL_PIN(110, "JTDI"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 110),
MTK_FUNCTION(0, "GPIO110"),
@@ -995,8 +884,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(5, "AP_MD32_JTAG_TDI"),
MTK_FUNCTION(6, "DFD_TDI")
),
- MTK_PIN(
- PINCTRL_PIN(111, "JTDO"),
+ MTK_PIN(PINCTRL_PIN(111, "JTDO"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 111),
MTK_FUNCTION(0, "GPIO111"),
@@ -1005,8 +893,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(5, "AP_MD32_JTAG_TDO"),
MTK_FUNCTION(6, "DFD_TDO")
),
- MTK_PIN(
- PINCTRL_PIN(112, "JTRST_B"),
+ MTK_PIN(PINCTRL_PIN(112, "JTRST_B"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 112),
MTK_FUNCTION(0, "GPIO112"),
@@ -1015,8 +902,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(5, "AP_MD32_JTAG_TRST"),
MTK_FUNCTION(6, "DFD_NTRST")
),
- MTK_PIN(
- PINCTRL_PIN(113, "URXD0"),
+ MTK_PIN(PINCTRL_PIN(113, "URXD0"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 113),
MTK_FUNCTION(0, "GPIO113"),
@@ -1025,8 +911,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(6, "I2S2_WS"),
MTK_FUNCTION(7, "DBG_MON_A_0_")
),
- MTK_PIN(
- PINCTRL_PIN(114, "UTXD0"),
+ MTK_PIN(PINCTRL_PIN(114, "UTXD0"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 114),
MTK_FUNCTION(0, "GPIO114"),
@@ -1035,8 +920,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(6, "I2S2_BCK"),
MTK_FUNCTION(7, "DBG_MON_A_1_")
),
- MTK_PIN(
- PINCTRL_PIN(115, "URTS0"),
+ MTK_PIN(PINCTRL_PIN(115, "URTS0"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 115),
MTK_FUNCTION(0, "GPIO115"),
@@ -1045,8 +929,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(6, "I2S2_MCK"),
MTK_FUNCTION(7, "DBG_MON_A_2_")
),
- MTK_PIN(
- PINCTRL_PIN(116, "UCTS0"),
+ MTK_PIN(PINCTRL_PIN(116, "UCTS0"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 116),
MTK_FUNCTION(0, "GPIO116"),
@@ -1055,8 +938,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(6, "I2S2_DI_1"),
MTK_FUNCTION(7, "DBG_MON_A_3_")
),
- MTK_PIN(
- PINCTRL_PIN(117, "URXD3"),
+ MTK_PIN(PINCTRL_PIN(117, "URXD3"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 117),
MTK_FUNCTION(0, "GPIO117"),
@@ -1064,8 +946,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(2, "UTXD3"),
MTK_FUNCTION(7, "DBG_MON_A_9_")
),
- MTK_PIN(
- PINCTRL_PIN(118, "UTXD3"),
+ MTK_PIN(PINCTRL_PIN(118, "UTXD3"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 118),
MTK_FUNCTION(0, "GPIO118"),
@@ -1073,16 +954,14 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(2, "URXD3"),
MTK_FUNCTION(7, "DBG_MON_A_10_")
),
- MTK_PIN(
- PINCTRL_PIN(119, "KPROW0"),
+ MTK_PIN(PINCTRL_PIN(119, "KPROW0"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 119),
MTK_FUNCTION(0, "GPIO119"),
MTK_FUNCTION(1, "KROW0"),
MTK_FUNCTION(7, "DBG_MON_A_11_")
),
- MTK_PIN(
- PINCTRL_PIN(120, "KPROW1"),
+ MTK_PIN(PINCTRL_PIN(120, "KPROW1"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 120),
MTK_FUNCTION(0, "GPIO120"),
@@ -1090,8 +969,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(3, "PWM6"),
MTK_FUNCTION(7, "DBG_MON_A_12_")
),
- MTK_PIN(
- PINCTRL_PIN(121, "KPROW2"),
+ MTK_PIN(PINCTRL_PIN(121, "KPROW2"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 121),
MTK_FUNCTION(0, "GPIO121"),
@@ -1102,16 +980,14 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(5, "USB_DRVVBUS_P1"),
MTK_FUNCTION(7, "DBG_MON_A_13_")
),
- MTK_PIN(
- PINCTRL_PIN(122, "KPCOL0"),
+ MTK_PIN(PINCTRL_PIN(122, "KPCOL0"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 122),
MTK_FUNCTION(0, "GPIO122"),
MTK_FUNCTION(1, "KCOL0"),
MTK_FUNCTION(7, "DBG_MON_A_14_")
),
- MTK_PIN(
- PINCTRL_PIN(123, "KPCOL1"),
+ MTK_PIN(PINCTRL_PIN(123, "KPCOL1"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 123),
MTK_FUNCTION(0, "GPIO123"),
@@ -1120,8 +996,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(3, "PWM5"),
MTK_FUNCTION(7, "DBG_MON_A_15_")
),
- MTK_PIN(
- PINCTRL_PIN(124, "KPCOL2"),
+ MTK_PIN(PINCTRL_PIN(124, "KPCOL2"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 124),
MTK_FUNCTION(0, "GPIO124"),
@@ -1132,29 +1007,25 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(5, "USB_DRVVBUS_P1"),
MTK_FUNCTION(7, "DBG_MON_A_16_")
),
- MTK_PIN(
- PINCTRL_PIN(125, "SDA1"),
+ MTK_PIN(PINCTRL_PIN(125, "SDA1"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 125),
MTK_FUNCTION(0, "GPIO125"),
MTK_FUNCTION(1, "SDA1")
),
- MTK_PIN(
- PINCTRL_PIN(126, "SCL1"),
+ MTK_PIN(PINCTRL_PIN(126, "SCL1"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 126),
MTK_FUNCTION(0, "GPIO126"),
MTK_FUNCTION(1, "SCL1")
),
- MTK_PIN(
- PINCTRL_PIN(127, "LCM_RST"),
+ MTK_PIN(PINCTRL_PIN(127, "LCM_RST"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 127),
MTK_FUNCTION(0, "GPIO127"),
MTK_FUNCTION(1, "LCM_RST")
),
- MTK_PIN(
- PINCTRL_PIN(128, "I2S0_LRCK"),
+ MTK_PIN(PINCTRL_PIN(128, "I2S0_LRCK"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 128),
MTK_FUNCTION(0, "GPIO128"),
@@ -1164,8 +1035,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(5, "SPI_CK_2_"),
MTK_FUNCTION(7, "DBG_MON_A_4_")
),
- MTK_PIN(
- PINCTRL_PIN(129, "I2S0_BCK"),
+ MTK_PIN(PINCTRL_PIN(129, "I2S0_BCK"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 129),
MTK_FUNCTION(0, "GPIO129"),
@@ -1175,8 +1045,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(5, "SPI_MI_2_"),
MTK_FUNCTION(7, "DBG_MON_A_5_")
),
- MTK_PIN(
- PINCTRL_PIN(130, "I2S0_MCK"),
+ MTK_PIN(PINCTRL_PIN(130, "I2S0_MCK"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 130),
MTK_FUNCTION(0, "GPIO130"),
@@ -1186,8 +1055,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(5, "SPI_MO_2_"),
MTK_FUNCTION(7, "DBG_MON_A_6_")
),
- MTK_PIN(
- PINCTRL_PIN(131, "I2S0_DATA0"),
+ MTK_PIN(PINCTRL_PIN(131, "I2S0_DATA0"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 131),
MTK_FUNCTION(0, "GPIO131"),
@@ -1197,8 +1065,7 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(5, "SPI_CS_2_"),
MTK_FUNCTION(7, "DBG_MON_A_7_")
),
- MTK_PIN(
- PINCTRL_PIN(132, "I2S0_DATA1"),
+ MTK_PIN(PINCTRL_PIN(132, "I2S0_DATA1"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 132),
MTK_FUNCTION(0, "GPIO132"),
@@ -1207,15 +1074,13 @@ static const struct mtk_desc_pin mtk_pins_mt8173[] = {
MTK_FUNCTION(3, "I2S2_DI_2"),
MTK_FUNCTION(7, "DBG_MON_A_8_")
),
- MTK_PIN(
- PINCTRL_PIN(133, "SDA4"),
+ MTK_PIN(PINCTRL_PIN(133, "SDA4"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 133),
MTK_FUNCTION(0, "GPIO133"),
MTK_FUNCTION(1, "SDA4")
),
- MTK_PIN(
- PINCTRL_PIN(134, "SCL4"),
+ MTK_PIN(PINCTRL_PIN(134, "SCL4"),
NULL, "mt8173",
MTK_EINT_FUNCTION(0, 134),
MTK_FUNCTION(0, "GPIO134"),
diff --git a/drivers/pinctrl/meson/pinctrl-meson8b.c b/drivers/pinctrl/meson/pinctrl-meson8b.c
index 5bd808dc81e1..bb2a30964fc6 100644
--- a/drivers/pinctrl/meson/pinctrl-meson8b.c
+++ b/drivers/pinctrl/meson/pinctrl-meson8b.c
@@ -884,20 +884,24 @@ static struct meson_pmx_func meson8b_aobus_functions[] = {
};
static struct meson_bank meson8b_cbus_banks[] = {
- /* name first last irq pullen pull dir out in */
- BANK("X", GPIOX_0, GPIOX_21, 97, 118, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
- BANK("Y", GPIOY_0, GPIOY_14, 80, 96, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
- BANK("DV", GPIODV_9, GPIODV_29, 59, 79, 0, 0, 0, 0, 7, 0, 8, 0, 9, 0),
- BANK("H", GPIOH_0, GPIOH_9, 14, 23, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19),
- BANK("CARD", CARD_0, CARD_6, 43, 49, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22),
- BANK("BOOT", BOOT_0, BOOT_18, 24, 42, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0),
+ /* name first last irq pullen pull dir out in */
+ BANK("X0..11", GPIOX_0, GPIOX_11, 97, 108, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
+ BANK("X16..21", GPIOX_16, GPIOX_21, 113, 118, 4, 16, 4, 16, 0, 16, 1, 16, 2, 16),
+ BANK("Y0..1", GPIOY_0, GPIOY_1, 80, 81, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
+ BANK("Y3", GPIOY_3, GPIOY_3, 83, 83, 3, 3, 3, 3, 3, 3, 4, 3, 5, 3),
+ BANK("Y6..14", GPIOY_6, GPIOY_14, 86, 94, 3, 6, 3, 6, 3, 6, 4, 6, 5, 6),
+ BANK("DV9", GPIODV_9, GPIODV_9, 59, 59, 0, 9, 0, 9, 7, 9, 8, 9, 9, 9),
+ BANK("DV24..29", GPIODV_24, GPIODV_29, 74, 79, 0, 24, 0, 24, 7, 24, 8, 24, 9, 24),
+ BANK("H", GPIOH_0, GPIOH_9, 14, 23, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19),
+ BANK("CARD", CARD_0, CARD_6, 43, 49, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22),
+ BANK("BOOT", BOOT_0, BOOT_18, 24, 42, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0),
/*
* The following bank is not mentionned in the public datasheet
* There is no information whether it can be used with the gpio
* interrupt controller
*/
- BANK("DIF", DIF_0_P, DIF_4_N, -1, -1, 5, 8, 5, 8, 12, 12, 13, 12, 14, 12),
+ BANK("DIF", DIF_0_P, DIF_4_N, -1, -1, 5, 8, 5, 8, 12, 12, 13, 12, 14, 12),
};
static struct meson_bank meson8b_aobus_banks[] = {
diff --git a/drivers/pinctrl/nomadik/Kconfig b/drivers/pinctrl/nomadik/Kconfig
index f4fcebfce68c..c3efe7d7e91f 100644
--- a/drivers/pinctrl/nomadik/Kconfig
+++ b/drivers/pinctrl/nomadik/Kconfig
@@ -11,14 +11,6 @@ config PINCTRL_AB8500
bool "AB8500 pin controller driver"
depends on PINCTRL_ABX500 && ARCH_U8500
-config PINCTRL_AB8540
- bool "AB8540 pin controller driver"
- depends on PINCTRL_ABX500 && ARCH_U8500
-
-config PINCTRL_AB9540
- bool "AB9540 pin controller driver"
- depends on PINCTRL_ABX500 && ARCH_U8500
-
config PINCTRL_AB8505
bool "AB8505 pin controller driver"
depends on PINCTRL_ABX500 && ARCH_U8500
@@ -44,8 +36,4 @@ config PINCTRL_DB8500
bool "DB8500 pin controller driver"
depends on PINCTRL_NOMADIK && ARCH_U8500
-config PINCTRL_DB8540
- bool "DB8540 pin controller driver"
- depends on PINCTRL_NOMADIK && ARCH_U8500
-
endif
diff --git a/drivers/pinctrl/nomadik/Makefile b/drivers/pinctrl/nomadik/Makefile
index bf8b7517ee4a..dd10d49daf80 100644
--- a/drivers/pinctrl/nomadik/Makefile
+++ b/drivers/pinctrl/nomadik/Makefile
@@ -2,10 +2,7 @@
# Nomadik family pin control drivers
obj-$(CONFIG_PINCTRL_ABX500) += pinctrl-abx500.o
obj-$(CONFIG_PINCTRL_AB8500) += pinctrl-ab8500.o
-obj-$(CONFIG_PINCTRL_AB8540) += pinctrl-ab8540.o
-obj-$(CONFIG_PINCTRL_AB9540) += pinctrl-ab9540.o
obj-$(CONFIG_PINCTRL_AB8505) += pinctrl-ab8505.o
obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o
obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o
obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o
-obj-$(CONFIG_PINCTRL_DB8540) += pinctrl-nomadik-db8540.o
diff --git a/drivers/pinctrl/nomadik/pinctrl-ab8540.c b/drivers/pinctrl/nomadik/pinctrl-ab8540.c
deleted file mode 100644
index 9867535d49c1..000000000000
--- a/drivers/pinctrl/nomadik/pinctrl-ab8540.c
+++ /dev/null
@@ -1,408 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2012
- *
- * Author: Patrice Chotard <patrice.chotard@stericsson.com> for ST-Ericsson.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/gpio.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/mfd/abx500/ab8500.h>
-#include "pinctrl-abx500.h"
-
-/* All the pins that can be used for GPIO and some other functions */
-#define ABX500_GPIO(offset) (offset)
-
-#define AB8540_PIN_J16 ABX500_GPIO(1)
-#define AB8540_PIN_D17 ABX500_GPIO(2)
-#define AB8540_PIN_C12 ABX500_GPIO(3)
-#define AB8540_PIN_G12 ABX500_GPIO(4)
-/* hole */
-#define AB8540_PIN_D16 ABX500_GPIO(14)
-#define AB8540_PIN_F15 ABX500_GPIO(15)
-#define AB8540_PIN_J8 ABX500_GPIO(16)
-#define AB8540_PIN_K16 ABX500_GPIO(17)
-#define AB8540_PIN_G15 ABX500_GPIO(18)
-#define AB8540_PIN_F17 ABX500_GPIO(19)
-#define AB8540_PIN_E17 ABX500_GPIO(20)
-/* hole */
-#define AB8540_PIN_AA16 ABX500_GPIO(27)
-#define AB8540_PIN_W18 ABX500_GPIO(28)
-#define AB8540_PIN_Y15 ABX500_GPIO(29)
-#define AB8540_PIN_W16 ABX500_GPIO(30)
-#define AB8540_PIN_V15 ABX500_GPIO(31)
-#define AB8540_PIN_W17 ABX500_GPIO(32)
-/* hole */
-#define AB8540_PIN_D12 ABX500_GPIO(42)
-#define AB8540_PIN_P4 ABX500_GPIO(43)
-#define AB8540_PIN_AB1 ABX500_GPIO(44)
-#define AB8540_PIN_K7 ABX500_GPIO(45)
-#define AB8540_PIN_L7 ABX500_GPIO(46)
-#define AB8540_PIN_G10 ABX500_GPIO(47)
-#define AB8540_PIN_K12 ABX500_GPIO(48)
-/* hole */
-#define AB8540_PIN_N8 ABX500_GPIO(51)
-#define AB8540_PIN_P12 ABX500_GPIO(52)
-#define AB8540_PIN_K8 ABX500_GPIO(53)
-#define AB8540_PIN_J11 ABX500_GPIO(54)
-#define AB8540_PIN_AC2 ABX500_GPIO(55)
-#define AB8540_PIN_AB2 ABX500_GPIO(56)
-
-/* indicates the highest GPIO number */
-#define AB8540_GPIO_MAX_NUMBER 56
-
-/*
- * The names of the pins are denoted by GPIO number and ball name, even
- * though they can be used for other things than GPIO, this is the first
- * column in the table of the data sheet and often used on schematics and
- * such.
- */
-static const struct pinctrl_pin_desc ab8540_pins[] = {
- PINCTRL_PIN(AB8540_PIN_J16, "GPIO1_J16"),
- PINCTRL_PIN(AB8540_PIN_D17, "GPIO2_D17"),
- PINCTRL_PIN(AB8540_PIN_C12, "GPIO3_C12"),
- PINCTRL_PIN(AB8540_PIN_G12, "GPIO4_G12"),
- /* hole */
- PINCTRL_PIN(AB8540_PIN_D16, "GPIO14_D16"),
- PINCTRL_PIN(AB8540_PIN_F15, "GPIO15_F15"),
- PINCTRL_PIN(AB8540_PIN_J8, "GPIO16_J8"),
- PINCTRL_PIN(AB8540_PIN_K16, "GPIO17_K16"),
- PINCTRL_PIN(AB8540_PIN_G15, "GPIO18_G15"),
- PINCTRL_PIN(AB8540_PIN_F17, "GPIO19_F17"),
- PINCTRL_PIN(AB8540_PIN_E17, "GPIO20_E17"),
- /* hole */
- PINCTRL_PIN(AB8540_PIN_AA16, "GPIO27_AA16"),
- PINCTRL_PIN(AB8540_PIN_W18, "GPIO28_W18"),
- PINCTRL_PIN(AB8540_PIN_Y15, "GPIO29_Y15"),
- PINCTRL_PIN(AB8540_PIN_W16, "GPIO30_W16"),
- PINCTRL_PIN(AB8540_PIN_V15, "GPIO31_V15"),
- PINCTRL_PIN(AB8540_PIN_W17, "GPIO32_W17"),
- /* hole */
- PINCTRL_PIN(AB8540_PIN_D12, "GPIO42_D12"),
- PINCTRL_PIN(AB8540_PIN_P4, "GPIO43_P4"),
- PINCTRL_PIN(AB8540_PIN_AB1, "GPIO44_AB1"),
- PINCTRL_PIN(AB8540_PIN_K7, "GPIO45_K7"),
- PINCTRL_PIN(AB8540_PIN_L7, "GPIO46_L7"),
- PINCTRL_PIN(AB8540_PIN_G10, "GPIO47_G10"),
- PINCTRL_PIN(AB8540_PIN_K12, "GPIO48_K12"),
- /* hole */
- PINCTRL_PIN(AB8540_PIN_N8, "GPIO51_N8"),
- PINCTRL_PIN(AB8540_PIN_P12, "GPIO52_P12"),
- PINCTRL_PIN(AB8540_PIN_K8, "GPIO53_K8"),
- PINCTRL_PIN(AB8540_PIN_J11, "GPIO54_J11"),
- PINCTRL_PIN(AB8540_PIN_AC2, "GPIO55_AC2"),
- PINCTRL_PIN(AB8540_PIN_AB2, "GPIO56_AB2"),
-};
-
-/*
- * Maps local GPIO offsets to local pin numbers
- */
-static const struct abx500_pinrange ab8540_pinranges[] = {
- ABX500_PINRANGE(1, 4, ABX500_ALT_A),
- ABX500_PINRANGE(14, 7, ABX500_ALT_A),
- ABX500_PINRANGE(27, 6, ABX500_ALT_A),
- ABX500_PINRANGE(42, 7, ABX500_ALT_A),
- ABX500_PINRANGE(51, 6, ABX500_ALT_A),
-};
-
-/*
- * Read the pin group names like this:
- * sysclkreq2_d_1 = first groups of pins for sysclkreq2 on default function
- *
- * The groups are arranged as sets per altfunction column, so we can
- * mux in one group at a time by selecting the same altfunction for them
- * all. When functions require pins on different altfunctions, you need
- * to combine several groups.
- */
-
-/* default column */
-static const unsigned sysclkreq2_d_1_pins[] = { AB8540_PIN_J16 };
-static const unsigned sysclkreq3_d_1_pins[] = { AB8540_PIN_D17 };
-static const unsigned sysclkreq4_d_1_pins[] = { AB8540_PIN_C12 };
-static const unsigned sysclkreq6_d_1_pins[] = { AB8540_PIN_G12 };
-static const unsigned pwmout1_d_1_pins[] = { AB8540_PIN_D16 };
-static const unsigned pwmout2_d_1_pins[] = { AB8540_PIN_F15 };
-static const unsigned pwmout3_d_1_pins[] = { AB8540_PIN_J8 };
-
-/* audio data interface 1*/
-static const unsigned adi1_d_1_pins[] = { AB8540_PIN_K16, AB8540_PIN_G15,
- AB8540_PIN_F17, AB8540_PIN_E17 };
-/* Digital microphone 1 and 2 */
-static const unsigned dmic12_d_1_pins[] = { AB8540_PIN_AA16, AB8540_PIN_W18 };
-/* Digital microphone 3 and 4 */
-static const unsigned dmic34_d_1_pins[] = { AB8540_PIN_Y15, AB8540_PIN_W16 };
-/* Digital microphone 5 and 6 */
-static const unsigned dmic56_d_1_pins[] = { AB8540_PIN_V15, AB8540_PIN_W17 };
-static const unsigned sysclkreq5_d_1_pins[] = { AB8540_PIN_D12 };
-static const unsigned batremn_d_1_pins[] = { AB8540_PIN_P4 };
-static const unsigned service_d_1_pins[] = { AB8540_PIN_AB1 };
-static const unsigned pwrctrl0_d_1_pins[] = { AB8540_PIN_K7 };
-static const unsigned pwrctrl1_d_1_pins[] = { AB8540_PIN_L7 };
-static const unsigned pwmextvibra1_d_1_pins[] = { AB8540_PIN_G10 };
-static const unsigned pwmextvibra2_d_1_pins[] = { AB8540_PIN_K12 };
-static const unsigned gpio1_vbat_d_1_pins[] = { AB8540_PIN_N8 };
-static const unsigned gpio2_vbat_d_1_pins[] = { AB8540_PIN_P12 };
-static const unsigned gpio3_vbat_d_1_pins[] = { AB8540_PIN_K8 };
-static const unsigned gpio4_vbat_d_1_pins[] = { AB8540_PIN_J11 };
-static const unsigned pdmclkdat_d_1_pins[] = { AB8540_PIN_AC2, AB8540_PIN_AB2 };
-
-/* Altfunction A column */
-static const unsigned gpio1_a_1_pins[] = { AB8540_PIN_J16 };
-static const unsigned gpio2_a_1_pins[] = { AB8540_PIN_D17 };
-static const unsigned gpio3_a_1_pins[] = { AB8540_PIN_C12 };
-static const unsigned gpio4_a_1_pins[] = { AB8540_PIN_G12 };
-static const unsigned gpio14_a_1_pins[] = { AB8540_PIN_D16 };
-static const unsigned gpio15_a_1_pins[] = { AB8540_PIN_F15 };
-static const unsigned gpio16_a_1_pins[] = { AB8540_PIN_J8 };
-static const unsigned gpio17_a_1_pins[] = { AB8540_PIN_K16 };
-static const unsigned gpio18_a_1_pins[] = { AB8540_PIN_G15 };
-static const unsigned gpio19_a_1_pins[] = { AB8540_PIN_F17 };
-static const unsigned gpio20_a_1_pins[] = { AB8540_PIN_E17 };
-static const unsigned gpio27_a_1_pins[] = { AB8540_PIN_AA16 };
-static const unsigned gpio28_a_1_pins[] = { AB8540_PIN_W18 };
-static const unsigned gpio29_a_1_pins[] = { AB8540_PIN_Y15 };
-static const unsigned gpio30_a_1_pins[] = { AB8540_PIN_W16 };
-static const unsigned gpio31_a_1_pins[] = { AB8540_PIN_V15 };
-static const unsigned gpio32_a_1_pins[] = { AB8540_PIN_W17 };
-static const unsigned gpio42_a_1_pins[] = { AB8540_PIN_D12 };
-static const unsigned gpio43_a_1_pins[] = { AB8540_PIN_P4 };
-static const unsigned gpio44_a_1_pins[] = { AB8540_PIN_AB1 };
-static const unsigned gpio45_a_1_pins[] = { AB8540_PIN_K7 };
-static const unsigned gpio46_a_1_pins[] = { AB8540_PIN_L7 };
-static const unsigned gpio47_a_1_pins[] = { AB8540_PIN_G10 };
-static const unsigned gpio48_a_1_pins[] = { AB8540_PIN_K12 };
-static const unsigned gpio51_a_1_pins[] = { AB8540_PIN_N8 };
-static const unsigned gpio52_a_1_pins[] = { AB8540_PIN_P12 };
-static const unsigned gpio53_a_1_pins[] = { AB8540_PIN_K8 };
-static const unsigned gpio54_a_1_pins[] = { AB8540_PIN_J11 };
-static const unsigned gpio55_a_1_pins[] = { AB8540_PIN_AC2 };
-static const unsigned gpio56_a_1_pins[] = { AB8540_PIN_AB2 };
-
-#define AB8540_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \
- .npins = ARRAY_SIZE(a##_pins), .altsetting = b }
-
-static const struct abx500_pingroup ab8540_groups[] = {
- /* default column */
- AB8540_PIN_GROUP(sysclkreq2_d_1, ABX500_DEFAULT),
- AB8540_PIN_GROUP(sysclkreq3_d_1, ABX500_DEFAULT),
- AB8540_PIN_GROUP(sysclkreq4_d_1, ABX500_DEFAULT),
- AB8540_PIN_GROUP(sysclkreq6_d_1, ABX500_DEFAULT),
- AB8540_PIN_GROUP(pwmout1_d_1, ABX500_DEFAULT),
- AB8540_PIN_GROUP(pwmout2_d_1, ABX500_DEFAULT),
- AB8540_PIN_GROUP(pwmout3_d_1, ABX500_DEFAULT),
- AB8540_PIN_GROUP(adi1_d_1, ABX500_DEFAULT),
- AB8540_PIN_GROUP(dmic12_d_1, ABX500_DEFAULT),
- AB8540_PIN_GROUP(dmic34_d_1, ABX500_DEFAULT),
- AB8540_PIN_GROUP(dmic56_d_1, ABX500_DEFAULT),
- AB8540_PIN_GROUP(sysclkreq5_d_1, ABX500_DEFAULT),
- AB8540_PIN_GROUP(batremn_d_1, ABX500_DEFAULT),
- AB8540_PIN_GROUP(service_d_1, ABX500_DEFAULT),
- AB8540_PIN_GROUP(pwrctrl0_d_1, ABX500_DEFAULT),
- AB8540_PIN_GROUP(pwrctrl1_d_1, ABX500_DEFAULT),
- AB8540_PIN_GROUP(pwmextvibra1_d_1, ABX500_DEFAULT),
- AB8540_PIN_GROUP(pwmextvibra2_d_1, ABX500_DEFAULT),
- AB8540_PIN_GROUP(gpio1_vbat_d_1, ABX500_DEFAULT),
- AB8540_PIN_GROUP(gpio2_vbat_d_1, ABX500_DEFAULT),
- AB8540_PIN_GROUP(gpio3_vbat_d_1, ABX500_DEFAULT),
- AB8540_PIN_GROUP(gpio4_vbat_d_1, ABX500_DEFAULT),
- AB8540_PIN_GROUP(pdmclkdat_d_1, ABX500_DEFAULT),
- /* Altfunction A column */
- AB8540_PIN_GROUP(gpio1_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio2_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio3_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio4_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio14_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio15_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio16_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio17_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio18_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio19_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio20_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio27_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio28_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio29_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio30_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio31_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio32_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio42_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio43_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio44_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio45_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio46_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio47_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio48_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio51_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio52_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio53_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio54_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio55_a_1, ABX500_ALT_A),
- AB8540_PIN_GROUP(gpio56_a_1, ABX500_ALT_A),
-};
-
-/* We use this macro to define the groups applicable to a function */
-#define AB8540_FUNC_GROUPS(a, b...) \
-static const char * const a##_groups[] = { b };
-
-AB8540_FUNC_GROUPS(sysclkreq, "sysclkreq2_d_1", "sysclkreq3_d_1",
- "sysclkreq4_d_1", "sysclkreq5_d_1", "sysclkreq6_d_1");
-AB8540_FUNC_GROUPS(gpio, "gpio1_a_1", "gpio2_a_1", "gpio3_a_1", "gpio4_a_1",
- "gpio14_a_1", "gpio15_a_1", "gpio16_a_1", "gpio17_a_1",
- "gpio18_a_1", "gpio19_a_1", "gpio20_a_1", "gpio27_a_1",
- "gpio28_a_1", "gpio29_a_1", "gpio30_a_1", "gpio31_a_1",
- "gpio32_a_1", "gpio42_a_1", "gpio43_a_1", "gpio44_a_1",
- "gpio45_a_1", "gpio46_a_1", "gpio47_a_1", "gpio48_a_1",
- "gpio51_a_1", "gpio52_a_1", "gpio53_a_1", "gpio54_a_1",
- "gpio55_a_1", "gpio56_a_1");
-AB8540_FUNC_GROUPS(pwmout, "pwmout1_d_1", "pwmout2_d_1", "pwmout3_d_1");
-AB8540_FUNC_GROUPS(adi1, "adi1_d_1");
-AB8540_FUNC_GROUPS(dmic, "dmic12_d_1", "dmic34_d_1", "dmic56_d_1");
-AB8540_FUNC_GROUPS(batremn, "batremn_d_1");
-AB8540_FUNC_GROUPS(service, "service_d_1");
-AB8540_FUNC_GROUPS(pwrctrl, "pwrctrl0_d_1", "pwrctrl1_d_1");
-AB8540_FUNC_GROUPS(pwmextvibra, "pwmextvibra1_d_1", "pwmextvibra2_d_1");
-AB8540_FUNC_GROUPS(gpio_vbat, "gpio1_vbat_d_1", "gpio2_vbat_d_1",
- "gpio3_vbat_d_1", "gpio4_vbat_d_1");
-AB8540_FUNC_GROUPS(pdm, "pdmclkdat_d_1");
-
-#define FUNCTION(fname) \
- { \
- .name = #fname, \
- .groups = fname##_groups, \
- .ngroups = ARRAY_SIZE(fname##_groups), \
- }
-
-static const struct abx500_function ab8540_functions[] = {
- FUNCTION(sysclkreq),
- FUNCTION(gpio),
- FUNCTION(pwmout),
- FUNCTION(adi1),
- FUNCTION(dmic),
- FUNCTION(batremn),
- FUNCTION(service),
- FUNCTION(pwrctrl),
- FUNCTION(pwmextvibra),
- FUNCTION(gpio_vbat),
- FUNCTION(pdm),
-};
-
-/*
- * this table translates what's is in the AB8540 specification regarding the
- * balls alternate functions (as for DB, default, ALT_A, ALT_B and ALT_C).
- * ALTERNATE_FUNCTIONS(GPIO_NUMBER, GPIOSEL bit, ALTERNATFUNC bit1,
- * ALTERNATEFUNC bit2, ALTA val, ALTB val, ALTC val),
- * AB8540 only supports DEFAULT and ALTA functions, so ALTERNATFUNC
- * registers is not used
- *
- */
-
-static struct
-alternate_functions ab8540_alternate_functions[AB8540_GPIO_MAX_NUMBER + 1] = {
- /* GPIOSEL1 - bit 4-7 reserved */
- ALTERNATE_FUNCTIONS(0, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO0 */
- ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO1, altA controlled by bit 0 */
- ALTERNATE_FUNCTIONS(2, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO2, altA controlled by bit 1 */
- ALTERNATE_FUNCTIONS(3, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO3, altA controlled by bit 2*/
- ALTERNATE_FUNCTIONS(4, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO4, altA controlled by bit 3*/
- ALTERNATE_FUNCTIONS(5, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO5 */
- ALTERNATE_FUNCTIONS(6, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO6 */
- ALTERNATE_FUNCTIONS(7, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO7 */
- ALTERNATE_FUNCTIONS(8, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO8 */
- /* GPIOSEL2 - bit 0-4 reserved */
- ALTERNATE_FUNCTIONS(9, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO9 */
- ALTERNATE_FUNCTIONS(10, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO10 */
- ALTERNATE_FUNCTIONS(11, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO11 */
- ALTERNATE_FUNCTIONS(12, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO12 */
- ALTERNATE_FUNCTIONS(13, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO13 */
- ALTERNATE_FUNCTIONS(14, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */
- ALTERNATE_FUNCTIONS(15, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO15, altA controlled by bit 6 */
- ALTERNATE_FUNCTIONS(16, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO16, altA controlled by bit 7 */
- /* GPIOSEL3 - bit 4-7 reserved */
- ALTERNATE_FUNCTIONS(17, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO17, altA controlled by bit 0 */
- ALTERNATE_FUNCTIONS(18, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO18, altA controlled by bit 1 */
- ALTERNATE_FUNCTIONS(19, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO19, altA controlled by bit 2 */
- ALTERNATE_FUNCTIONS(20, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO20, altA controlled by bit 3 */
- ALTERNATE_FUNCTIONS(21, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO21 */
- ALTERNATE_FUNCTIONS(22, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO22 */
- ALTERNATE_FUNCTIONS(23, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO23 */
- ALTERNATE_FUNCTIONS(24, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO24 */
- /* GPIOSEL4 - bit 0-1 reserved */
- ALTERNATE_FUNCTIONS(25, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO25 */
- ALTERNATE_FUNCTIONS(26, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO26 */
- ALTERNATE_FUNCTIONS(27, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO27, altA controlled by bit 2 */
- ALTERNATE_FUNCTIONS(28, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO28, altA controlled by bit 3 */
- ALTERNATE_FUNCTIONS(29, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO29, altA controlled by bit 4 */
- ALTERNATE_FUNCTIONS(30, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO30, altA controlled by bit 5 */
- ALTERNATE_FUNCTIONS(31, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO31, altA controlled by bit 6 */
- ALTERNATE_FUNCTIONS(32, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO32, altA controlled by bit 7 */
- /* GPIOSEL5 - bit 0-7 reserved */
- ALTERNATE_FUNCTIONS(33, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO33 */
- ALTERNATE_FUNCTIONS(34, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO34 */
- ALTERNATE_FUNCTIONS(35, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO35 */
- ALTERNATE_FUNCTIONS(36, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO36 */
- ALTERNATE_FUNCTIONS(37, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO37 */
- ALTERNATE_FUNCTIONS(38, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO38 */
- ALTERNATE_FUNCTIONS(39, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO39 */
- ALTERNATE_FUNCTIONS(40, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO40 */
- /* GPIOSEL6 - bit 0 reserved */
- ALTERNATE_FUNCTIONS(41, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO41 */
- ALTERNATE_FUNCTIONS(42, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO42, altA controlled by bit 1 */
- ALTERNATE_FUNCTIONS(43, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO43, altA controlled by bit 2 */
- ALTERNATE_FUNCTIONS(44, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO44, altA controlled by bit 3 */
- ALTERNATE_FUNCTIONS(45, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO45, altA controlled by bit 4 */
- ALTERNATE_FUNCTIONS(46, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO46, altA controlled by bit 5 */
- ALTERNATE_FUNCTIONS(47, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO47, altA controlled by bit 6 */
- ALTERNATE_FUNCTIONS(48, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO48, altA controlled by bit 7 */
- /* GPIOSEL7 - bit 0-1 reserved */
- ALTERNATE_FUNCTIONS(49, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO49 */
- ALTERNATE_FUNCTIONS(50, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO50 */
- ALTERNATE_FUNCTIONS(51, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO51, altA controlled by bit 2 */
- ALTERNATE_FUNCTIONS(52, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO52, altA controlled by bit 3 */
- ALTERNATE_FUNCTIONS(53, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO53, altA controlled by bit 4 */
- ALTERNATE_FUNCTIONS(54, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO54, altA controlled by bit 5 */
- ALTERNATE_FUNCTIONS(55, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO55, altA controlled by bit 6 */
- ALTERNATE_FUNCTIONS(56, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO56, altA controlled by bit 7 */
-};
-
-static struct pullud ab8540_pullud = {
- .first_pin = 51, /* GPIO1_VBAT */
- .last_pin = 54, /* GPIO4_VBAT */
-};
-
-/*
- * For AB8540 Only some GPIOs are interrupt capable:
- * GPIO43 to GPIO44
- * GPIO51 to GPIO54
- */
-static struct abx500_gpio_irq_cluster ab8540_gpio_irq_cluster[] = {
- GPIO_IRQ_CLUSTER(43, 43, AB8540_INT_GPIO43F),
- GPIO_IRQ_CLUSTER(44, 44, AB8540_INT_GPIO44F),
- GPIO_IRQ_CLUSTER(51, 54, AB9540_INT_GPIO51R),
-};
-
-static struct abx500_pinctrl_soc_data ab8540_soc = {
- .gpio_ranges = ab8540_pinranges,
- .gpio_num_ranges = ARRAY_SIZE(ab8540_pinranges),
- .pins = ab8540_pins,
- .npins = ARRAY_SIZE(ab8540_pins),
- .functions = ab8540_functions,
- .nfunctions = ARRAY_SIZE(ab8540_functions),
- .groups = ab8540_groups,
- .ngroups = ARRAY_SIZE(ab8540_groups),
- .alternate_functions = ab8540_alternate_functions,
- .pullud = &ab8540_pullud,
- .gpio_irq_cluster = ab8540_gpio_irq_cluster,
- .ngpio_irq_cluster = ARRAY_SIZE(ab8540_gpio_irq_cluster),
- .irq_gpio_rising_offset = AB8540_INT_GPIO43R,
- .irq_gpio_falling_offset = AB8540_INT_GPIO43F,
- .irq_gpio_factor = 2,
-};
-
-void
-abx500_pinctrl_ab8540_init(struct abx500_pinctrl_soc_data **soc)
-{
- *soc = &ab8540_soc;
-}
diff --git a/drivers/pinctrl/nomadik/pinctrl-ab9540.c b/drivers/pinctrl/nomadik/pinctrl-ab9540.c
deleted file mode 100644
index 1a281ca95dac..000000000000
--- a/drivers/pinctrl/nomadik/pinctrl-ab9540.c
+++ /dev/null
@@ -1,486 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2012
- *
- * Author: Patrice Chotard <patrice.chotard@stericsson.com> for ST-Ericsson.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/gpio.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/mfd/abx500/ab8500.h>
-#include "pinctrl-abx500.h"
-
-/* All the pins that can be used for GPIO and some other functions */
-#define ABX500_GPIO(offset) (offset)
-
-#define AB9540_PIN_R4 ABX500_GPIO(1)
-#define AB9540_PIN_V3 ABX500_GPIO(2)
-#define AB9540_PIN_T4 ABX500_GPIO(3)
-#define AB9540_PIN_T5 ABX500_GPIO(4)
-/* hole */
-#define AB9540_PIN_B18 ABX500_GPIO(10)
-#define AB9540_PIN_C18 ABX500_GPIO(11)
-/* hole */
-#define AB9540_PIN_D18 ABX500_GPIO(13)
-#define AB9540_PIN_B19 ABX500_GPIO(14)
-#define AB9540_PIN_C19 ABX500_GPIO(15)
-#define AB9540_PIN_D19 ABX500_GPIO(16)
-#define AB9540_PIN_R3 ABX500_GPIO(17)
-#define AB9540_PIN_T2 ABX500_GPIO(18)
-#define AB9540_PIN_U2 ABX500_GPIO(19)
-#define AB9540_PIN_V2 ABX500_GPIO(20)
-#define AB9540_PIN_N17 ABX500_GPIO(21)
-#define AB9540_PIN_N16 ABX500_GPIO(22)
-#define AB9540_PIN_M19 ABX500_GPIO(23)
-#define AB9540_PIN_T3 ABX500_GPIO(24)
-#define AB9540_PIN_W2 ABX500_GPIO(25)
-/* hole */
-#define AB9540_PIN_H4 ABX500_GPIO(27)
-#define AB9540_PIN_F1 ABX500_GPIO(28)
-#define AB9540_PIN_F4 ABX500_GPIO(29)
-#define AB9540_PIN_F2 ABX500_GPIO(30)
-#define AB9540_PIN_E4 ABX500_GPIO(31)
-#define AB9540_PIN_F3 ABX500_GPIO(32)
-/* hole */
-#define AB9540_PIN_J13 ABX500_GPIO(34)
-/* hole */
-#define AB9540_PIN_L17 ABX500_GPIO(40)
-#define AB9540_PIN_L16 ABX500_GPIO(41)
-#define AB9540_PIN_W3 ABX500_GPIO(42)
-#define AB9540_PIN_N4 ABX500_GPIO(50)
-#define AB9540_PIN_G12 ABX500_GPIO(51)
-#define AB9540_PIN_E17 ABX500_GPIO(52)
-#define AB9540_PIN_D11 ABX500_GPIO(53)
-#define AB9540_PIN_M18 ABX500_GPIO(54)
-
-/* indicates the highest GPIO number */
-#define AB9540_GPIO_MAX_NUMBER 54
-
-/*
- * The names of the pins are denoted by GPIO number and ball name, even
- * though they can be used for other things than GPIO, this is the first
- * column in the table of the data sheet and often used on schematics and
- * such.
- */
-static const struct pinctrl_pin_desc ab9540_pins[] = {
- PINCTRL_PIN(AB9540_PIN_R4, "GPIO1_R4"),
- PINCTRL_PIN(AB9540_PIN_V3, "GPIO2_V3"),
- PINCTRL_PIN(AB9540_PIN_T4, "GPIO3_T4"),
- PINCTRL_PIN(AB9540_PIN_T5, "GPIO4_T5"),
- /* hole */
- PINCTRL_PIN(AB9540_PIN_B18, "GPIO10_B18"),
- PINCTRL_PIN(AB9540_PIN_C18, "GPIO11_C18"),
- /* hole */
- PINCTRL_PIN(AB9540_PIN_D18, "GPIO13_D18"),
- PINCTRL_PIN(AB9540_PIN_B19, "GPIO14_B19"),
- PINCTRL_PIN(AB9540_PIN_C19, "GPIO15_C19"),
- PINCTRL_PIN(AB9540_PIN_D19, "GPIO16_D19"),
- PINCTRL_PIN(AB9540_PIN_R3, "GPIO17_R3"),
- PINCTRL_PIN(AB9540_PIN_T2, "GPIO18_T2"),
- PINCTRL_PIN(AB9540_PIN_U2, "GPIO19_U2"),
- PINCTRL_PIN(AB9540_PIN_V2, "GPIO20_V2"),
- PINCTRL_PIN(AB9540_PIN_N17, "GPIO21_N17"),
- PINCTRL_PIN(AB9540_PIN_N16, "GPIO22_N16"),
- PINCTRL_PIN(AB9540_PIN_M19, "GPIO23_M19"),
- PINCTRL_PIN(AB9540_PIN_T3, "GPIO24_T3"),
- PINCTRL_PIN(AB9540_PIN_W2, "GPIO25_W2"),
- /* hole */
- PINCTRL_PIN(AB9540_PIN_H4, "GPIO27_H4"),
- PINCTRL_PIN(AB9540_PIN_F1, "GPIO28_F1"),
- PINCTRL_PIN(AB9540_PIN_F4, "GPIO29_F4"),
- PINCTRL_PIN(AB9540_PIN_F2, "GPIO30_F2"),
- PINCTRL_PIN(AB9540_PIN_E4, "GPIO31_E4"),
- PINCTRL_PIN(AB9540_PIN_F3, "GPIO32_F3"),
- /* hole */
- PINCTRL_PIN(AB9540_PIN_J13, "GPIO34_J13"),
- /* hole */
- PINCTRL_PIN(AB9540_PIN_L17, "GPIO40_L17"),
- PINCTRL_PIN(AB9540_PIN_L16, "GPIO41_L16"),
- PINCTRL_PIN(AB9540_PIN_W3, "GPIO42_W3"),
- PINCTRL_PIN(AB9540_PIN_N4, "GPIO50_N4"),
- PINCTRL_PIN(AB9540_PIN_G12, "GPIO51_G12"),
- PINCTRL_PIN(AB9540_PIN_E17, "GPIO52_E17"),
- PINCTRL_PIN(AB9540_PIN_D11, "GPIO53_D11"),
- PINCTRL_PIN(AB9540_PIN_M18, "GPIO60_M18"),
-};
-
-/*
- * Maps local GPIO offsets to local pin numbers
- */
-static const struct abx500_pinrange ab9540_pinranges[] = {
- ABX500_PINRANGE(1, 4, ABX500_ALT_A),
- ABX500_PINRANGE(10, 2, ABX500_DEFAULT),
- ABX500_PINRANGE(13, 1, ABX500_DEFAULT),
- ABX500_PINRANGE(14, 12, ABX500_ALT_A),
- ABX500_PINRANGE(27, 6, ABX500_ALT_A),
- ABX500_PINRANGE(34, 1, ABX500_ALT_A),
- ABX500_PINRANGE(40, 3, ABX500_ALT_A),
- ABX500_PINRANGE(50, 1, ABX500_DEFAULT),
- ABX500_PINRANGE(51, 3, ABX500_ALT_A),
- ABX500_PINRANGE(54, 1, ABX500_DEFAULT),
-};
-
-/*
- * Read the pin group names like this:
- * sysclkreq2_d_1 = first groups of pins for sysclkreq2 on default function
- *
- * The groups are arranged as sets per altfunction column, so we can
- * mux in one group at a time by selecting the same altfunction for them
- * all. When functions require pins on different altfunctions, you need
- * to combine several groups.
- */
-
-/* default column */
-static const unsigned sysclkreq2_d_1_pins[] = { AB9540_PIN_R4 };
-static const unsigned sysclkreq3_d_1_pins[] = { AB9540_PIN_V3 };
-static const unsigned sysclkreq4_d_1_pins[] = { AB9540_PIN_T4 };
-static const unsigned sysclkreq6_d_1_pins[] = { AB9540_PIN_T5 };
-static const unsigned gpio10_d_1_pins[] = { AB9540_PIN_B18 };
-static const unsigned gpio11_d_1_pins[] = { AB9540_PIN_C18 };
-static const unsigned gpio13_d_1_pins[] = { AB9540_PIN_D18 };
-static const unsigned pwmout1_d_1_pins[] = { AB9540_PIN_B19 };
-static const unsigned pwmout2_d_1_pins[] = { AB9540_PIN_C19 };
-static const unsigned pwmout3_d_1_pins[] = { AB9540_PIN_D19 };
-/* audio data interface 1*/
-static const unsigned adi1_d_1_pins[] = { AB9540_PIN_R3, AB9540_PIN_T2,
- AB9540_PIN_U2, AB9540_PIN_V2 };
-/* USBUICC */
-static const unsigned usbuicc_d_1_pins[] = { AB9540_PIN_N17, AB9540_PIN_N16,
- AB9540_PIN_M19 };
-static const unsigned sysclkreq7_d_1_pins[] = { AB9540_PIN_T3 };
-static const unsigned sysclkreq8_d_1_pins[] = { AB9540_PIN_W2 };
-/* Digital microphone 1 and 2 */
-static const unsigned dmic12_d_1_pins[] = { AB9540_PIN_H4, AB9540_PIN_F1 };
-/* Digital microphone 3 and 4 */
-static const unsigned dmic34_d_1_pins[] = { AB9540_PIN_F4, AB9540_PIN_F2 };
-/* Digital microphone 5 and 6 */
-static const unsigned dmic56_d_1_pins[] = { AB9540_PIN_E4, AB9540_PIN_F3 };
-static const unsigned extcpena_d_1_pins[] = { AB9540_PIN_J13 };
-/* modem SDA/SCL */
-static const unsigned modsclsda_d_1_pins[] = { AB9540_PIN_L17, AB9540_PIN_L16 };
-static const unsigned sysclkreq5_d_1_pins[] = { AB9540_PIN_W3 };
-static const unsigned gpio50_d_1_pins[] = { AB9540_PIN_N4 };
-static const unsigned batremn_d_1_pins[] = { AB9540_PIN_G12 };
-static const unsigned resethw_d_1_pins[] = { AB9540_PIN_E17 };
-static const unsigned service_d_1_pins[] = { AB9540_PIN_D11 };
-static const unsigned gpio60_d_1_pins[] = { AB9540_PIN_M18 };
-
-/* Altfunction A column */
-static const unsigned gpio1_a_1_pins[] = { AB9540_PIN_R4 };
-static const unsigned gpio2_a_1_pins[] = { AB9540_PIN_V3 };
-static const unsigned gpio3_a_1_pins[] = { AB9540_PIN_T4 };
-static const unsigned gpio4_a_1_pins[] = { AB9540_PIN_T5 };
-static const unsigned hiqclkena_a_1_pins[] = { AB9540_PIN_B18 };
-static const unsigned pdmclk_a_1_pins[] = { AB9540_PIN_C18 };
-static const unsigned uartdata_a_1_pins[] = { AB9540_PIN_D18, AB9540_PIN_N4 };
-static const unsigned gpio14_a_1_pins[] = { AB9540_PIN_B19 };
-static const unsigned gpio15_a_1_pins[] = { AB9540_PIN_C19 };
-static const unsigned gpio16_a_1_pins[] = { AB9540_PIN_D19 };
-static const unsigned gpio17_a_1_pins[] = { AB9540_PIN_R3 };
-static const unsigned gpio18_a_1_pins[] = { AB9540_PIN_T2 };
-static const unsigned gpio19_a_1_pins[] = { AB9540_PIN_U2 };
-static const unsigned gpio20_a_1_pins[] = { AB9540_PIN_V2 };
-static const unsigned gpio21_a_1_pins[] = { AB9540_PIN_N17 };
-static const unsigned gpio22_a_1_pins[] = { AB9540_PIN_N16 };
-static const unsigned gpio23_a_1_pins[] = { AB9540_PIN_M19 };
-static const unsigned gpio24_a_1_pins[] = { AB9540_PIN_T3 };
-static const unsigned gpio25_a_1_pins[] = { AB9540_PIN_W2 };
-static const unsigned gpio27_a_1_pins[] = { AB9540_PIN_H4 };
-static const unsigned gpio28_a_1_pins[] = { AB9540_PIN_F1 };
-static const unsigned gpio29_a_1_pins[] = { AB9540_PIN_F4 };
-static const unsigned gpio30_a_1_pins[] = { AB9540_PIN_F2 };
-static const unsigned gpio31_a_1_pins[] = { AB9540_PIN_E4 };
-static const unsigned gpio32_a_1_pins[] = { AB9540_PIN_F3 };
-static const unsigned gpio34_a_1_pins[] = { AB9540_PIN_J13 };
-static const unsigned gpio40_a_1_pins[] = { AB9540_PIN_L17 };
-static const unsigned gpio41_a_1_pins[] = { AB9540_PIN_L16 };
-static const unsigned gpio42_a_1_pins[] = { AB9540_PIN_W3 };
-static const unsigned gpio51_a_1_pins[] = { AB9540_PIN_G12 };
-static const unsigned gpio52_a_1_pins[] = { AB9540_PIN_E17 };
-static const unsigned gpio53_a_1_pins[] = { AB9540_PIN_D11 };
-static const unsigned usbuiccpd_a_1_pins[] = { AB9540_PIN_M18 };
-
-/* Altfunction B colum */
-static const unsigned pdmdata_b_1_pins[] = { AB9540_PIN_B18 };
-static const unsigned pwmextvibra1_b_1_pins[] = { AB9540_PIN_D18 };
-static const unsigned pwmextvibra2_b_1_pins[] = { AB9540_PIN_N4 };
-
-/* Altfunction C column */
-static const unsigned usbvdat_c_1_pins[] = { AB9540_PIN_D18 };
-
-#define AB9540_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \
- .npins = ARRAY_SIZE(a##_pins), .altsetting = b }
-
-static const struct abx500_pingroup ab9540_groups[] = {
- /* default column */
- AB9540_PIN_GROUP(sysclkreq2_d_1, ABX500_DEFAULT),
- AB9540_PIN_GROUP(sysclkreq3_d_1, ABX500_DEFAULT),
- AB9540_PIN_GROUP(sysclkreq4_d_1, ABX500_DEFAULT),
- AB9540_PIN_GROUP(sysclkreq6_d_1, ABX500_DEFAULT),
- AB9540_PIN_GROUP(gpio10_d_1, ABX500_DEFAULT),
- AB9540_PIN_GROUP(gpio11_d_1, ABX500_DEFAULT),
- AB9540_PIN_GROUP(gpio13_d_1, ABX500_DEFAULT),
- AB9540_PIN_GROUP(pwmout1_d_1, ABX500_DEFAULT),
- AB9540_PIN_GROUP(pwmout2_d_1, ABX500_DEFAULT),
- AB9540_PIN_GROUP(pwmout3_d_1, ABX500_DEFAULT),
- AB9540_PIN_GROUP(adi1_d_1, ABX500_DEFAULT),
- AB9540_PIN_GROUP(usbuicc_d_1, ABX500_DEFAULT),
- AB9540_PIN_GROUP(sysclkreq7_d_1, ABX500_DEFAULT),
- AB9540_PIN_GROUP(sysclkreq8_d_1, ABX500_DEFAULT),
- AB9540_PIN_GROUP(dmic12_d_1, ABX500_DEFAULT),
- AB9540_PIN_GROUP(dmic34_d_1, ABX500_DEFAULT),
- AB9540_PIN_GROUP(dmic56_d_1, ABX500_DEFAULT),
- AB9540_PIN_GROUP(extcpena_d_1, ABX500_DEFAULT),
- AB9540_PIN_GROUP(modsclsda_d_1, ABX500_DEFAULT),
- AB9540_PIN_GROUP(sysclkreq5_d_1, ABX500_DEFAULT),
- AB9540_PIN_GROUP(gpio50_d_1, ABX500_DEFAULT),
- AB9540_PIN_GROUP(batremn_d_1, ABX500_DEFAULT),
- AB9540_PIN_GROUP(resethw_d_1, ABX500_DEFAULT),
- AB9540_PIN_GROUP(service_d_1, ABX500_DEFAULT),
- AB9540_PIN_GROUP(gpio60_d_1, ABX500_DEFAULT),
-
- /* Altfunction A column */
- AB9540_PIN_GROUP(gpio1_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(gpio2_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(gpio3_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(gpio4_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(hiqclkena_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(pdmclk_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(uartdata_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(gpio14_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(gpio15_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(gpio16_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(gpio17_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(gpio18_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(gpio19_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(gpio20_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(gpio21_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(gpio22_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(gpio23_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(gpio24_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(gpio25_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(gpio27_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(gpio28_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(gpio29_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(gpio30_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(gpio31_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(gpio32_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(gpio34_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(gpio40_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(gpio41_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(gpio42_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(gpio51_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(gpio52_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(gpio53_a_1, ABX500_ALT_A),
- AB9540_PIN_GROUP(usbuiccpd_a_1, ABX500_ALT_A),
-
- /* Altfunction B column */
- AB9540_PIN_GROUP(pdmdata_b_1, ABX500_ALT_B),
- AB9540_PIN_GROUP(pwmextvibra1_b_1, ABX500_ALT_B),
- AB9540_PIN_GROUP(pwmextvibra2_b_1, ABX500_ALT_B),
-
- /* Altfunction C column */
- AB9540_PIN_GROUP(usbvdat_c_1, ABX500_ALT_C),
-};
-
-/* We use this macro to define the groups applicable to a function */
-#define AB9540_FUNC_GROUPS(a, b...) \
-static const char * const a##_groups[] = { b };
-
-AB9540_FUNC_GROUPS(sysclkreq, "sysclkreq2_d_1", "sysclkreq3_d_1",
- "sysclkreq4_d_1", "sysclkreq5_d_1", "sysclkreq6_d_1",
- "sysclkreq7_d_1", "sysclkreq8_d_1");
-AB9540_FUNC_GROUPS(gpio, "gpio1_a_1", "gpio2_a_1", "gpio3_a_1", "gpio4_a_1",
- "gpio10_d_1", "gpio11_d_1", "gpio13_d_1", "gpio14_a_1",
- "gpio15_a_1", "gpio16_a_1", "gpio17_a_1", "gpio18_a_1",
- "gpio19_a_1", "gpio20_a_1", "gpio21_a_1", "gpio22_a_1",
- "gpio23_a_1", "gpio24_a_1", "gpio25_a_1", "gpio27_a_1",
- "gpio28_a_1", "gpio29_a_1", "gpio30_a_1", "gpio31_a_1",
- "gpio32_a_1", "gpio34_a_1", "gpio40_a_1", "gpio41_a_1",
- "gpio42_a_1", "gpio50_d_1", "gpio51_a_1", "gpio52_a_1",
- "gpio53_a_1", "gpio60_d_1");
-AB9540_FUNC_GROUPS(pwmout, "pwmout1_d_1", "pwmout2_d_1", "pwmout3_d_1");
-AB9540_FUNC_GROUPS(adi1, "adi1_d_1");
-AB9540_FUNC_GROUPS(usbuicc, "usbuicc_d_1", "usbuiccpd_a_1");
-AB9540_FUNC_GROUPS(dmic, "dmic12_d_1", "dmic34_d_1", "dmic56_d_1");
-AB9540_FUNC_GROUPS(extcpena, "extcpena_d_1");
-AB9540_FUNC_GROUPS(modsclsda, "modsclsda_d_1");
-AB9540_FUNC_GROUPS(batremn, "batremn_d_1");
-AB9540_FUNC_GROUPS(resethw, "resethw_d_1");
-AB9540_FUNC_GROUPS(service, "service_d_1");
-AB9540_FUNC_GROUPS(hiqclkena, "hiqclkena_a_1");
-AB9540_FUNC_GROUPS(pdm, "pdmdata_b_1", "pdmclk_a_1");
-AB9540_FUNC_GROUPS(uartdata, "uartdata_a_1");
-AB9540_FUNC_GROUPS(pwmextvibra, "pwmextvibra1_b_1", "pwmextvibra2_b_1");
-AB9540_FUNC_GROUPS(usbvdat, "usbvdat_c_1");
-
-#define FUNCTION(fname) \
- { \
- .name = #fname, \
- .groups = fname##_groups, \
- .ngroups = ARRAY_SIZE(fname##_groups), \
- }
-
-static const struct abx500_function ab9540_functions[] = {
- FUNCTION(sysclkreq),
- FUNCTION(gpio),
- FUNCTION(pwmout),
- FUNCTION(adi1),
- FUNCTION(usbuicc),
- FUNCTION(dmic),
- FUNCTION(extcpena),
- FUNCTION(modsclsda),
- FUNCTION(batremn),
- FUNCTION(resethw),
- FUNCTION(service),
- FUNCTION(hiqclkena),
- FUNCTION(pdm),
- FUNCTION(uartdata),
- FUNCTION(pwmextvibra),
- FUNCTION(usbvdat),
-};
-
-/*
- * this table translates what's is in the AB9540 specification regarding the
- * balls alternate functions (as for DB, default, ALT_A, ALT_B and ALT_C).
- * ALTERNATE_FUNCTIONS(GPIO_NUMBER, GPIOSEL bit, ALTERNATFUNC bit1,
- * ALTERNATEFUNC bit2, ALTA val, ALTB val, ALTC val),
- *
- * example :
- *
- * ALTERNATE_FUNCTIONS(13, 4, 3, 4, 1, 0, 2),
- * means that pin AB9540_PIN_D18 (pin 13) supports 4 mux (default/ALT_A,
- * ALT_B and ALT_C), so GPIOSEL and ALTERNATFUNC registers are used to
- * select the mux. ALTA, ALTB and ALTC val indicates values to write in
- * ALTERNATFUNC register. We need to specifies these values as SOC
- * designers didn't apply the same logic on how to select mux in the
- * ABx500 family.
- *
- * As this pins supports at least ALT_B mux, default mux is
- * selected by writing 1 in GPIOSEL bit :
- *
- * | GPIOSEL bit=4 | alternatfunc bit2=4 | alternatfunc bit1=3
- * default | 1 | 0 | 0
- * alt_A | 0 | 0 | 1
- * alt_B | 0 | 0 | 0
- * alt_C | 0 | 1 | 0
- *
- * ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED),
- * means that pin AB9540_PIN_R4 (pin 1) supports 2 mux, so only GPIOSEL
- * register is used to select the mux. As this pins doesn't support at
- * least ALT_B mux, default mux is by writing 0 in GPIOSEL bit :
- *
- * | GPIOSEL bit=0 | alternatfunc bit2= | alternatfunc bit1=
- * default | 0 | 0 | 0
- * alt_A | 1 | 0 | 0
- */
-
-static struct
-alternate_functions ab9540alternate_functions[AB9540_GPIO_MAX_NUMBER + 1] = {
- /* GPIOSEL1 - bits 4-7 are reserved */
- ALTERNATE_FUNCTIONS(0, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO0 */
- ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO1, altA controlled by bit 0 */
- ALTERNATE_FUNCTIONS(2, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO2, altA controlled by bit 1 */
- ALTERNATE_FUNCTIONS(3, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO3, altA controlled by bit 2*/
- ALTERNATE_FUNCTIONS(4, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO4, altA controlled by bit 3*/
- ALTERNATE_FUNCTIONS(5, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO5 */
- ALTERNATE_FUNCTIONS(6, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO6 */
- ALTERNATE_FUNCTIONS(7, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO7 */
- ALTERNATE_FUNCTIONS(8, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO8 */
- /* GPIOSEL2 - bits 0 and 3 are reserved */
- ALTERNATE_FUNCTIONS(9, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO9 */
- ALTERNATE_FUNCTIONS(10, 1, 0, UNUSED, 1, 0, 0), /* GPIO10, altA and altB controlled by bit 0 */
- ALTERNATE_FUNCTIONS(11, 2, 1, UNUSED, 0, 0, 0), /* GPIO11, altA controlled by bit 1 */
- ALTERNATE_FUNCTIONS(12, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO12 */
- ALTERNATE_FUNCTIONS(13, 4, 3, 4, 1, 0, 2), /* GPIO13, altA altB and altC controlled by bit 3 and 4 */
- ALTERNATE_FUNCTIONS(14, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */
- ALTERNATE_FUNCTIONS(15, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO15, altA controlled by bit 6 */
- ALTERNATE_FUNCTIONS(16, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO16, altA controlled by bit 7 */
- /* GPIOSEL3 - bit 1-3 reserved
- * pins 17 to 20 are special case, only bit 0 is used to select
- * alternate function for these 4 pins.
- * bits 1 to 3 are reserved
- */
- ALTERNATE_FUNCTIONS(17, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO17, altA controlled by bit 0 */
- ALTERNATE_FUNCTIONS(18, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO18, altA controlled by bit 0 */
- ALTERNATE_FUNCTIONS(19, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO19, altA controlled by bit 0 */
- ALTERNATE_FUNCTIONS(20, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO20, altA controlled by bit 0 */
- ALTERNATE_FUNCTIONS(21, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO21, altA controlled by bit 4 */
- ALTERNATE_FUNCTIONS(22, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO22, altA controlled by bit 5 */
- ALTERNATE_FUNCTIONS(23, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO23, altA controlled by bit 6 */
- ALTERNATE_FUNCTIONS(24, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO24, altA controlled by bit 7 */
- /* GPIOSEL4 - bit 1 reserved */
- ALTERNATE_FUNCTIONS(25, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO25, altA controlled by bit 0 */
- ALTERNATE_FUNCTIONS(26, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO26 */
- ALTERNATE_FUNCTIONS(27, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO27, altA controlled by bit 2 */
- ALTERNATE_FUNCTIONS(28, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO28, altA controlled by bit 3 */
- ALTERNATE_FUNCTIONS(29, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO29, altA controlled by bit 4 */
- ALTERNATE_FUNCTIONS(30, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO30, altA controlled by bit 5 */
- ALTERNATE_FUNCTIONS(31, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO31, altA controlled by bit 6 */
- ALTERNATE_FUNCTIONS(32, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO32, altA controlled by bit 7 */
- /* GPIOSEL5 - bit 0, 2-6 are reserved */
- ALTERNATE_FUNCTIONS(33, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO33 */
- ALTERNATE_FUNCTIONS(34, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO34, altA controlled by bit 1 */
- ALTERNATE_FUNCTIONS(35, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO35 */
- ALTERNATE_FUNCTIONS(36, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO36 */
- ALTERNATE_FUNCTIONS(37, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO37 */
- ALTERNATE_FUNCTIONS(38, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO38 */
- ALTERNATE_FUNCTIONS(39, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO39 */
- ALTERNATE_FUNCTIONS(40, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO40, altA controlled by bit 7 */
- /* GPIOSEL6 - bit 2-7 are reserved */
- ALTERNATE_FUNCTIONS(41, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO41, altA controlled by bit 0 */
- ALTERNATE_FUNCTIONS(42, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO42, altA controlled by bit 1 */
- ALTERNATE_FUNCTIONS(43, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO43 */
- ALTERNATE_FUNCTIONS(44, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO44 */
- ALTERNATE_FUNCTIONS(45, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO45 */
- ALTERNATE_FUNCTIONS(46, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO46 */
- ALTERNATE_FUNCTIONS(47, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO47 */
- ALTERNATE_FUNCTIONS(48, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO48 */
- /*
- * GPIOSEL7 - bit 0 and 6-7 are reserved
- * special case with GPIO60, wich is located at offset 5 of gpiosel7
- * don't know why it has been called GPIO60 in AB9540 datasheet,
- * GPIO54 would be logical..., so at SOC point of view we consider
- * GPIO60 = GPIO54
- */
- ALTERNATE_FUNCTIONS(49, 0, UNUSED, UNUSED, 0, 0, 0), /* no GPIO49 */
- ALTERNATE_FUNCTIONS(50, 1, 2, UNUSED, 1, 0, 0), /* GPIO50, altA and altB controlled by bit 1 */
- ALTERNATE_FUNCTIONS(51, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO51, altA controlled by bit 2 */
- ALTERNATE_FUNCTIONS(52, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO52, altA controlled by bit 3 */
- ALTERNATE_FUNCTIONS(53, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO53, altA controlled by bit 4 */
- ALTERNATE_FUNCTIONS(54, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO54 = GPIO60, altA controlled by bit 5 */
-};
-
-static struct abx500_gpio_irq_cluster ab9540_gpio_irq_cluster[] = {
- GPIO_IRQ_CLUSTER(10, 13, AB8500_INT_GPIO10R),
- GPIO_IRQ_CLUSTER(24, 25, AB8500_INT_GPIO24R),
- GPIO_IRQ_CLUSTER(40, 41, AB8500_INT_GPIO40R),
- GPIO_IRQ_CLUSTER(50, 54, AB9540_INT_GPIO50R),
-};
-
-static struct abx500_pinctrl_soc_data ab9540_soc = {
- .gpio_ranges = ab9540_pinranges,
- .gpio_num_ranges = ARRAY_SIZE(ab9540_pinranges),
- .pins = ab9540_pins,
- .npins = ARRAY_SIZE(ab9540_pins),
- .functions = ab9540_functions,
- .nfunctions = ARRAY_SIZE(ab9540_functions),
- .groups = ab9540_groups,
- .ngroups = ARRAY_SIZE(ab9540_groups),
- .alternate_functions = ab9540alternate_functions,
- .gpio_irq_cluster = ab9540_gpio_irq_cluster,
- .ngpio_irq_cluster = ARRAY_SIZE(ab9540_gpio_irq_cluster),
- .irq_gpio_rising_offset = AB8500_INT_GPIO6R,
- .irq_gpio_falling_offset = AB8500_INT_GPIO6F,
- .irq_gpio_factor = 1,
-};
-
-void
-abx500_pinctrl_ab9540_init(struct abx500_pinctrl_soc_data **soc)
-{
- *soc = &ab9540_soc;
-}
diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c
index d56a49e53f56..aa592ef23a29 100644
--- a/drivers/pinctrl/nomadik/pinctrl-abx500.c
+++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c
@@ -38,15 +38,6 @@
#include "../pinctrl-utils.h"
/*
- * The AB9540 and AB8540 GPIO support are extended versions
- * of the AB8500 GPIO support.
- * The AB9540 supports an additional (7th) register so that
- * more GPIO may be configured and used.
- * The AB8540 supports 4 new gpios (GPIOx_VBAT) that have
- * internal pull-up and pull-down capabilities.
- */
-
-/*
* GPIO registers offset
* Bank: 0x10
*/
@@ -56,7 +47,6 @@
#define AB8500_GPIO_SEL4_REG 0x03
#define AB8500_GPIO_SEL5_REG 0x04
#define AB8500_GPIO_SEL6_REG 0x05
-#define AB9540_GPIO_SEL7_REG 0x06
#define AB8500_GPIO_DIR1_REG 0x10
#define AB8500_GPIO_DIR2_REG 0x11
@@ -64,7 +54,6 @@
#define AB8500_GPIO_DIR4_REG 0x13
#define AB8500_GPIO_DIR5_REG 0x14
#define AB8500_GPIO_DIR6_REG 0x15
-#define AB9540_GPIO_DIR7_REG 0x16
#define AB8500_GPIO_OUT1_REG 0x20
#define AB8500_GPIO_OUT2_REG 0x21
@@ -72,7 +61,6 @@
#define AB8500_GPIO_OUT4_REG 0x23
#define AB8500_GPIO_OUT5_REG 0x24
#define AB8500_GPIO_OUT6_REG 0x25
-#define AB9540_GPIO_OUT7_REG 0x26
#define AB8500_GPIO_PUD1_REG 0x30
#define AB8500_GPIO_PUD2_REG 0x31
@@ -80,7 +68,6 @@
#define AB8500_GPIO_PUD4_REG 0x33
#define AB8500_GPIO_PUD5_REG 0x34
#define AB8500_GPIO_PUD6_REG 0x35
-#define AB9540_GPIO_PUD7_REG 0x36
#define AB8500_GPIO_IN1_REG 0x40
#define AB8500_GPIO_IN2_REG 0x41
@@ -88,14 +75,7 @@
#define AB8500_GPIO_IN4_REG 0x43
#define AB8500_GPIO_IN5_REG 0x44
#define AB8500_GPIO_IN6_REG 0x45
-#define AB9540_GPIO_IN7_REG 0x46
-#define AB8540_GPIO_VINSEL_REG 0x47
-#define AB8540_GPIO_PULL_UPDOWN_REG 0x48
#define AB8500_GPIO_ALTFUN_REG 0x50
-#define AB8540_GPIO_PULL_UPDOWN_MASK 0x03
-#define AB8540_GPIO_VINSEL_MASK 0x03
-#define AB8540_GPIOX_VBAT_START 51
-#define AB8540_GPIOX_VBAT_END 54
#define ABX500_GPIO_INPUT 0
#define ABX500_GPIO_OUTPUT 1
@@ -192,94 +172,11 @@ static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
dev_err(pct->dev, "%s write failed (%d)\n", __func__, ret);
}
-#ifdef CONFIG_DEBUG_FS
-static int abx500_get_pull_updown(struct abx500_pinctrl *pct, int offset,
- enum abx500_gpio_pull_updown *pull_updown)
-{
- u8 pos;
- u8 val;
- int ret;
- struct pullud *pullud;
-
- if (!pct->soc->pullud) {
- dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature",
- __func__);
- ret = -EPERM;
- goto out;
- }
-
- pullud = pct->soc->pullud;
-
- if ((offset < pullud->first_pin)
- || (offset > pullud->last_pin)) {
- ret = -EINVAL;
- goto out;
- }
-
- ret = abx500_get_register_interruptible(pct->dev,
- AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG, &val);
-
- pos = (offset - pullud->first_pin) << 1;
- *pull_updown = (val >> pos) & AB8540_GPIO_PULL_UPDOWN_MASK;
-
-out:
- if (ret < 0)
- dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
-
- return ret;
-}
-#endif
-
-static int abx500_set_pull_updown(struct abx500_pinctrl *pct,
- int offset, enum abx500_gpio_pull_updown val)
-{
- u8 pos;
- int ret;
- struct pullud *pullud;
-
- if (!pct->soc->pullud) {
- dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature",
- __func__);
- ret = -EPERM;
- goto out;
- }
-
- pullud = pct->soc->pullud;
-
- if ((offset < pullud->first_pin)
- || (offset > pullud->last_pin)) {
- ret = -EINVAL;
- goto out;
- }
- pos = (offset - pullud->first_pin) << 1;
-
- ret = abx500_mask_and_set_register_interruptible(pct->dev,
- AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG,
- AB8540_GPIO_PULL_UPDOWN_MASK << pos, val << pos);
-
-out:
- if (ret < 0)
- dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
-
- return ret;
-}
-
-static bool abx500_pullud_supported(struct gpio_chip *chip, unsigned gpio)
-{
- struct abx500_pinctrl *pct = gpiochip_get_data(chip);
- struct pullud *pullud = pct->soc->pullud;
-
- return (pullud &&
- gpio >= pullud->first_pin &&
- gpio <= pullud->last_pin);
-}
-
static int abx500_gpio_direction_output(struct gpio_chip *chip,
unsigned offset,
int val)
{
struct abx500_pinctrl *pct = gpiochip_get_data(chip);
- unsigned gpio;
int ret;
/* set direction as output */
@@ -295,16 +192,7 @@ static int abx500_gpio_direction_output(struct gpio_chip *chip,
AB8500_GPIO_PUD1_REG,
offset,
ABX500_GPIO_PULL_NONE);
- if (ret < 0)
- goto out;
- /* if supported, disable both pull down and pull up */
- gpio = offset + 1;
- if (abx500_pullud_supported(chip, gpio)) {
- ret = abx500_set_pull_updown(pct,
- gpio,
- ABX500_GPIO_PULL_NONE);
- }
out:
if (ret < 0) {
dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
@@ -570,7 +458,6 @@ static void abx500_gpio_dbg_show_one(struct seq_file *s,
int mode = -1;
bool is_out;
bool pd;
- enum abx500_gpio_pull_updown pud = 0;
int ret;
const char *modes[] = {
@@ -597,20 +484,12 @@ static void abx500_gpio_dbg_show_one(struct seq_file *s,
is_out ? "out" : "in ");
if (!is_out) {
- if (abx500_pullud_supported(chip, offset)) {
- ret = abx500_get_pull_updown(pct, offset, &pud);
- if (ret < 0)
- goto out;
-
- seq_printf(s, " %-9s", pull_up_down[pud]);
- } else {
- ret = abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG,
- gpio_offset, &pd);
- if (ret < 0)
- goto out;
+ ret = abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG,
+ gpio_offset, &pd);
+ if (ret < 0)
+ goto out;
- seq_printf(s, " %-9s", pull_up_down[pd]);
- }
+ seq_printf(s, " %-9s", pull_up_down[pd]);
} else
seq_printf(s, " %-9s", chip->get(chip, offset) ? "hi" : "lo");
@@ -994,23 +873,11 @@ static int abx500_pin_config_set(struct pinctrl_dev *pctldev,
ret = abx500_gpio_direction_input(chip, offset);
if (ret < 0)
goto out;
- /*
- * Some chips only support pull down, while some
- * actually support both pull up and pull down. Such
- * chips have a "pullud" range specified for the pins
- * that support both features. If the pin is not
- * within that range, we fall back to the old bit set
- * that only support pull down.
- */
- if (abx500_pullud_supported(chip, pin))
- ret = abx500_set_pull_updown(pct,
- pin,
- ABX500_GPIO_PULL_NONE);
- else
- /* Chip only supports pull down */
- ret = abx500_gpio_set_bits(chip,
- AB8500_GPIO_PUD1_REG, offset,
- ABX500_GPIO_PULL_NONE);
+
+ /* Chip only supports pull down */
+ ret = abx500_gpio_set_bits(chip,
+ AB8500_GPIO_PUD1_REG, offset,
+ ABX500_GPIO_PULL_NONE);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
@@ -1020,25 +887,13 @@ static int abx500_pin_config_set(struct pinctrl_dev *pctldev,
/*
* if argument = 1 set the pull down
* else clear the pull down
- * Some chips only support pull down, while some
- * actually support both pull up and pull down. Such
- * chips have a "pullud" range specified for the pins
- * that support both features. If the pin is not
- * within that range, we fall back to the old bit set
- * that only support pull down.
+ * Chip only supports pull down
*/
- if (abx500_pullud_supported(chip, pin))
- ret = abx500_set_pull_updown(pct,
- pin,
- argument ? ABX500_GPIO_PULL_DOWN :
- ABX500_GPIO_PULL_NONE);
- else
- /* Chip only supports pull down */
- ret = abx500_gpio_set_bits(chip,
- AB8500_GPIO_PUD1_REG,
- offset,
- argument ? ABX500_GPIO_PULL_DOWN :
- ABX500_GPIO_PULL_NONE);
+ ret = abx500_gpio_set_bits(chip,
+ AB8500_GPIO_PUD1_REG,
+ offset,
+ argument ? ABX500_GPIO_PULL_DOWN :
+ ABX500_GPIO_PULL_NONE);
break;
case PIN_CONFIG_BIAS_PULL_UP:
@@ -1050,18 +905,6 @@ static int abx500_pin_config_set(struct pinctrl_dev *pctldev,
* else clear the pull up
*/
ret = abx500_gpio_direction_input(chip, offset);
- /*
- * Some chips only support pull down, while some
- * actually support both pull up and pull down. Such
- * chips have a "pullud" range specified for the pins
- * that support both features. If the pin is not
- * within that range, do nothing
- */
- if (abx500_pullud_supported(chip, pin))
- ret = abx500_set_pull_updown(pct,
- pin,
- argument ? ABX500_GPIO_PULL_UP :
- ABX500_GPIO_PULL_NONE);
break;
case PIN_CONFIG_OUTPUT:
@@ -1136,8 +979,6 @@ static int abx500_get_gpio_num(struct abx500_pinctrl_soc_data *soc)
static const struct of_device_id abx500_gpio_match[] = {
{ .compatible = "stericsson,ab8500-gpio", .data = (void *)PINCTRL_AB8500, },
{ .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, },
- { .compatible = "stericsson,ab8540-gpio", .data = (void *)PINCTRL_AB8540, },
- { .compatible = "stericsson,ab9540-gpio", .data = (void *)PINCTRL_AB9540, },
{ }
};
@@ -1177,12 +1018,6 @@ static int abx500_gpio_probe(struct platform_device *pdev)
case PINCTRL_AB8500:
abx500_pinctrl_ab8500_init(&pct->soc);
break;
- case PINCTRL_AB8540:
- abx500_pinctrl_ab8540_init(&pct->soc);
- break;
- case PINCTRL_AB9540:
- abx500_pinctrl_ab9540_init(&pct->soc);
- break;
case PINCTRL_AB8505:
abx500_pinctrl_ab8505_init(&pct->soc);
break;
diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.h b/drivers/pinctrl/nomadik/pinctrl-abx500.h
index 43f9b718a8ef..90bb12fe8073 100644
--- a/drivers/pinctrl/nomadik/pinctrl-abx500.h
+++ b/drivers/pinctrl/nomadik/pinctrl-abx500.h
@@ -4,9 +4,7 @@
/* Package definitions */
#define PINCTRL_AB8500 0
-#define PINCTRL_AB8540 1
-#define PINCTRL_AB9540 2
-#define PINCTRL_AB8505 3
+#define PINCTRL_AB8505 1
/* pins alternate function */
enum abx500_pin_func {
@@ -96,17 +94,6 @@ struct alternate_functions {
u8 altc_val;
};
-/**
- * struct pullud - specific pull up/down feature
- * @first_pin: The pin number of the first pins which support
- * specific pull up/down
- * @last_pin: The pin number of the last pins
- */
-struct pullud {
- unsigned first_pin;
- unsigned last_pin;
-};
-
#define GPIO_IRQ_CLUSTER(a, b, c) \
{ \
.start = a, \
@@ -162,8 +149,6 @@ struct abx500_pinrange {
* @ngroups: The number of entries in @groups.
* @alternate_functions: array describing pins which supports alternate and
* how to set it.
- * @pullud: array describing pins which supports pull up/down
- * specific registers.
* @gpio_irq_cluster: An array of GPIO interrupt capable for this SoC
* @ngpio_irq_cluster: The number of GPIO inetrrupt capable for this SoC
* @irq_gpio_rising_offset: Interrupt offset used as base to compute specific
@@ -184,7 +169,6 @@ struct abx500_pinctrl_soc_data {
const struct abx500_pingroup *groups;
unsigned ngroups;
struct alternate_functions *alternate_functions;
- struct pullud *pullud;
struct abx500_gpio_irq_cluster *gpio_irq_cluster;
unsigned ngpio_irq_cluster;
int irq_gpio_rising_offset;
@@ -205,32 +189,6 @@ abx500_pinctrl_ab8500_init(struct abx500_pinctrl_soc_data **soc)
#endif
-#ifdef CONFIG_PINCTRL_AB8540
-
-void abx500_pinctrl_ab8540_init(struct abx500_pinctrl_soc_data **soc);
-
-#else
-
-static inline void
-abx500_pinctrl_ab8540_init(struct abx500_pinctrl_soc_data **soc)
-{
-}
-
-#endif
-
-#ifdef CONFIG_PINCTRL_AB9540
-
-void abx500_pinctrl_ab9540_init(struct abx500_pinctrl_soc_data **soc);
-
-#else
-
-static inline void
-abx500_pinctrl_ab9540_init(struct abx500_pinctrl_soc_data **soc)
-{
-}
-
-#endif
-
#ifdef CONFIG_PINCTRL_AB8505
void abx500_pinctrl_ab8505_init(struct abx500_pinctrl_soc_data **soc);
diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik-db8540.c b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8540.c
deleted file mode 100644
index ae3ac7b799a6..000000000000
--- a/drivers/pinctrl/nomadik/pinctrl-nomadik-db8540.c
+++ /dev/null
@@ -1,1243 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/kernel.h>
-#include <linux/pinctrl/pinctrl.h>
-#include "pinctrl-nomadik.h"
-
-/* All the pins that can be used for GPIO and some other functions */
-#define _GPIO(offset) (offset)
-
-#define DB8540_PIN_AH6 _GPIO(0)
-#define DB8540_PIN_AG7 _GPIO(1)
-#define DB8540_PIN_AF2 _GPIO(2)
-#define DB8540_PIN_AD3 _GPIO(3)
-#define DB8540_PIN_AF6 _GPIO(4)
-#define DB8540_PIN_AG6 _GPIO(5)
-#define DB8540_PIN_AD5 _GPIO(6)
-#define DB8540_PIN_AF7 _GPIO(7)
-#define DB8540_PIN_AG5 _GPIO(8)
-#define DB8540_PIN_AH5 _GPIO(9)
-#define DB8540_PIN_AE4 _GPIO(10)
-#define DB8540_PIN_AD1 _GPIO(11)
-#define DB8540_PIN_AD2 _GPIO(12)
-#define DB8540_PIN_AC2 _GPIO(13)
-#define DB8540_PIN_AC4 _GPIO(14)
-#define DB8540_PIN_AC3 _GPIO(15)
-#define DB8540_PIN_AH7 _GPIO(16)
-#define DB8540_PIN_AE7 _GPIO(17)
-/* Hole */
-#define DB8540_PIN_AF8 _GPIO(22)
-#define DB8540_PIN_AH11 _GPIO(23)
-#define DB8540_PIN_AG11 _GPIO(24)
-#define DB8540_PIN_AF11 _GPIO(25)
-#define DB8540_PIN_AH10 _GPIO(26)
-#define DB8540_PIN_AG10 _GPIO(27)
-#define DB8540_PIN_AF10 _GPIO(28)
-/* Hole */
-#define DB8540_PIN_AD4 _GPIO(33)
-#define DB8540_PIN_AF3 _GPIO(34)
-#define DB8540_PIN_AF5 _GPIO(35)
-#define DB8540_PIN_AG4 _GPIO(36)
-#define DB8540_PIN_AF9 _GPIO(37)
-#define DB8540_PIN_AE8 _GPIO(38)
-/* Hole */
-#define DB8540_PIN_M26 _GPIO(64)
-#define DB8540_PIN_M25 _GPIO(65)
-#define DB8540_PIN_M27 _GPIO(66)
-#define DB8540_PIN_N25 _GPIO(67)
-/* Hole */
-#define DB8540_PIN_M28 _GPIO(70)
-#define DB8540_PIN_N26 _GPIO(71)
-#define DB8540_PIN_M22 _GPIO(72)
-#define DB8540_PIN_N22 _GPIO(73)
-#define DB8540_PIN_N27 _GPIO(74)
-#define DB8540_PIN_N28 _GPIO(75)
-#define DB8540_PIN_P22 _GPIO(76)
-#define DB8540_PIN_P28 _GPIO(77)
-#define DB8540_PIN_P26 _GPIO(78)
-#define DB8540_PIN_T22 _GPIO(79)
-#define DB8540_PIN_R27 _GPIO(80)
-#define DB8540_PIN_P27 _GPIO(81)
-#define DB8540_PIN_R26 _GPIO(82)
-#define DB8540_PIN_R25 _GPIO(83)
-#define DB8540_PIN_U22 _GPIO(84)
-#define DB8540_PIN_T27 _GPIO(85)
-#define DB8540_PIN_T25 _GPIO(86)
-#define DB8540_PIN_T26 _GPIO(87)
-/* Hole */
-#define DB8540_PIN_AF20 _GPIO(116)
-#define DB8540_PIN_AG21 _GPIO(117)
-#define DB8540_PIN_AH19 _GPIO(118)
-#define DB8540_PIN_AE19 _GPIO(119)
-#define DB8540_PIN_AG18 _GPIO(120)
-#define DB8540_PIN_AH17 _GPIO(121)
-#define DB8540_PIN_AF19 _GPIO(122)
-#define DB8540_PIN_AF18 _GPIO(123)
-#define DB8540_PIN_AE18 _GPIO(124)
-#define DB8540_PIN_AG17 _GPIO(125)
-#define DB8540_PIN_AF17 _GPIO(126)
-#define DB8540_PIN_AE17 _GPIO(127)
-#define DB8540_PIN_AC27 _GPIO(128)
-#define DB8540_PIN_AD27 _GPIO(129)
-#define DB8540_PIN_AE28 _GPIO(130)
-#define DB8540_PIN_AG26 _GPIO(131)
-#define DB8540_PIN_AF25 _GPIO(132)
-#define DB8540_PIN_AE27 _GPIO(133)
-#define DB8540_PIN_AF27 _GPIO(134)
-#define DB8540_PIN_AG28 _GPIO(135)
-#define DB8540_PIN_AF28 _GPIO(136)
-#define DB8540_PIN_AG25 _GPIO(137)
-#define DB8540_PIN_AG24 _GPIO(138)
-#define DB8540_PIN_AD25 _GPIO(139)
-#define DB8540_PIN_AH25 _GPIO(140)
-#define DB8540_PIN_AF26 _GPIO(141)
-#define DB8540_PIN_AF23 _GPIO(142)
-#define DB8540_PIN_AG23 _GPIO(143)
-#define DB8540_PIN_AE25 _GPIO(144)
-#define DB8540_PIN_AH24 _GPIO(145)
-#define DB8540_PIN_AJ25 _GPIO(146)
-#define DB8540_PIN_AG27 _GPIO(147)
-#define DB8540_PIN_AH23 _GPIO(148)
-#define DB8540_PIN_AE26 _GPIO(149)
-#define DB8540_PIN_AE24 _GPIO(150)
-#define DB8540_PIN_AJ24 _GPIO(151)
-#define DB8540_PIN_AE21 _GPIO(152)
-#define DB8540_PIN_AG22 _GPIO(153)
-#define DB8540_PIN_AF21 _GPIO(154)
-#define DB8540_PIN_AF24 _GPIO(155)
-#define DB8540_PIN_AH22 _GPIO(156)
-#define DB8540_PIN_AJ23 _GPIO(157)
-#define DB8540_PIN_AH21 _GPIO(158)
-#define DB8540_PIN_AG20 _GPIO(159)
-#define DB8540_PIN_AE23 _GPIO(160)
-#define DB8540_PIN_AH20 _GPIO(161)
-#define DB8540_PIN_AG19 _GPIO(162)
-#define DB8540_PIN_AF22 _GPIO(163)
-#define DB8540_PIN_AJ21 _GPIO(164)
-#define DB8540_PIN_AD26 _GPIO(165)
-#define DB8540_PIN_AD28 _GPIO(166)
-#define DB8540_PIN_AC28 _GPIO(167)
-#define DB8540_PIN_AC26 _GPIO(168)
-/* Hole */
-#define DB8540_PIN_J3 _GPIO(192)
-#define DB8540_PIN_H1 _GPIO(193)
-#define DB8540_PIN_J2 _GPIO(194)
-#define DB8540_PIN_H2 _GPIO(195)
-#define DB8540_PIN_H3 _GPIO(196)
-#define DB8540_PIN_H4 _GPIO(197)
-#define DB8540_PIN_G2 _GPIO(198)
-#define DB8540_PIN_G3 _GPIO(199)
-#define DB8540_PIN_G4 _GPIO(200)
-#define DB8540_PIN_F2 _GPIO(201)
-#define DB8540_PIN_C6 _GPIO(202)
-#define DB8540_PIN_B6 _GPIO(203)
-#define DB8540_PIN_B7 _GPIO(204)
-#define DB8540_PIN_A7 _GPIO(205)
-#define DB8540_PIN_D7 _GPIO(206)
-#define DB8540_PIN_D8 _GPIO(207)
-#define DB8540_PIN_F3 _GPIO(208)
-#define DB8540_PIN_E2 _GPIO(209)
-#define DB8540_PIN_C7 _GPIO(210)
-#define DB8540_PIN_B8 _GPIO(211)
-#define DB8540_PIN_C10 _GPIO(212)
-#define DB8540_PIN_C8 _GPIO(213)
-#define DB8540_PIN_C9 _GPIO(214)
-/* Hole */
-#define DB8540_PIN_B9 _GPIO(219)
-#define DB8540_PIN_A10 _GPIO(220)
-#define DB8540_PIN_D9 _GPIO(221)
-#define DB8540_PIN_B11 _GPIO(222)
-#define DB8540_PIN_B10 _GPIO(223)
-#define DB8540_PIN_E10 _GPIO(224)
-#define DB8540_PIN_B12 _GPIO(225)
-#define DB8540_PIN_D10 _GPIO(226)
-#define DB8540_PIN_D11 _GPIO(227)
-#define DB8540_PIN_AJ6 _GPIO(228)
-#define DB8540_PIN_B13 _GPIO(229)
-#define DB8540_PIN_C12 _GPIO(230)
-#define DB8540_PIN_B14 _GPIO(231)
-#define DB8540_PIN_E11 _GPIO(232)
-/* Hole */
-#define DB8540_PIN_D12 _GPIO(256)
-#define DB8540_PIN_D15 _GPIO(257)
-#define DB8540_PIN_C13 _GPIO(258)
-#define DB8540_PIN_C14 _GPIO(259)
-#define DB8540_PIN_C18 _GPIO(260)
-#define DB8540_PIN_C16 _GPIO(261)
-#define DB8540_PIN_B16 _GPIO(262)
-#define DB8540_PIN_D18 _GPIO(263)
-#define DB8540_PIN_C15 _GPIO(264)
-#define DB8540_PIN_C17 _GPIO(265)
-#define DB8540_PIN_B17 _GPIO(266)
-#define DB8540_PIN_D17 _GPIO(267)
-
-/*
- * The names of the pins are denoted by GPIO number and ball name, even
- * though they can be used for other things than GPIO, this is the first
- * column in the table of the data sheet and often used on schematics and
- * such.
- */
-static const struct pinctrl_pin_desc nmk_db8540_pins[] = {
- PINCTRL_PIN(DB8540_PIN_AH6, "GPIO0_AH6"),
- PINCTRL_PIN(DB8540_PIN_AG7, "GPIO1_AG7"),
- PINCTRL_PIN(DB8540_PIN_AF2, "GPIO2_AF2"),
- PINCTRL_PIN(DB8540_PIN_AD3, "GPIO3_AD3"),
- PINCTRL_PIN(DB8540_PIN_AF6, "GPIO4_AF6"),
- PINCTRL_PIN(DB8540_PIN_AG6, "GPIO5_AG6"),
- PINCTRL_PIN(DB8540_PIN_AD5, "GPIO6_AD5"),
- PINCTRL_PIN(DB8540_PIN_AF7, "GPIO7_AF7"),
- PINCTRL_PIN(DB8540_PIN_AG5, "GPIO8_AG5"),
- PINCTRL_PIN(DB8540_PIN_AH5, "GPIO9_AH5"),
- PINCTRL_PIN(DB8540_PIN_AE4, "GPIO10_AE4"),
- PINCTRL_PIN(DB8540_PIN_AD1, "GPIO11_AD1"),
- PINCTRL_PIN(DB8540_PIN_AD2, "GPIO12_AD2"),
- PINCTRL_PIN(DB8540_PIN_AC2, "GPIO13_AC2"),
- PINCTRL_PIN(DB8540_PIN_AC4, "GPIO14_AC4"),
- PINCTRL_PIN(DB8540_PIN_AC3, "GPIO15_AC3"),
- PINCTRL_PIN(DB8540_PIN_AH7, "GPIO16_AH7"),
- PINCTRL_PIN(DB8540_PIN_AE7, "GPIO17_AE7"),
- /* Hole */
- PINCTRL_PIN(DB8540_PIN_AF8, "GPIO22_AF8"),
- PINCTRL_PIN(DB8540_PIN_AH11, "GPIO23_AH11"),
- PINCTRL_PIN(DB8540_PIN_AG11, "GPIO24_AG11"),
- PINCTRL_PIN(DB8540_PIN_AF11, "GPIO25_AF11"),
- PINCTRL_PIN(DB8540_PIN_AH10, "GPIO26_AH10"),
- PINCTRL_PIN(DB8540_PIN_AG10, "GPIO27_AG10"),
- PINCTRL_PIN(DB8540_PIN_AF10, "GPIO28_AF10"),
- /* Hole */
- PINCTRL_PIN(DB8540_PIN_AD4, "GPIO33_AD4"),
- PINCTRL_PIN(DB8540_PIN_AF3, "GPIO34_AF3"),
- PINCTRL_PIN(DB8540_PIN_AF5, "GPIO35_AF5"),
- PINCTRL_PIN(DB8540_PIN_AG4, "GPIO36_AG4"),
- PINCTRL_PIN(DB8540_PIN_AF9, "GPIO37_AF9"),
- PINCTRL_PIN(DB8540_PIN_AE8, "GPIO38_AE8"),
- /* Hole */
- PINCTRL_PIN(DB8540_PIN_M26, "GPIO64_M26"),
- PINCTRL_PIN(DB8540_PIN_M25, "GPIO65_M25"),
- PINCTRL_PIN(DB8540_PIN_M27, "GPIO66_M27"),
- PINCTRL_PIN(DB8540_PIN_N25, "GPIO67_N25"),
- /* Hole */
- PINCTRL_PIN(DB8540_PIN_M28, "GPIO70_M28"),
- PINCTRL_PIN(DB8540_PIN_N26, "GPIO71_N26"),
- PINCTRL_PIN(DB8540_PIN_M22, "GPIO72_M22"),
- PINCTRL_PIN(DB8540_PIN_N22, "GPIO73_N22"),
- PINCTRL_PIN(DB8540_PIN_N27, "GPIO74_N27"),
- PINCTRL_PIN(DB8540_PIN_N28, "GPIO75_N28"),
- PINCTRL_PIN(DB8540_PIN_P22, "GPIO76_P22"),
- PINCTRL_PIN(DB8540_PIN_P28, "GPIO77_P28"),
- PINCTRL_PIN(DB8540_PIN_P26, "GPIO78_P26"),
- PINCTRL_PIN(DB8540_PIN_T22, "GPIO79_T22"),
- PINCTRL_PIN(DB8540_PIN_R27, "GPIO80_R27"),
- PINCTRL_PIN(DB8540_PIN_P27, "GPIO81_P27"),
- PINCTRL_PIN(DB8540_PIN_R26, "GPIO82_R26"),
- PINCTRL_PIN(DB8540_PIN_R25, "GPIO83_R25"),
- PINCTRL_PIN(DB8540_PIN_U22, "GPIO84_U22"),
- PINCTRL_PIN(DB8540_PIN_T27, "GPIO85_T27"),
- PINCTRL_PIN(DB8540_PIN_T25, "GPIO86_T25"),
- PINCTRL_PIN(DB8540_PIN_T26, "GPIO87_T26"),
- /* Hole */
- PINCTRL_PIN(DB8540_PIN_AF20, "GPIO116_AF20"),
- PINCTRL_PIN(DB8540_PIN_AG21, "GPIO117_AG21"),
- PINCTRL_PIN(DB8540_PIN_AH19, "GPIO118_AH19"),
- PINCTRL_PIN(DB8540_PIN_AE19, "GPIO119_AE19"),
- PINCTRL_PIN(DB8540_PIN_AG18, "GPIO120_AG18"),
- PINCTRL_PIN(DB8540_PIN_AH17, "GPIO121_AH17"),
- PINCTRL_PIN(DB8540_PIN_AF19, "GPIO122_AF19"),
- PINCTRL_PIN(DB8540_PIN_AF18, "GPIO123_AF18"),
- PINCTRL_PIN(DB8540_PIN_AE18, "GPIO124_AE18"),
- PINCTRL_PIN(DB8540_PIN_AG17, "GPIO125_AG17"),
- PINCTRL_PIN(DB8540_PIN_AF17, "GPIO126_AF17"),
- PINCTRL_PIN(DB8540_PIN_AE17, "GPIO127_AE17"),
- PINCTRL_PIN(DB8540_PIN_AC27, "GPIO128_AC27"),
- PINCTRL_PIN(DB8540_PIN_AD27, "GPIO129_AD27"),
- PINCTRL_PIN(DB8540_PIN_AE28, "GPIO130_AE28"),
- PINCTRL_PIN(DB8540_PIN_AG26, "GPIO131_AG26"),
- PINCTRL_PIN(DB8540_PIN_AF25, "GPIO132_AF25"),
- PINCTRL_PIN(DB8540_PIN_AE27, "GPIO133_AE27"),
- PINCTRL_PIN(DB8540_PIN_AF27, "GPIO134_AF27"),
- PINCTRL_PIN(DB8540_PIN_AG28, "GPIO135_AG28"),
- PINCTRL_PIN(DB8540_PIN_AF28, "GPIO136_AF28"),
- PINCTRL_PIN(DB8540_PIN_AG25, "GPIO137_AG25"),
- PINCTRL_PIN(DB8540_PIN_AG24, "GPIO138_AG24"),
- PINCTRL_PIN(DB8540_PIN_AD25, "GPIO139_AD25"),
- PINCTRL_PIN(DB8540_PIN_AH25, "GPIO140_AH25"),
- PINCTRL_PIN(DB8540_PIN_AF26, "GPIO141_AF26"),
- PINCTRL_PIN(DB8540_PIN_AF23, "GPIO142_AF23"),
- PINCTRL_PIN(DB8540_PIN_AG23, "GPIO143_AG23"),
- PINCTRL_PIN(DB8540_PIN_AE25, "GPIO144_AE25"),
- PINCTRL_PIN(DB8540_PIN_AH24, "GPIO145_AH24"),
- PINCTRL_PIN(DB8540_PIN_AJ25, "GPIO146_AJ25"),
- PINCTRL_PIN(DB8540_PIN_AG27, "GPIO147_AG27"),
- PINCTRL_PIN(DB8540_PIN_AH23, "GPIO148_AH23"),
- PINCTRL_PIN(DB8540_PIN_AE26, "GPIO149_AE26"),
- PINCTRL_PIN(DB8540_PIN_AE24, "GPIO150_AE24"),
- PINCTRL_PIN(DB8540_PIN_AJ24, "GPIO151_AJ24"),
- PINCTRL_PIN(DB8540_PIN_AE21, "GPIO152_AE21"),
- PINCTRL_PIN(DB8540_PIN_AG22, "GPIO153_AG22"),
- PINCTRL_PIN(DB8540_PIN_AF21, "GPIO154_AF21"),
- PINCTRL_PIN(DB8540_PIN_AF24, "GPIO155_AF24"),
- PINCTRL_PIN(DB8540_PIN_AH22, "GPIO156_AH22"),
- PINCTRL_PIN(DB8540_PIN_AJ23, "GPIO157_AJ23"),
- PINCTRL_PIN(DB8540_PIN_AH21, "GPIO158_AH21"),
- PINCTRL_PIN(DB8540_PIN_AG20, "GPIO159_AG20"),
- PINCTRL_PIN(DB8540_PIN_AE23, "GPIO160_AE23"),
- PINCTRL_PIN(DB8540_PIN_AH20, "GPIO161_AH20"),
- PINCTRL_PIN(DB8540_PIN_AG19, "GPIO162_AG19"),
- PINCTRL_PIN(DB8540_PIN_AF22, "GPIO163_AF22"),
- PINCTRL_PIN(DB8540_PIN_AJ21, "GPIO164_AJ21"),
- PINCTRL_PIN(DB8540_PIN_AD26, "GPIO165_AD26"),
- PINCTRL_PIN(DB8540_PIN_AD28, "GPIO166_AD28"),
- PINCTRL_PIN(DB8540_PIN_AC28, "GPIO167_AC28"),
- PINCTRL_PIN(DB8540_PIN_AC26, "GPIO168_AC26"),
- /* Hole */
- PINCTRL_PIN(DB8540_PIN_J3, "GPIO192_J3"),
- PINCTRL_PIN(DB8540_PIN_H1, "GPIO193_H1"),
- PINCTRL_PIN(DB8540_PIN_J2, "GPIO194_J2"),
- PINCTRL_PIN(DB8540_PIN_H2, "GPIO195_H2"),
- PINCTRL_PIN(DB8540_PIN_H3, "GPIO196_H3"),
- PINCTRL_PIN(DB8540_PIN_H4, "GPIO197_H4"),
- PINCTRL_PIN(DB8540_PIN_G2, "GPIO198_G2"),
- PINCTRL_PIN(DB8540_PIN_G3, "GPIO199_G3"),
- PINCTRL_PIN(DB8540_PIN_G4, "GPIO200_G4"),
- PINCTRL_PIN(DB8540_PIN_F2, "GPIO201_F2"),
- PINCTRL_PIN(DB8540_PIN_C6, "GPIO202_C6"),
- PINCTRL_PIN(DB8540_PIN_B6, "GPIO203_B6"),
- PINCTRL_PIN(DB8540_PIN_B7, "GPIO204_B7"),
- PINCTRL_PIN(DB8540_PIN_A7, "GPIO205_A7"),
- PINCTRL_PIN(DB8540_PIN_D7, "GPIO206_D7"),
- PINCTRL_PIN(DB8540_PIN_D8, "GPIO207_D8"),
- PINCTRL_PIN(DB8540_PIN_F3, "GPIO208_F3"),
- PINCTRL_PIN(DB8540_PIN_E2, "GPIO209_E2"),
- PINCTRL_PIN(DB8540_PIN_C7, "GPIO210_C7"),
- PINCTRL_PIN(DB8540_PIN_B8, "GPIO211_B8"),
- PINCTRL_PIN(DB8540_PIN_C10, "GPIO212_C10"),
- PINCTRL_PIN(DB8540_PIN_C8, "GPIO213_C8"),
- PINCTRL_PIN(DB8540_PIN_C9, "GPIO214_C9"),
- /* Hole */
- PINCTRL_PIN(DB8540_PIN_B9, "GPIO219_B9"),
- PINCTRL_PIN(DB8540_PIN_A10, "GPIO220_A10"),
- PINCTRL_PIN(DB8540_PIN_D9, "GPIO221_D9"),
- PINCTRL_PIN(DB8540_PIN_B11, "GPIO222_B11"),
- PINCTRL_PIN(DB8540_PIN_B10, "GPIO223_B10"),
- PINCTRL_PIN(DB8540_PIN_E10, "GPIO224_E10"),
- PINCTRL_PIN(DB8540_PIN_B12, "GPIO225_B12"),
- PINCTRL_PIN(DB8540_PIN_D10, "GPIO226_D10"),
- PINCTRL_PIN(DB8540_PIN_D11, "GPIO227_D11"),
- PINCTRL_PIN(DB8540_PIN_AJ6, "GPIO228_AJ6"),
- PINCTRL_PIN(DB8540_PIN_B13, "GPIO229_B13"),
- PINCTRL_PIN(DB8540_PIN_C12, "GPIO230_C12"),
- PINCTRL_PIN(DB8540_PIN_B14, "GPIO231_B14"),
- PINCTRL_PIN(DB8540_PIN_E11, "GPIO232_E11"),
- /* Hole */
- PINCTRL_PIN(DB8540_PIN_D12, "GPIO256_D12"),
- PINCTRL_PIN(DB8540_PIN_D15, "GPIO257_D15"),
- PINCTRL_PIN(DB8540_PIN_C13, "GPIO258_C13"),
- PINCTRL_PIN(DB8540_PIN_C14, "GPIO259_C14"),
- PINCTRL_PIN(DB8540_PIN_C18, "GPIO260_C18"),
- PINCTRL_PIN(DB8540_PIN_C16, "GPIO261_C16"),
- PINCTRL_PIN(DB8540_PIN_B16, "GPIO262_B16"),
- PINCTRL_PIN(DB8540_PIN_D18, "GPIO263_D18"),
- PINCTRL_PIN(DB8540_PIN_C15, "GPIO264_C15"),
- PINCTRL_PIN(DB8540_PIN_C17, "GPIO265_C17"),
- PINCTRL_PIN(DB8540_PIN_B17, "GPIO266_B17"),
- PINCTRL_PIN(DB8540_PIN_D17, "GPIO267_D17"),
-};
-
-/*
- * Read the pin group names like this:
- * u0_a_1 = first groups of pins for uart0 on alt function a
- * i2c2_b_2 = second group of pins for i2c2 on alt function b
- *
- * The groups are arranged as sets per altfunction column, so we can
- * mux in one group at a time by selecting the same altfunction for them
- * all. When functions require pins on different altfunctions, you need
- * to combine several groups.
- */
-
-/* Altfunction A column */
-static const unsigned u0_a_1_pins[] = { DB8540_PIN_AH6, DB8540_PIN_AG7,
- DB8540_PIN_AF2, DB8540_PIN_AD3 };
-static const unsigned u1rxtx_a_1_pins[] = { DB8540_PIN_AF6, DB8540_PIN_AG6 };
-static const unsigned u1ctsrts_a_1_pins[] = { DB8540_PIN_AD5, DB8540_PIN_AF7 };
-/* Image processor I2C line, this is driven by image processor firmware */
-static const unsigned ipi2c_a_1_pins[] = { DB8540_PIN_AG5, DB8540_PIN_AH5 };
-static const unsigned ipi2c_a_2_pins[] = { DB8540_PIN_AE4, DB8540_PIN_AD1 };
-/* MSP0 can only be on these pins, but TXD and RXD can be flipped */
-static const unsigned msp0txrx_a_1_pins[] = { DB8540_PIN_AD2, DB8540_PIN_AC3 };
-static const unsigned msp0tfstck_a_1_pins[] = { DB8540_PIN_AC2,
- DB8540_PIN_AC4 };
-static const unsigned msp0rfsrck_a_1_pins[] = { DB8540_PIN_AH7,
- DB8540_PIN_AE7 };
-/* Basic pins of the MMC/SD card 0 interface */
-static const unsigned mc0_a_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AG11,
- DB8540_PIN_AF11, DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10};
-/* MSP1 can only be on these pins, but TXD and RXD can be flipped */
-static const unsigned msp1txrx_a_1_pins[] = { DB8540_PIN_AD4, DB8540_PIN_AG4 };
-static const unsigned msp1_a_1_pins[] = { DB8540_PIN_AF3, DB8540_PIN_AF5 };
-
-static const unsigned modobsclk_a_1_pins[] = { DB8540_PIN_AF9 };
-static const unsigned clkoutreq_a_1_pins[] = { DB8540_PIN_AE8 };
-/* LCD interface */
-static const unsigned lcdb_a_1_pins[] = { DB8540_PIN_M26, DB8540_PIN_M25,
- DB8540_PIN_M27, DB8540_PIN_N25 };
-static const unsigned lcdvsi0_a_1_pins[] = { DB8540_PIN_AJ24 };
-static const unsigned lcdvsi1_a_1_pins[] = { DB8540_PIN_AE21 };
-static const unsigned lcd_d0_d7_a_1_pins[] = { DB8540_PIN_M28, DB8540_PIN_N26,
- DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27, DB8540_PIN_N28,
- DB8540_PIN_P22, DB8540_PIN_P28 };
-/* D8 thru D11 often used as TVOUT lines */
-static const unsigned lcd_d8_d11_a_1_pins[] = { DB8540_PIN_P26, DB8540_PIN_T22,
- DB8540_PIN_R27, DB8540_PIN_P27 };
-static const unsigned lcd_d12_d23_a_1_pins[] = { DB8540_PIN_R26, DB8540_PIN_R25,
- DB8540_PIN_U22, DB8540_PIN_T27, DB8540_PIN_AG22, DB8540_PIN_AF21,
- DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
- DB8540_PIN_AG20, DB8540_PIN_AE23 };
-static const unsigned kp_a_1_pins[] = { DB8540_PIN_AH20, DB8540_PIN_AG19,
- DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25, DB8540_PIN_T26 };
-/* MC2 has 8 data lines and no direction control, so only for (e)MMC */
-static const unsigned mc2_a_1_pins[] = { DB8540_PIN_AC27, DB8540_PIN_AD27,
- DB8540_PIN_AE28, DB8540_PIN_AG26, DB8540_PIN_AF25, DB8540_PIN_AE27,
- DB8540_PIN_AF27, DB8540_PIN_AG28, DB8540_PIN_AF28, DB8540_PIN_AG25,
- DB8540_PIN_AG24 };
-static const unsigned ssp1_a_1_pins[] = { DB8540_PIN_AD25, DB8540_PIN_AH25,
- DB8540_PIN_AF26, DB8540_PIN_AF23 };
-static const unsigned ssp0_a_1_pins[] = { DB8540_PIN_AG23, DB8540_PIN_AE25,
- DB8540_PIN_AH24, DB8540_PIN_AJ25 };
-static const unsigned i2c0_a_1_pins[] = { DB8540_PIN_AG27, DB8540_PIN_AH23 };
-/*
- * Image processor GPIO pins are named "ipgpio" and have their own
- * numberspace
- */
-static const unsigned ipgpio0_a_1_pins[] = { DB8540_PIN_AE26 };
-static const unsigned ipgpio1_a_1_pins[] = { DB8540_PIN_AE24 };
-/* modem i2s interface */
-static const unsigned modi2s_a_1_pins[] = { DB8540_PIN_AD26, DB8540_PIN_AD28,
- DB8540_PIN_AC28, DB8540_PIN_AC26 };
-static const unsigned spi2_a_1_pins[] = { DB8540_PIN_AF20, DB8540_PIN_AG21,
- DB8540_PIN_AH19, DB8540_PIN_AE19 };
-static const unsigned u2txrx_a_1_pins[] = { DB8540_PIN_AG18, DB8540_PIN_AH17 };
-static const unsigned u2ctsrts_a_1_pins[] = { DB8540_PIN_AF19,
- DB8540_PIN_AF18 };
-static const unsigned modsmb_a_1_pins[] = { DB8540_PIN_AF17, DB8540_PIN_AE17 };
-static const unsigned msp2sck_a_1_pins[] = { DB8540_PIN_J3 };
-static const unsigned msp2txdtcktfs_a_1_pins[] = { DB8540_PIN_H1, DB8540_PIN_J2,
- DB8540_PIN_H2 };
-static const unsigned msp2rxd_a_1_pins[] = { DB8540_PIN_H3 };
-static const unsigned mc4_a_1_pins[] = { DB8540_PIN_H4, DB8540_PIN_G2,
- DB8540_PIN_G3, DB8540_PIN_G4, DB8540_PIN_F2, DB8540_PIN_C6,
- DB8540_PIN_B6, DB8540_PIN_B7, DB8540_PIN_A7, DB8540_PIN_D7,
- DB8540_PIN_D8 };
-static const unsigned mc1_a_1_pins[] = { DB8540_PIN_F3, DB8540_PIN_E2,
- DB8540_PIN_C7, DB8540_PIN_B8, DB8540_PIN_C10, DB8540_PIN_C8,
- DB8540_PIN_C9 };
-/* mc1_a_2_pins exclude MC1_FBCLK */
-static const unsigned mc1_a_2_pins[] = { DB8540_PIN_F3, DB8540_PIN_C7,
- DB8540_PIN_B8, DB8540_PIN_C10, DB8540_PIN_C8,
- DB8540_PIN_C9 };
-static const unsigned hsir_a_1_pins[] = { DB8540_PIN_B9, DB8540_PIN_A10,
- DB8540_PIN_D9 };
-static const unsigned hsit_a_1_pins[] = { DB8540_PIN_B11, DB8540_PIN_B10,
- DB8540_PIN_E10, DB8540_PIN_B12, DB8540_PIN_D10 };
-static const unsigned hsit_a_2_pins[] = { DB8540_PIN_B11, DB8540_PIN_B10,
- DB8540_PIN_E10, DB8540_PIN_B12 };
-static const unsigned clkout1_a_1_pins[] = { DB8540_PIN_D11 };
-static const unsigned clkout1_a_2_pins[] = { DB8540_PIN_B13 };
-static const unsigned clkout2_a_1_pins[] = { DB8540_PIN_AJ6 };
-static const unsigned clkout2_a_2_pins[] = { DB8540_PIN_C12 };
-static const unsigned msp4_a_1_pins[] = { DB8540_PIN_B14, DB8540_PIN_E11 };
-static const unsigned usb_a_1_pins[] = { DB8540_PIN_D12, DB8540_PIN_D15,
- DB8540_PIN_C13, DB8540_PIN_C14, DB8540_PIN_C18, DB8540_PIN_C16,
- DB8540_PIN_B16, DB8540_PIN_D18, DB8540_PIN_C15, DB8540_PIN_C17,
- DB8540_PIN_B17, DB8540_PIN_D17 };
-/* Altfunction B colum */
-static const unsigned apetrig_b_1_pins[] = { DB8540_PIN_AH6, DB8540_PIN_AG7 };
-static const unsigned modtrig_b_1_pins[] = { DB8540_PIN_AF2, DB8540_PIN_AD3 };
-static const unsigned i2c4_b_1_pins[] = { DB8540_PIN_AF6, DB8540_PIN_AG6 };
-static const unsigned i2c1_b_1_pins[] = { DB8540_PIN_AD5, DB8540_PIN_AF7 };
-static const unsigned i2c2_b_1_pins[] = { DB8540_PIN_AG5, DB8540_PIN_AH5 };
-static const unsigned i2c2_b_2_pins[] = { DB8540_PIN_AE4, DB8540_PIN_AD1 };
-static const unsigned msp0txrx_b_1_pins[] = { DB8540_PIN_AD2, DB8540_PIN_AC3 };
-static const unsigned i2c1_b_2_pins[] = { DB8540_PIN_AH7, DB8540_PIN_AE7 };
-static const unsigned stmmod_b_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AF11,
- DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10 };
-static const unsigned moduartstmmux_b_1_pins[] = { DB8540_PIN_AG11 };
-static const unsigned msp1txrx_b_1_pins[] = { DB8540_PIN_AD4, DB8540_PIN_AG4 };
-static const unsigned kp_b_1_pins[] = { DB8540_PIN_AJ24, DB8540_PIN_AE21,
- DB8540_PIN_M26, DB8540_PIN_M25, DB8540_PIN_M27, DB8540_PIN_N25,
- DB8540_PIN_M28, DB8540_PIN_N26, DB8540_PIN_M22, DB8540_PIN_N22,
- DB8540_PIN_N27, DB8540_PIN_N28, DB8540_PIN_P22, DB8540_PIN_P28,
- DB8540_PIN_P26, DB8540_PIN_T22, DB8540_PIN_R27, DB8540_PIN_P27,
- DB8540_PIN_R26, DB8540_PIN_R25 };
-static const unsigned u2txrx_b_1_pins[] = { DB8540_PIN_U22, DB8540_PIN_T27 };
-static const unsigned sm_b_1_pins[] = { DB8540_PIN_AG22, DB8540_PIN_AF21,
- DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
- DB8540_PIN_AG20, DB8540_PIN_AE23, DB8540_PIN_AH20, DB8540_PIN_AF22,
- DB8540_PIN_AJ21, DB8540_PIN_AC27, DB8540_PIN_AD27, DB8540_PIN_AE28,
- DB8540_PIN_AG26, DB8540_PIN_AF25, DB8540_PIN_AE27, DB8540_PIN_AF27,
- DB8540_PIN_AG28, DB8540_PIN_AF28, DB8540_PIN_AG25, DB8540_PIN_AG24,
- DB8540_PIN_AD25 };
-static const unsigned smcs0_b_1_pins[] = { DB8540_PIN_AG19 };
-static const unsigned smcs1_b_1_pins[] = { DB8540_PIN_AE26 };
-static const unsigned ipgpio7_b_1_pins[] = { DB8540_PIN_AH25 };
-static const unsigned ipgpio2_b_1_pins[] = { DB8540_PIN_AF26 };
-static const unsigned ipgpio3_b_1_pins[] = { DB8540_PIN_AF23 };
-static const unsigned i2c6_b_1_pins[] = { DB8540_PIN_AG23, DB8540_PIN_AE25 };
-static const unsigned i2c5_b_1_pins[] = { DB8540_PIN_AH24, DB8540_PIN_AJ25 };
-static const unsigned u3txrx_b_1_pins[] = { DB8540_PIN_AF20, DB8540_PIN_AG21 };
-static const unsigned u3ctsrts_b_1_pins[] = { DB8540_PIN_AH19,
- DB8540_PIN_AE19 };
-static const unsigned i2c5_b_2_pins[] = { DB8540_PIN_AG18, DB8540_PIN_AH17 };
-static const unsigned i2c4_b_2_pins[] = { DB8540_PIN_AF19, DB8540_PIN_AF18 };
-static const unsigned u4txrx_b_1_pins[] = { DB8540_PIN_AE18, DB8540_PIN_AG17 };
-static const unsigned u4ctsrts_b_1_pins[] = { DB8540_PIN_AF17,
- DB8540_PIN_AE17 };
-static const unsigned ddrtrig_b_1_pins[] = { DB8540_PIN_J3 };
-static const unsigned msp4_b_1_pins[] = { DB8540_PIN_H3 };
-static const unsigned pwl_b_1_pins[] = { DB8540_PIN_C6 };
-static const unsigned spi1_b_1_pins[] = { DB8540_PIN_E2, DB8540_PIN_C10,
- DB8540_PIN_C8, DB8540_PIN_C9 };
-static const unsigned mc3_b_1_pins[] = { DB8540_PIN_B9, DB8540_PIN_A10,
- DB8540_PIN_D9, DB8540_PIN_B11, DB8540_PIN_B10, DB8540_PIN_E10,
- DB8540_PIN_B12 };
-static const unsigned pwl_b_2_pins[] = { DB8540_PIN_D10 };
-static const unsigned pwl_b_3_pins[] = { DB8540_PIN_B13 };
-static const unsigned pwl_b_4_pins[] = { DB8540_PIN_C12 };
-static const unsigned u2txrx_b_2_pins[] = { DB8540_PIN_B17, DB8540_PIN_D17 };
-
-/* Altfunction C column */
-static const unsigned ipgpio6_c_1_pins[] = { DB8540_PIN_AG6 };
-static const unsigned ipgpio0_c_1_pins[] = { DB8540_PIN_AD5 };
-static const unsigned ipgpio1_c_1_pins[] = { DB8540_PIN_AF7 };
-static const unsigned ipgpio3_c_1_pins[] = { DB8540_PIN_AE4 };
-static const unsigned ipgpio2_c_1_pins[] = { DB8540_PIN_AD1 };
-static const unsigned u0_c_1_pins[] = { DB8540_PIN_AD4, DB8540_PIN_AF3,
- DB8540_PIN_AF5, DB8540_PIN_AG4 };
-static const unsigned smcleale_c_1_pins[] = { DB8540_PIN_AJ24,
- DB8540_PIN_AE21 };
-static const unsigned ipgpio4_c_1_pins[] = { DB8540_PIN_M26 };
-static const unsigned ipgpio5_c_1_pins[] = { DB8540_PIN_M25 };
-static const unsigned ipgpio6_c_2_pins[] = { DB8540_PIN_M27 };
-static const unsigned ipgpio7_c_1_pins[] = { DB8540_PIN_N25 };
-static const unsigned stmape_c_1_pins[] = { DB8540_PIN_M28, DB8540_PIN_N26,
- DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27 };
-static const unsigned u2rxtx_c_1_pins[] = { DB8540_PIN_N28, DB8540_PIN_P22 };
-static const unsigned modobsresout_c_1_pins[] = { DB8540_PIN_P28 };
-static const unsigned ipgpio2_c_2_pins[] = { DB8540_PIN_P26 };
-static const unsigned ipgpio3_c_2_pins[] = { DB8540_PIN_T22 };
-static const unsigned ipgpio4_c_2_pins[] = { DB8540_PIN_R27 };
-static const unsigned ipgpio5_c_2_pins[] = { DB8540_PIN_P27 };
-static const unsigned modaccgpo_c_1_pins[] = { DB8540_PIN_R26, DB8540_PIN_R25,
- DB8540_PIN_U22 };
-static const unsigned modobspwrrst_c_1_pins[] = { DB8540_PIN_T27 };
-static const unsigned mc5_c_1_pins[] = { DB8540_PIN_AG22, DB8540_PIN_AF21,
- DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
- DB8540_PIN_AG20, DB8540_PIN_AE23, DB8540_PIN_AH20, DB8540_PIN_AF22,
- DB8540_PIN_AJ21};
-static const unsigned smps0_c_1_pins[] = { DB8540_PIN_AG19 };
-static const unsigned moduart1_c_1_pins[] = { DB8540_PIN_T25, DB8540_PIN_T26 };
-static const unsigned mc2rstn_c_1_pins[] = { DB8540_PIN_AE28 };
-static const unsigned i2c5_c_1_pins[] = { DB8540_PIN_AG28, DB8540_PIN_AF28 };
-static const unsigned ipgpio0_c_2_pins[] = { DB8540_PIN_AG25 };
-static const unsigned ipgpio1_c_2_pins[] = { DB8540_PIN_AG24 };
-static const unsigned kp_c_1_pins[] = { DB8540_PIN_AD25, DB8540_PIN_AH25,
- DB8540_PIN_AF26, DB8540_PIN_AF23 };
-static const unsigned modrf_c_1_pins[] = { DB8540_PIN_AG23, DB8540_PIN_AE25,
- DB8540_PIN_AH24 };
-static const unsigned smps1_c_1_pins[] = { DB8540_PIN_AE26 };
-static const unsigned i2c5_c_2_pins[] = { DB8540_PIN_AH19, DB8540_PIN_AE19 };
-static const unsigned u4ctsrts_c_1_pins[] = { DB8540_PIN_AG18,
- DB8540_PIN_AH17 };
-static const unsigned u3rxtx_c_1_pins[] = { DB8540_PIN_AF19, DB8540_PIN_AF18 };
-static const unsigned msp4_c_1_pins[] = { DB8540_PIN_J3 };
-static const unsigned mc4rstn_c_1_pins[] = { DB8540_PIN_C6 };
-static const unsigned spi0_c_1_pins[] = { DB8540_PIN_A10, DB8540_PIN_B10,
- DB8540_PIN_E10, DB8540_PIN_B12 };
-static const unsigned i2c3_c_1_pins[] = { DB8540_PIN_B13, DB8540_PIN_C12 };
-
-/* Other alt C1 column */
-static const unsigned spi3_oc1_1_pins[] = { DB8540_PIN_AG5, DB8540_PIN_AH5,
- DB8540_PIN_AE4, DB8540_PIN_AD1 };
-static const unsigned stmape_oc1_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AF11,
- DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10 };
-static const unsigned u2_oc1_1_pins[] = { DB8540_PIN_AG11 };
-static const unsigned remap0_oc1_1_pins[] = { DB8540_PIN_AJ24 };
-static const unsigned remap1_oc1_1_pins[] = { DB8540_PIN_AE21 };
-static const unsigned modobsrefclk_oc1_1_pins[] = { DB8540_PIN_M26 };
-static const unsigned modobspwrctrl_oc1_1_pins[] = { DB8540_PIN_M25 };
-static const unsigned modobsclkout_oc1_1_pins[] = { DB8540_PIN_M27 };
-static const unsigned moduart1_oc1_1_pins[] = { DB8540_PIN_N25 };
-static const unsigned modprcmudbg_oc1_1_pins[] = { DB8540_PIN_M28,
- DB8540_PIN_N26, DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27,
- DB8540_PIN_P22, DB8540_PIN_P28, DB8540_PIN_P26, DB8540_PIN_T22,
- DB8540_PIN_R26, DB8540_PIN_R25, DB8540_PIN_U22, DB8540_PIN_T27,
- DB8540_PIN_AH20, DB8540_PIN_AG19, DB8540_PIN_AF22, DB8540_PIN_AJ21,
- DB8540_PIN_T25};
-static const unsigned modobsresout_oc1_1_pins[] = { DB8540_PIN_N28 };
-static const unsigned modaccgpo_oc1_1_pins[] = { DB8540_PIN_R27, DB8540_PIN_P27,
- DB8540_PIN_T26 };
-static const unsigned kp_oc1_1_pins[] = { DB8540_PIN_AG22, DB8540_PIN_AF21,
- DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
- DB8540_PIN_AG20, DB8540_PIN_AE23 };
-static const unsigned modxmip_oc1_1_pins[] = { DB8540_PIN_AD25, DB8540_PIN_AH25,
- DB8540_PIN_AG23, DB8540_PIN_AE25 };
-static const unsigned i2c6_oc1_1_pins[] = { DB8540_PIN_AE26, DB8540_PIN_AE24 };
-static const unsigned u2txrx_oc1_1_pins[] = { DB8540_PIN_B7, DB8540_PIN_A7 };
-static const unsigned u2ctsrts_oc1_1_pins[] = { DB8540_PIN_D7, DB8540_PIN_D8 };
-
-/* Other alt C2 column */
-static const unsigned sbag_oc2_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AG11,
- DB8540_PIN_AF11, DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10 };
-static const unsigned hxclk_oc2_1_pins[] = { DB8540_PIN_M25 };
-static const unsigned modaccuart_oc2_1_pins[] = { DB8540_PIN_N25 };
-static const unsigned stmmod_oc2_1_pins[] = { DB8540_PIN_M28, DB8540_PIN_N26,
- DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27 };
-static const unsigned moduartstmmux_oc2_1_pins[] = { DB8540_PIN_N28 };
-static const unsigned hxgpio_oc2_1_pins[] = { DB8540_PIN_P22, DB8540_PIN_P28,
- DB8540_PIN_P26, DB8540_PIN_T22, DB8540_PIN_R27, DB8540_PIN_P27,
- DB8540_PIN_R26, DB8540_PIN_R25 };
-static const unsigned sbag_oc2_2_pins[] = { DB8540_PIN_U22, DB8540_PIN_T27,
- DB8540_PIN_AG22, DB8540_PIN_AF21, DB8540_PIN_AF24, DB8540_PIN_AH22 };
-static const unsigned modobsservice_oc2_1_pins[] = { DB8540_PIN_AJ23 };
-static const unsigned moduart0_oc2_1_pins[] = { DB8540_PIN_AG20,
- DB8540_PIN_AE23 };
-static const unsigned stmape_oc2_1_pins[] = { DB8540_PIN_AH20, DB8540_PIN_AG19,
- DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25 };
-static const unsigned u2_oc2_1_pins[] = { DB8540_PIN_T26, DB8540_PIN_AH21 };
-static const unsigned modxmip_oc2_1_pins[] = { DB8540_PIN_AE26,
- DB8540_PIN_AE24 };
-
-/* Other alt C3 column */
-static const unsigned modaccgpo_oc3_1_pins[] = { DB8540_PIN_AG11 };
-static const unsigned tpui_oc3_1_pins[] = { DB8540_PIN_M26, DB8540_PIN_M25,
- DB8540_PIN_M27, DB8540_PIN_N25, DB8540_PIN_M28, DB8540_PIN_N26,
- DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27, DB8540_PIN_N28,
- DB8540_PIN_P22, DB8540_PIN_P28, DB8540_PIN_P26, DB8540_PIN_T22,
- DB8540_PIN_R27, DB8540_PIN_P27, DB8540_PIN_R26, DB8540_PIN_R25,
- DB8540_PIN_U22, DB8540_PIN_T27, DB8540_PIN_AG22, DB8540_PIN_AF21,
- DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
- DB8540_PIN_AG20, DB8540_PIN_AE23, DB8540_PIN_AH20, DB8540_PIN_AG19,
- DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25, DB8540_PIN_T26 };
-
-/* Other alt C4 column */
-static const unsigned hwobs_oc4_1_pins[] = { DB8540_PIN_M26, DB8540_PIN_M25,
- DB8540_PIN_M27, DB8540_PIN_N25, DB8540_PIN_M28, DB8540_PIN_N26,
- DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27, DB8540_PIN_N28,
- DB8540_PIN_P22, DB8540_PIN_P28, DB8540_PIN_P26, DB8540_PIN_T22,
- DB8540_PIN_R27, DB8540_PIN_P27, DB8540_PIN_R26, DB8540_PIN_R25 };
-static const unsigned moduart1txrx_oc4_1_pins[] = { DB8540_PIN_U22,
- DB8540_PIN_T27 };
-static const unsigned moduart1rtscts_oc4_1_pins[] = { DB8540_PIN_AG22,
- DB8540_PIN_AF21 };
-static const unsigned modaccuarttxrx_oc4_1_pins[] = { DB8540_PIN_AF24,
- DB8540_PIN_AH22 };
-static const unsigned modaccuartrtscts_oc4_1_pins[] = { DB8540_PIN_AJ23,
- DB8540_PIN_AH21 };
-static const unsigned stmmod_oc4_1_pins[] = { DB8540_PIN_AH20, DB8540_PIN_AG19,
- DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25 };
-static const unsigned moduartstmmux_oc4_1_pins[] = { DB8540_PIN_T26 };
-
-#define DB8540_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \
- .npins = ARRAY_SIZE(a##_pins), .altsetting = b }
-
-static const struct nmk_pingroup nmk_db8540_groups[] = {
- /* Altfunction A column */
- DB8540_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(u1rxtx_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(u1ctsrts_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(ipi2c_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(ipi2c_a_2, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(msp0txrx_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(msp0tfstck_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(msp0rfsrck_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(mc0_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(msp1txrx_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(msp1_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(modobsclk_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(clkoutreq_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(lcdb_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(lcdvsi0_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(lcdvsi1_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(lcd_d0_d7_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(lcd_d8_d11_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(lcd_d12_d23_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(kp_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(mc2_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(ssp1_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(ssp0_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(ipgpio0_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(ipgpio1_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(modi2s_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(spi2_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(u2txrx_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(u2ctsrts_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(modsmb_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(msp2sck_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(msp2txdtcktfs_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(msp2rxd_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(hsit_a_2, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(clkout1_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(clkout1_a_2, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(clkout2_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(clkout2_a_2, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(msp4_a_1, NMK_GPIO_ALT_A),
- DB8540_PIN_GROUP(usb_a_1, NMK_GPIO_ALT_A),
- /* Altfunction B column */
- DB8540_PIN_GROUP(apetrig_b_1, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(modtrig_b_1, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(i2c4_b_1, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(i2c1_b_1, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(i2c2_b_1, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(i2c2_b_2, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(msp0txrx_b_1, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(i2c1_b_2, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(stmmod_b_1, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(moduartstmmux_b_1, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(msp1txrx_b_1, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(kp_b_1, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(u2txrx_b_1, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(sm_b_1, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(smcs0_b_1, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(smcs1_b_1, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(ipgpio7_b_1, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(ipgpio2_b_1, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(ipgpio3_b_1, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(i2c6_b_1, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(i2c5_b_1, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(u3txrx_b_1, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(u3ctsrts_b_1, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(i2c5_b_2, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(i2c4_b_2, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(u4txrx_b_1, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(u4ctsrts_b_1, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(ddrtrig_b_1, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(msp4_b_1, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(pwl_b_1, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(spi1_b_1, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(mc3_b_1, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(pwl_b_2, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(pwl_b_3, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(pwl_b_4, NMK_GPIO_ALT_B),
- DB8540_PIN_GROUP(u2txrx_b_2, NMK_GPIO_ALT_B),
- /* Altfunction C column */
- DB8540_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(ipgpio0_c_1, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(ipgpio1_c_1, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(ipgpio3_c_1, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(ipgpio2_c_1, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(u0_c_1, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(smcleale_c_1, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(ipgpio4_c_1, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(ipgpio5_c_1, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(ipgpio6_c_2, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(ipgpio7_c_1, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(stmape_c_1, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(u2rxtx_c_1, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(modobsresout_c_1, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(ipgpio2_c_2, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(ipgpio3_c_2, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(ipgpio4_c_2, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(ipgpio5_c_2, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(modaccgpo_c_1, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(modobspwrrst_c_1, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(mc5_c_1, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(smps0_c_1, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(moduart1_c_1, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(mc2rstn_c_1, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(i2c5_c_1, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(ipgpio0_c_2, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(ipgpio1_c_2, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(kp_c_1, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(modrf_c_1, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(smps1_c_1, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(i2c5_c_2, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(u4ctsrts_c_1, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(u3rxtx_c_1, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(msp4_c_1, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(mc4rstn_c_1, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(spi0_c_1, NMK_GPIO_ALT_C),
- DB8540_PIN_GROUP(i2c3_c_1, NMK_GPIO_ALT_C),
-
- /* Other alt C1 column */
- DB8540_PIN_GROUP(spi3_oc1_1, NMK_GPIO_ALT_C1),
- DB8540_PIN_GROUP(stmape_oc1_1, NMK_GPIO_ALT_C1),
- DB8540_PIN_GROUP(u2_oc1_1, NMK_GPIO_ALT_C1),
- DB8540_PIN_GROUP(remap0_oc1_1, NMK_GPIO_ALT_C1),
- DB8540_PIN_GROUP(remap1_oc1_1, NMK_GPIO_ALT_C1),
- DB8540_PIN_GROUP(modobsrefclk_oc1_1, NMK_GPIO_ALT_C1),
- DB8540_PIN_GROUP(modobspwrctrl_oc1_1, NMK_GPIO_ALT_C1),
- DB8540_PIN_GROUP(modobsclkout_oc1_1, NMK_GPIO_ALT_C1),
- DB8540_PIN_GROUP(moduart1_oc1_1, NMK_GPIO_ALT_C1),
- DB8540_PIN_GROUP(modprcmudbg_oc1_1, NMK_GPIO_ALT_C1),
- DB8540_PIN_GROUP(modobsresout_oc1_1, NMK_GPIO_ALT_C1),
- DB8540_PIN_GROUP(modaccgpo_oc1_1, NMK_GPIO_ALT_C1),
- DB8540_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C1),
- DB8540_PIN_GROUP(modxmip_oc1_1, NMK_GPIO_ALT_C1),
- DB8540_PIN_GROUP(i2c6_oc1_1, NMK_GPIO_ALT_C1),
- DB8540_PIN_GROUP(u2txrx_oc1_1, NMK_GPIO_ALT_C1),
- DB8540_PIN_GROUP(u2ctsrts_oc1_1, NMK_GPIO_ALT_C1),
-
- /* Other alt C2 column */
- DB8540_PIN_GROUP(sbag_oc2_1, NMK_GPIO_ALT_C2),
- DB8540_PIN_GROUP(hxclk_oc2_1, NMK_GPIO_ALT_C2),
- DB8540_PIN_GROUP(modaccuart_oc2_1, NMK_GPIO_ALT_C2),
- DB8540_PIN_GROUP(stmmod_oc2_1, NMK_GPIO_ALT_C2),
- DB8540_PIN_GROUP(moduartstmmux_oc2_1, NMK_GPIO_ALT_C2),
- DB8540_PIN_GROUP(hxgpio_oc2_1, NMK_GPIO_ALT_C2),
- DB8540_PIN_GROUP(sbag_oc2_2, NMK_GPIO_ALT_C2),
- DB8540_PIN_GROUP(modobsservice_oc2_1, NMK_GPIO_ALT_C2),
- DB8540_PIN_GROUP(moduart0_oc2_1, NMK_GPIO_ALT_C2),
- DB8540_PIN_GROUP(stmape_oc2_1, NMK_GPIO_ALT_C2),
- DB8540_PIN_GROUP(u2_oc2_1, NMK_GPIO_ALT_C2),
- DB8540_PIN_GROUP(modxmip_oc2_1, NMK_GPIO_ALT_C2),
-
- /* Other alt C3 column */
- DB8540_PIN_GROUP(modaccgpo_oc3_1, NMK_GPIO_ALT_C3),
- DB8540_PIN_GROUP(tpui_oc3_1, NMK_GPIO_ALT_C3),
-
- /* Other alt C4 column */
- DB8540_PIN_GROUP(hwobs_oc4_1, NMK_GPIO_ALT_C4),
- DB8540_PIN_GROUP(moduart1txrx_oc4_1, NMK_GPIO_ALT_C4),
- DB8540_PIN_GROUP(moduart1rtscts_oc4_1, NMK_GPIO_ALT_C4),
- DB8540_PIN_GROUP(modaccuarttxrx_oc4_1, NMK_GPIO_ALT_C4),
- DB8540_PIN_GROUP(modaccuartrtscts_oc4_1, NMK_GPIO_ALT_C4),
- DB8540_PIN_GROUP(stmmod_oc4_1, NMK_GPIO_ALT_C4),
- DB8540_PIN_GROUP(moduartstmmux_oc4_1, NMK_GPIO_ALT_C4),
-
-};
-
-/* We use this macro to define the groups applicable to a function */
-#define DB8540_FUNC_GROUPS(a, b...) \
-static const char * const a##_groups[] = { b };
-
-DB8540_FUNC_GROUPS(apetrig, "apetrig_b_1");
-DB8540_FUNC_GROUPS(clkout, "clkoutreq_a_1", "clkout1_a_1", "clkout1_a_2",
- "clkout2_a_1", "clkout2_a_2");
-DB8540_FUNC_GROUPS(ddrtrig, "ddrtrig_b_1");
-DB8540_FUNC_GROUPS(hsi, "hsir_a_1", "hsit_a_1", "hsit_a_2");
-DB8540_FUNC_GROUPS(hwobs, "hwobs_oc4_1");
-DB8540_FUNC_GROUPS(hx, "hxclk_oc2_1", "hxgpio_oc2_1");
-DB8540_FUNC_GROUPS(i2c0, "i2c0_a_1");
-DB8540_FUNC_GROUPS(i2c1, "i2c1_b_1", "i2c1_b_2");
-DB8540_FUNC_GROUPS(i2c2, "i2c2_b_1", "i2c2_b_2");
-DB8540_FUNC_GROUPS(i2c3, "i2c3_c_1", "i2c4_b_1");
-DB8540_FUNC_GROUPS(i2c4, "i2c4_b_2");
-DB8540_FUNC_GROUPS(i2c5, "i2c5_b_1", "i2c5_b_2", "i2c5_c_1", "i2c5_c_2");
-DB8540_FUNC_GROUPS(i2c6, "i2c6_b_1", "i2c6_oc1_1");
-/* The image processor has 8 GPIO pins that can be muxed out */
-DB8540_FUNC_GROUPS(ipgpio, "ipgpio0_a_1", "ipgpio0_c_1", "ipgpio0_c_2",
- "ipgpio1_a_1", "ipgpio1_c_1", "ipgpio1_c_2",
- "ipgpio2_b_1", "ipgpio2_c_1", "ipgpio2_c_2",
- "ipgpio3_b_1", "ipgpio3_c_1", "ipgpio3_c_2",
- "ipgpio4_c_1", "ipgpio4_c_2",
- "ipgpio5_c_1", "ipgpio5_c_2",
- "ipgpio6_c_1", "ipgpio6_c_2",
- "ipgpio7_b_1", "ipgpio7_c_1");
-DB8540_FUNC_GROUPS(ipi2c, "ipi2c_a_1", "ipi2c_a_2");
-DB8540_FUNC_GROUPS(kp, "kp_a_1", "kp_b_1", "kp_c_1", "kp_oc1_1");
-DB8540_FUNC_GROUPS(lcd, "lcd_d0_d7_a_1", "lcd_d12_d23_a_1", "lcd_d8_d11_a_1",
- "lcdvsi0_a_1", "lcdvsi1_a_1");
-DB8540_FUNC_GROUPS(lcdb, "lcdb_a_1");
-DB8540_FUNC_GROUPS(mc0, "mc0_a_1");
-DB8540_FUNC_GROUPS(mc1, "mc1_a_1", "mc1_a_2");
-DB8540_FUNC_GROUPS(mc2, "mc2_a_1", "mc2rstn_c_1");
-DB8540_FUNC_GROUPS(mc3, "mc3_b_1");
-DB8540_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1");
-DB8540_FUNC_GROUPS(mc5, "mc5_c_1");
-DB8540_FUNC_GROUPS(modaccgpo, "modaccgpo_c_1", "modaccgpo_oc1_1",
- "modaccgpo_oc3_1");
-DB8540_FUNC_GROUPS(modaccuart, "modaccuart_oc2_1", "modaccuarttxrx_oc4_1",
- "modaccuartrtccts_oc4_1");
-DB8540_FUNC_GROUPS(modi2s, "modi2s_a_1");
-DB8540_FUNC_GROUPS(modobs, "modobsclk_a_1", "modobsclkout_oc1_1",
- "modobspwrctrl_oc1_1", "modobspwrrst_c_1",
- "modobsrefclk_oc1_1", "modobsresout_c_1",
- "modobsresout_oc1_1", "modobsservice_oc2_1");
-DB8540_FUNC_GROUPS(modprcmudbg, "modprcmudbg_oc1_1");
-DB8540_FUNC_GROUPS(modrf, "modrf_c_1");
-DB8540_FUNC_GROUPS(modsmb, "modsmb_a_1");
-DB8540_FUNC_GROUPS(modtrig, "modtrig_b_1");
-DB8540_FUNC_GROUPS(moduart, "moduart1_c_1", "moduart1_oc1_1",
- "moduart1txrx_oc4_1", "moduart1rtscts_oc4_1", "moduart0_oc2_1");
-DB8540_FUNC_GROUPS(moduartstmmux, "moduartstmmux_b_1", "moduartstmmux_oc2_1",
- "moduartstmmux_oc4_1");
-DB8540_FUNC_GROUPS(modxmip, "modxmip_oc1_1", "modxmip_oc2_1");
-/*
- * MSP0 can only be on a certain set of pins, but the TX/RX pins can be
- * switched around by selecting the altfunction A or B.
- */
-DB8540_FUNC_GROUPS(msp0, "msp0rfsrck_a_1", "msp0tfstck_a_1", "msp0txrx_a_1",
- "msp0txrx_b_1");
-DB8540_FUNC_GROUPS(msp1, "msp1_a_1", "msp1txrx_a_1", "msp1txrx_b_1");
-DB8540_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2txdtcktfs_a_1", "msp2rxd_a_1");
-DB8540_FUNC_GROUPS(msp4, "msp4_a_1", "msp4_b_1", "msp4_c_1");
-DB8540_FUNC_GROUPS(pwl, "pwl_b_1", "pwl_b_2", "pwl_b_3", "pwl_b_4");
-DB8540_FUNC_GROUPS(remap, "remap0_oc1_1", "remap1_oc1_1");
-DB8540_FUNC_GROUPS(sbag, "sbag_oc2_1", "sbag_oc2_2");
-/* Select between CS0 on alt B or PS1 on alt C */
-DB8540_FUNC_GROUPS(sm, "sm_b_1", "smcleale_c_1", "smcs0_b_1", "smcs1_b_1",
- "smps0_c_1", "smps1_c_1");
-DB8540_FUNC_GROUPS(spi0, "spi0_c_1");
-DB8540_FUNC_GROUPS(spi1, "spi1_b_1");
-DB8540_FUNC_GROUPS(spi2, "spi2_a_1");
-DB8540_FUNC_GROUPS(spi3, "spi3_oc1_1");
-DB8540_FUNC_GROUPS(ssp0, "ssp0_a_1");
-DB8540_FUNC_GROUPS(ssp1, "ssp1_a_1");
-DB8540_FUNC_GROUPS(stmape, "stmape_c_1", "stmape_oc1_1", "stmape_oc2_1");
-DB8540_FUNC_GROUPS(stmmod, "stmmod_b_1", "stmmod_oc2_1", "stmmod_oc4_1");
-DB8540_FUNC_GROUPS(tpui, "tpui_oc3_1");
-DB8540_FUNC_GROUPS(u0, "u0_a_1", "u0_c_1");
-DB8540_FUNC_GROUPS(u1, "u1ctsrts_a_1", "u1rxtx_a_1");
-DB8540_FUNC_GROUPS(u2, "u2_oc1_1", "u2_oc2_1", "u2ctsrts_a_1", "u2ctsrts_oc1_1",
- "u2rxtx_c_1", "u2txrx_a_1", "u2txrx_b_1", "u2txrx_b_2",
- "u2txrx_oc1_1");
-DB8540_FUNC_GROUPS(u3, "u3ctsrts_b_1", "u3rxtx_c_1", "u3txrxa_b_1");
-DB8540_FUNC_GROUPS(u4, "u4ctsrts_b_1", "u4ctsrts_c_1", "u4txrx_b_1");
-DB8540_FUNC_GROUPS(usb, "usb_a_1");
-
-
-#define FUNCTION(fname) \
- { \
- .name = #fname, \
- .groups = fname##_groups, \
- .ngroups = ARRAY_SIZE(fname##_groups), \
- }
-
-static const struct nmk_function nmk_db8540_functions[] = {
- FUNCTION(apetrig),
- FUNCTION(clkout),
- FUNCTION(ddrtrig),
- FUNCTION(hsi),
- FUNCTION(hwobs),
- FUNCTION(hx),
- FUNCTION(i2c0),
- FUNCTION(i2c1),
- FUNCTION(i2c2),
- FUNCTION(i2c3),
- FUNCTION(i2c4),
- FUNCTION(i2c5),
- FUNCTION(i2c6),
- FUNCTION(ipgpio),
- FUNCTION(ipi2c),
- FUNCTION(kp),
- FUNCTION(lcd),
- FUNCTION(lcdb),
- FUNCTION(mc0),
- FUNCTION(mc1),
- FUNCTION(mc2),
- FUNCTION(mc3),
- FUNCTION(mc4),
- FUNCTION(mc5),
- FUNCTION(modaccgpo),
- FUNCTION(modaccuart),
- FUNCTION(modi2s),
- FUNCTION(modobs),
- FUNCTION(modprcmudbg),
- FUNCTION(modrf),
- FUNCTION(modsmb),
- FUNCTION(modtrig),
- FUNCTION(moduart),
- FUNCTION(modxmip),
- FUNCTION(msp0),
- FUNCTION(msp1),
- FUNCTION(msp2),
- FUNCTION(msp4),
- FUNCTION(pwl),
- FUNCTION(remap),
- FUNCTION(sbag),
- FUNCTION(sm),
- FUNCTION(spi0),
- FUNCTION(spi1),
- FUNCTION(spi2),
- FUNCTION(spi3),
- FUNCTION(ssp0),
- FUNCTION(ssp1),
- FUNCTION(stmape),
- FUNCTION(stmmod),
- FUNCTION(tpui),
- FUNCTION(u0),
- FUNCTION(u1),
- FUNCTION(u2),
- FUNCTION(u3),
- FUNCTION(u4),
- FUNCTION(usb)
-};
-
-static const struct prcm_gpiocr_altcx_pin_desc db8540_altcx_pins[] = {
- PRCM_GPIOCR_ALTCX(8, true, PRCM_IDX_GPIOCR1, 20, /* SPI3_CLK */
- false, 0, 0,
- false, 0, 0,
- false, 0, 0
- ),
- PRCM_GPIOCR_ALTCX(9, true, PRCM_IDX_GPIOCR1, 20, /* SPI3_RXD */
- false, 0, 0,
- false, 0, 0,
- false, 0, 0
- ),
- PRCM_GPIOCR_ALTCX(10, true, PRCM_IDX_GPIOCR1, 20, /* SPI3_FRM */
- false, 0, 0,
- false, 0, 0,
- false, 0, 0
- ),
- PRCM_GPIOCR_ALTCX(11, true, PRCM_IDX_GPIOCR1, 20, /* SPI3_TXD */
- false, 0, 0,
- false, 0, 0,
- false, 0, 0
- ),
- PRCM_GPIOCR_ALTCX(23, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_CLK_a */
- true, PRCM_IDX_GPIOCR2, 10, /* SBAG_CLK_a */
- false, 0, 0,
- false, 0, 0
- ),
- PRCM_GPIOCR_ALTCX(24, true, PRCM_IDX_GPIOCR3, 30, /* U2_RXD_g */
- true, PRCM_IDX_GPIOCR2, 10, /* SBAG_VAL_a */
- false, 0, 0,
- false, 0, 0
- ),
- PRCM_GPIOCR_ALTCX(25, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[0] */
- true, PRCM_IDX_GPIOCR2, 10, /* SBAG_D_a[0] */
- false, 0, 0,
- false, 0, 0
- ),
- PRCM_GPIOCR_ALTCX(26, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[1] */
- true, PRCM_IDX_GPIOCR2, 10, /* SBAG_D_a[1] */
- false, 0, 0,
- false, 0, 0
- ),
- PRCM_GPIOCR_ALTCX(27, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[2] */
- true, PRCM_IDX_GPIOCR2, 10, /* SBAG_D_a[2] */
- false, 0, 0,
- false, 0, 0
- ),
- PRCM_GPIOCR_ALTCX(28, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[3] */
- true, PRCM_IDX_GPIOCR2, 10, /* SBAG_D_a[3] */
- false, 0, 0,
- false, 0, 0
- ),
- PRCM_GPIOCR_ALTCX(64, true, PRCM_IDX_GPIOCR1, 15, /* MODOBS_REFCLK_REQ */
- false, 0, 0,
- true, PRCM_IDX_GPIOCR1, 2, /* TPIU_CTL */
- true, PRCM_IDX_GPIOCR2, 23 /* HW_OBS_APE_PRCMU[17] */
- ),
- PRCM_GPIOCR_ALTCX(65, true, PRCM_IDX_GPIOCR1, 19, /* MODOBS_PWRCTRL0 */
- true, PRCM_IDX_GPIOCR1, 24, /* Hx_CLK */
- true, PRCM_IDX_GPIOCR1, 2, /* TPIU_CLK */
- true, PRCM_IDX_GPIOCR2, 24 /* HW_OBS_APE_PRCMU[16] */
- ),
- PRCM_GPIOCR_ALTCX(66, true, PRCM_IDX_GPIOCR1, 15, /* MODOBS_CLKOUT1 */
- false, 0, 0,
- true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[15] */
- true, PRCM_IDX_GPIOCR2, 25 /* HW_OBS_APE_PRCMU[15] */
- ),
- PRCM_GPIOCR_ALTCX(67, true, PRCM_IDX_GPIOCR1, 1, /* MODUART1_TXD_a */
- true, PRCM_IDX_GPIOCR1, 6, /* MODACCUART_TXD_a */
- true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[14] */
- true, PRCM_IDX_GPIOCR2, 26 /* HW_OBS_APE_PRCMU[14] */
- ),
- PRCM_GPIOCR_ALTCX(70, true, PRCM_IDX_GPIOCR3, 6, /* MOD_PRCMU_DEBUG[17] */
- true, PRCM_IDX_GPIOCR1, 10, /* STMMOD_CLK_b */
- true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[13] */
- true, PRCM_IDX_GPIOCR2, 27 /* HW_OBS_APE_PRCMU[13] */
- ),
- PRCM_GPIOCR_ALTCX(71, true, PRCM_IDX_GPIOCR3, 6, /* MOD_PRCMU_DEBUG[16] */
- true, PRCM_IDX_GPIOCR1, 10, /* STMMOD_DAT_b[3] */
- true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[12] */
- true, PRCM_IDX_GPIOCR2, 27 /* HW_OBS_APE_PRCMU[12] */
- ),
- PRCM_GPIOCR_ALTCX(72, true, PRCM_IDX_GPIOCR3, 6, /* MOD_PRCMU_DEBUG[15] */
- true, PRCM_IDX_GPIOCR1, 10, /* STMMOD_DAT_b[2] */
- true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[11] */
- true, PRCM_IDX_GPIOCR2, 27 /* HW_OBS_APE_PRCMU[11] */
- ),
- PRCM_GPIOCR_ALTCX(73, true, PRCM_IDX_GPIOCR3, 6, /* MOD_PRCMU_DEBUG[14] */
- true, PRCM_IDX_GPIOCR1, 10, /* STMMOD_DAT_b[1] */
- true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[10] */
- true, PRCM_IDX_GPIOCR2, 27 /* HW_OBS_APE_PRCMU[10] */
- ),
- PRCM_GPIOCR_ALTCX(74, true, PRCM_IDX_GPIOCR3, 6, /* MOD_PRCMU_DEBUG[13] */
- true, PRCM_IDX_GPIOCR1, 10, /* STMMOD_DAT_b[0] */
- true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[9] */
- true, PRCM_IDX_GPIOCR2, 27 /* HW_OBS_APE_PRCMU[9] */
- ),
- PRCM_GPIOCR_ALTCX(75, true, PRCM_IDX_GPIOCR1, 12, /* MODOBS_RESOUT0_N */
- true, PRCM_IDX_GPIOCR2, 1, /* MODUART_STMMUX_RXD_b */
- true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[8] */
- true, PRCM_IDX_GPIOCR2, 28 /* HW_OBS_APE_PRCMU[8] */
- ),
- PRCM_GPIOCR_ALTCX(76, true, PRCM_IDX_GPIOCR3, 7, /* MOD_PRCMU_DEBUG[12] */
- true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[7] */
- true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[7] */
- true, PRCM_IDX_GPIOCR2, 29 /* HW_OBS_APE_PRCMU[7] */
- ),
- PRCM_GPIOCR_ALTCX(77, true, PRCM_IDX_GPIOCR3, 7, /* MOD_PRCMU_DEBUG[11] */
- true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[6] */
- true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[6] */
- true, PRCM_IDX_GPIOCR2, 29 /* HW_OBS_APE_PRCMU[6] */
- ),
- PRCM_GPIOCR_ALTCX(78, true, PRCM_IDX_GPIOCR3, 7, /* MOD_PRCMU_DEBUG[10] */
- true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[5] */
- true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[5] */
- true, PRCM_IDX_GPIOCR2, 29 /* HW_OBS_APE_PRCMU[5] */
- ),
- PRCM_GPIOCR_ALTCX(79, true, PRCM_IDX_GPIOCR3, 7, /* MOD_PRCMU_DEBUG[9] */
- true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[4] */
- true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[4] */
- true, PRCM_IDX_GPIOCR2, 29 /* HW_OBS_APE_PRCMU[4] */
- ),
- PRCM_GPIOCR_ALTCX(80, true, PRCM_IDX_GPIOCR1, 26, /* MODACC_GPO[0] */
- true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[3] */
- true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[3] */
- true, PRCM_IDX_GPIOCR2, 30 /* HW_OBS_APE_PRCMU[3] */
- ),
- PRCM_GPIOCR_ALTCX(81, true, PRCM_IDX_GPIOCR2, 17, /* MODACC_GPO[1] */
- true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[2] */
- true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[2] */
- true, PRCM_IDX_GPIOCR2, 30 /* HW_OBS_APE_PRCMU[2] */
- ),
- PRCM_GPIOCR_ALTCX(82, true, PRCM_IDX_GPIOCR3, 8, /* MOD_PRCMU_DEBUG[8] */
- true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[1] */
- true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[1] */
- true, PRCM_IDX_GPIOCR2, 31 /* HW_OBS_APE_PRCMU[1] */
- ),
- PRCM_GPIOCR_ALTCX(83, true, PRCM_IDX_GPIOCR3, 8, /* MOD_PRCMU_DEBUG[7] */
- true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[0] */
- true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[0] */
- true, PRCM_IDX_GPIOCR2, 31 /* HW_OBS_APE_PRCMU[0] */
- ),
- PRCM_GPIOCR_ALTCX(84, true, PRCM_IDX_GPIOCR3, 9, /* MOD_PRCMU_DEBUG[6] */
- true, PRCM_IDX_GPIOCR1, 8, /* SBAG_CLK_b */
- true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[23] */
- true, PRCM_IDX_GPIOCR1, 16 /* MODUART1_RXD_b */
- ),
- PRCM_GPIOCR_ALTCX(85, true, PRCM_IDX_GPIOCR3, 9, /* MOD_PRCMU_DEBUG[5] */
- true, PRCM_IDX_GPIOCR1, 8, /* SBAG_D_b[3] */
- true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[22] */
- true, PRCM_IDX_GPIOCR1, 16 /* MODUART1_TXD_b */
- ),
- PRCM_GPIOCR_ALTCX(86, true, PRCM_IDX_GPIOCR3, 9, /* MOD_PRCMU_DEBUG[0] */
- true, PRCM_IDX_GPIOCR2, 18, /* STMAPE_DAT_b[0] */
- true, PRCM_IDX_GPIOCR1, 14, /* TPIU_D[25] */
- true, PRCM_IDX_GPIOCR1, 11 /* STMMOD_DAT_c[0] */
- ),
- PRCM_GPIOCR_ALTCX(87, true, PRCM_IDX_GPIOCR3, 0, /* MODACC_GPO_a[5] */
- true, PRCM_IDX_GPIOCR2, 3, /* U2_RXD_c */
- true, PRCM_IDX_GPIOCR1, 4, /* TPIU_D[24] */
- true, PRCM_IDX_GPIOCR1, 21 /* MODUART_STMMUX_RXD_c */
- ),
- PRCM_GPIOCR_ALTCX(151, true, PRCM_IDX_GPIOCR1, 18, /* REMAP0 */
- false, 0, 0,
- false, 0, 0,
- false, 0, 0
- ),
- PRCM_GPIOCR_ALTCX(152, true, PRCM_IDX_GPIOCR1, 18, /* REMAP1 */
- false, 0, 0,
- false, 0, 0,
- false, 0, 0
- ),
- PRCM_GPIOCR_ALTCX(153, true, PRCM_IDX_GPIOCR3, 2, /* KP_O_b[6] */
- true, PRCM_IDX_GPIOCR1, 8, /* SBAG_D_b[2] */
- true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[21] */
- true, PRCM_IDX_GPIOCR1, 0 /* MODUART1_RTS */
- ),
- PRCM_GPIOCR_ALTCX(154, true, PRCM_IDX_GPIOCR3, 2, /* KP_I_b[6] */
- true, PRCM_IDX_GPIOCR1, 8, /* SBAG_D_b[1] */
- true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[20] */
- true, PRCM_IDX_GPIOCR1, 0 /* MODUART1_CTS */
- ),
- PRCM_GPIOCR_ALTCX(155, true, PRCM_IDX_GPIOCR3, 3, /* KP_O_b[5] */
- true, PRCM_IDX_GPIOCR1, 8, /* SBAG_D_b[0] */
- true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[19] */
- true, PRCM_IDX_GPIOCR1, 5 /* MODACCUART_RXD_c */
- ),
- PRCM_GPIOCR_ALTCX(156, true, PRCM_IDX_GPIOCR3, 3, /* KP_O_b[4] */
- true, PRCM_IDX_GPIOCR1, 8, /* SBAG_VAL_b */
- true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[18] */
- true, PRCM_IDX_GPIOCR1, 5 /* MODACCUART_TXD_b */
- ),
- PRCM_GPIOCR_ALTCX(157, true, PRCM_IDX_GPIOCR3, 4, /* KP_I_b[5] */
- true, PRCM_IDX_GPIOCR1, 23, /* MODOBS_SERVICE_N */
- true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[17] */
- true, PRCM_IDX_GPIOCR1, 14 /* MODACCUART_RTS */
- ),
- PRCM_GPIOCR_ALTCX(158, true, PRCM_IDX_GPIOCR3, 4, /* KP_I_b[4] */
- true, PRCM_IDX_GPIOCR2, 0, /* U2_TXD_c */
- true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[16] */
- true, PRCM_IDX_GPIOCR1, 14 /* MODACCUART_CTS */
- ),
- PRCM_GPIOCR_ALTCX(159, true, PRCM_IDX_GPIOCR3, 5, /* KP_O_b[3] */
- true, PRCM_IDX_GPIOCR3, 10, /* MODUART0_RXD */
- true, PRCM_IDX_GPIOCR1, 4, /* TPIU_D[31] */
- false, 0, 0
- ),
- PRCM_GPIOCR_ALTCX(160, true, PRCM_IDX_GPIOCR3, 5, /* KP_I_b[3] */
- true, PRCM_IDX_GPIOCR3, 10, /* MODUART0_TXD */
- true, PRCM_IDX_GPIOCR1, 4, /* TPIU_D[30] */
- false, 0, 0
- ),
- PRCM_GPIOCR_ALTCX(161, true, PRCM_IDX_GPIOCR3, 9, /* MOD_PRCMU_DEBUG[4] */
- true, PRCM_IDX_GPIOCR2, 18, /* STMAPE_CLK_b */
- true, PRCM_IDX_GPIOCR1, 4, /* TPIU_D[29] */
- true, PRCM_IDX_GPIOCR1, 11 /* STMMOD_CLK_c */
- ),
- PRCM_GPIOCR_ALTCX(162, true, PRCM_IDX_GPIOCR3, 9, /* MOD_PRCMU_DEBUG[3] */
- true, PRCM_IDX_GPIOCR2, 18, /* STMAPE_DAT_b[3] */
- true, PRCM_IDX_GPIOCR1, 4, /* TPIU_D[28] */
- true, PRCM_IDX_GPIOCR1, 11 /* STMMOD_DAT_c[3] */
- ),
- PRCM_GPIOCR_ALTCX(163, true, PRCM_IDX_GPIOCR3, 9, /* MOD_PRCMU_DEBUG[2] */
- true, PRCM_IDX_GPIOCR2, 18, /* STMAPE_DAT_b[2] */
- true, PRCM_IDX_GPIOCR1, 4, /* TPIU_D[27] */
- true, PRCM_IDX_GPIOCR1, 11 /* STMMOD_DAT_c[2] */
- ),
- PRCM_GPIOCR_ALTCX(164, true, PRCM_IDX_GPIOCR3, 9, /* MOD_PRCMU_DEBUG[1] */
- true, PRCM_IDX_GPIOCR2, 18, /* STMAPE_DAT_b[1] */
- true, PRCM_IDX_GPIOCR1, 4, /* TPIU_D[26] */
- true, PRCM_IDX_GPIOCR1, 11 /* STMMOD_DAT_c[1] */
- ),
- PRCM_GPIOCR_ALTCX(204, true, PRCM_IDX_GPIOCR2, 2, /* U2_RXD_f */
- false, 0, 0,
- false, 0, 0,
- false, 0, 0
- ),
- PRCM_GPIOCR_ALTCX(205, true, PRCM_IDX_GPIOCR2, 2, /* U2_TXD_f */
- false, 0, 0,
- false, 0, 0,
- false, 0, 0
- ),
- PRCM_GPIOCR_ALTCX(206, true, PRCM_IDX_GPIOCR2, 2, /* U2_CTSn_b */
- false, 0, 0,
- false, 0, 0,
- false, 0, 0
- ),
- PRCM_GPIOCR_ALTCX(207, true, PRCM_IDX_GPIOCR2, 2, /* U2_RTSn_b */
- false, 0, 0,
- false, 0, 0,
- false, 0, 0
- ),
-};
-
-static const u16 db8540_prcm_gpiocr_regs[] = {
- [PRCM_IDX_GPIOCR1] = 0x138,
- [PRCM_IDX_GPIOCR2] = 0x574,
- [PRCM_IDX_GPIOCR3] = 0x2bc,
-};
-
-static const struct nmk_pinctrl_soc_data nmk_db8540_soc = {
- .pins = nmk_db8540_pins,
- .npins = ARRAY_SIZE(nmk_db8540_pins),
- .functions = nmk_db8540_functions,
- .nfunctions = ARRAY_SIZE(nmk_db8540_functions),
- .groups = nmk_db8540_groups,
- .ngroups = ARRAY_SIZE(nmk_db8540_groups),
- .altcx_pins = db8540_altcx_pins,
- .npins_altcx = ARRAY_SIZE(db8540_altcx_pins),
- .prcm_gpiocr_registers = db8540_prcm_gpiocr_regs,
-};
-
-void nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc)
-{
- *soc = &nmk_db8540_soc;
-}
diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c b/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c
index 7e814764da7d..8d944bb3a036 100644
--- a/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c
+++ b/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c
@@ -291,7 +291,17 @@ static const unsigned i2cusb_b_1_pins[] = { STN8815_PIN_C21, STN8815_PIN_C20 };
static const unsigned clcd_16_23_b_1_pins[] = { STN8815_PIN_AB6,
STN8815_PIN_AA6, STN8815_PIN_Y6, STN8815_PIN_Y5, STN8815_PIN_AA5,
STN8815_PIN_AB5, STN8815_PIN_AB4, STN8815_PIN_Y4 };
-
+/* Full-speed and high-speed USB pins */
+static const unsigned usbfs_b_1_pins[] = { STN8815_PIN_E21, STN8815_PIN_E20,
+ STN8815_PIN_C22, STN8815_PIN_D21,
+ STN8815_PIN_D20, STN8815_PIN_C21,
+ STN8815_PIN_C20 };
+static const unsigned usbhs_c_1_pins[] = { STN8815_PIN_E21, STN8815_PIN_E20,
+ STN8815_PIN_C20, STN8815_PIN_C19,
+ STN8815_PIN_C22, STN8815_PIN_D21,
+ STN8815_PIN_D20, STN8815_PIN_C21,
+ STN8815_PIN_C16, STN8815_PIN_A15,
+ STN8815_PIN_D17, STN8815_PIN_C17 };
#define STN8815_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \
.npins = ARRAY_SIZE(a##_pins), .altsetting = b }
@@ -308,6 +318,8 @@ static const struct nmk_pingroup nmk_stn8815_groups[] = {
STN8815_PIN_GROUP(u1_b_1, NMK_GPIO_ALT_B),
STN8815_PIN_GROUP(i2cusb_b_1, NMK_GPIO_ALT_B),
STN8815_PIN_GROUP(clcd_16_23_b_1, NMK_GPIO_ALT_B),
+ STN8815_PIN_GROUP(usbfs_b_1, NMK_GPIO_ALT_B),
+ STN8815_PIN_GROUP(usbhs_c_1, NMK_GPIO_ALT_C),
};
/* We use this macro to define the groups applicable to a function */
@@ -321,6 +333,7 @@ STN8815_FUNC_GROUPS(i2c1, "i2c1_a_1");
STN8815_FUNC_GROUPS(i2c0, "i2c0_a_1");
STN8815_FUNC_GROUPS(i2cusb, "i2cusb_b_1");
STN8815_FUNC_GROUPS(clcd, "clcd_16_23_b_1");
+STN8815_FUNC_GROUPS(usb, "usbfs_b_1", "usbhs_c_1");
#define FUNCTION(fname) \
{ \
@@ -337,6 +350,7 @@ static const struct nmk_function nmk_stn8815_functions[] = {
FUNCTION(i2c0),
FUNCTION(i2cusb),
FUNCTION(clcd),
+ FUNCTION(usb),
};
static const struct nmk_pinctrl_soc_data nmk_stn8815_soc = {
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 61d830c2bc17..04ae139671c8 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -40,6 +40,19 @@
#include "pinctrl-utils.h"
#include "pinctrl-amd.h"
+static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
+{
+ unsigned long flags;
+ u32 pin_reg;
+ struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+
+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
+ pin_reg = readl(gpio_dev->base + offset * 4);
+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
+
+ return !(pin_reg & BIT(OUTPUT_ENABLE_OFF));
+}
+
static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
{
unsigned long flags;
@@ -335,12 +348,21 @@ static void amd_gpio_irq_enable(struct irq_data *d)
unsigned long flags;
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+ u32 mask = BIT(INTERRUPT_ENABLE_OFF) | BIT(INTERRUPT_MASK_OFF);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
pin_reg |= BIT(INTERRUPT_MASK_OFF);
writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
+ /*
+ * When debounce logic is enabled it takes ~900 us before interrupts
+ * can be enabled. During this "debounce warm up" period the
+ * "INTERRUPT_ENABLE" bit will read as 0. Poll the bit here until it
+ * reads back as 1, signaling that interrupts are now enabled.
+ */
+ while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
+ continue;
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
@@ -845,6 +867,7 @@ static int amd_gpio_probe(struct platform_device *pdev)
#endif
gpio_dev->pdev = pdev;
+ gpio_dev->gc.get_direction = amd_gpio_get_direction;
gpio_dev->gc.direction_input = amd_gpio_direction_input;
gpio_dev->gc.direction_output = amd_gpio_direction_output;
gpio_dev->gc.get = amd_gpio_get_value;
diff --git a/drivers/pinctrl/pinctrl-artpec6.c b/drivers/pinctrl/pinctrl-artpec6.c
index e33781cd0a05..d89dc43c5757 100644
--- a/drivers/pinctrl/pinctrl-artpec6.c
+++ b/drivers/pinctrl/pinctrl-artpec6.c
@@ -277,37 +277,61 @@ static const struct artpec6_pin_group artpec6_pin_groups[] = {
.config = ARTPEC6_CONFIG_3,
},
{
- .name = "uart0grp0",
+ .name = "uart0grp0", /* All pins. */
.pins = uart0_pins0,
.num_pins = ARRAY_SIZE(uart0_pins0),
.config = ARTPEC6_CONFIG_1,
},
{
- .name = "uart0grp1",
+ .name = "uart0grp1", /* RX/TX and RTS/CTS */
.pins = uart0_pins1,
.num_pins = ARRAY_SIZE(uart0_pins1),
.config = ARTPEC6_CONFIG_1,
},
{
- .name = "uart1grp0",
+ .name = "uart0grp2", /* Only RX/TX pins. */
+ .pins = uart0_pins1,
+ .num_pins = ARRAY_SIZE(uart0_pins1) - 2,
+ .config = ARTPEC6_CONFIG_1,
+ },
+ {
+ .name = "uart1grp0", /* RX/TX and RTS/CTS */
.pins = uart1_pins0,
.num_pins = ARRAY_SIZE(uart1_pins0),
.config = ARTPEC6_CONFIG_2,
},
{
- .name = "uart2grp0",
+ .name = "uart1grp1", /* Only RX/TX pins. */
+ .pins = uart1_pins0,
+ .num_pins = 2,
+ .config = ARTPEC6_CONFIG_2,
+ },
+ {
+ .name = "uart2grp0", /* Full pinout */
.pins = uart2_pins0,
.num_pins = ARRAY_SIZE(uart2_pins0),
.config = ARTPEC6_CONFIG_1,
},
{
- .name = "uart2grp1",
+ .name = "uart2grp1", /* RX/TX and RTS/CTS */
.pins = uart2_pins1,
.num_pins = ARRAY_SIZE(uart2_pins1),
.config = ARTPEC6_CONFIG_1,
},
{
- .name = "uart3grp0",
+ .name = "uart2grp2", /* Only RX/TX */
+ .pins = uart2_pins1,
+ .num_pins = 2,
+ .config = ARTPEC6_CONFIG_1,
+ },
+ {
+ .name = "uart3grp0", /* RX/TX and CTS/RTS */
+ .pins = uart3_pins0,
+ .num_pins = ARRAY_SIZE(uart3_pins0),
+ .config = ARTPEC6_CONFIG_0,
+ },
+ {
+ .name = "uart3grp1", /* Only RX/TX */
.pins = uart3_pins0,
.num_pins = ARRAY_SIZE(uart3_pins0),
.config = ARTPEC6_CONFIG_0,
@@ -319,13 +343,19 @@ static const struct artpec6_pin_group artpec6_pin_groups[] = {
.config = ARTPEC6_CONFIG_2,
},
{
- .name = "uart5grp0",
+ .name = "uart5grp0", /* TX/RX and RTS/CTS */
.pins = uart5_pins0,
.num_pins = ARRAY_SIZE(uart5_pins0),
.config = ARTPEC6_CONFIG_2,
},
{
- .name = "uart5nocts",
+ .name = "uart5grp1", /* Only TX/RX */
+ .pins = uart5_pins0,
+ .num_pins = 2,
+ .config = ARTPEC6_CONFIG_2,
+ },
+ {
+ .name = "uart5nocts", /* TX/RX/RTS */
.pins = uart5_pins0,
.num_pins = ARRAY_SIZE(uart5_pins0) - 1,
.config = ARTPEC6_CONFIG_2,
@@ -457,8 +487,9 @@ static const char * const gpiogrps[] = {
"cpuclkoutgrp0", "udlclkoutgrp0", "i2c1grp0", "i2c2grp0",
"i2c3grp0", "i2s0grp0", "i2s1grp0", "i2srefclkgrp0",
"spi0grp0", "spi1grp0", "pciedebuggrp0", "uart0grp0",
- "uart0grp1", "uart1grp0", "uart2grp0", "uart2grp1",
- "uart4grp0", "uart5grp0",
+ "uart0grp1", "uart0grp2", "uart1grp0", "uart1grp1",
+ "uart2grp0", "uart2grp1", "uart2grp2", "uart4grp0", "uart5grp0",
+ "uart5grp1", "uart5nocts",
};
static const char * const cpuclkoutgrps[] = { "cpuclkoutgrp0" };
static const char * const udlclkoutgrps[] = { "udlclkoutgrp0" };
@@ -471,12 +502,15 @@ static const char * const i2srefclkgrps[] = { "i2srefclkgrp0" };
static const char * const spi0grps[] = { "spi0grp0" };
static const char * const spi1grps[] = { "spi1grp0" };
static const char * const pciedebuggrps[] = { "pciedebuggrp0" };
-static const char * const uart0grps[] = { "uart0grp0", "uart0grp1" };
-static const char * const uart1grps[] = { "uart1grp0" };
-static const char * const uart2grps[] = { "uart2grp0", "uart2grp1" };
+static const char * const uart0grps[] = { "uart0grp0", "uart0grp1",
+ "uart0grp2" };
+static const char * const uart1grps[] = { "uart1grp0", "uart1grp1" };
+static const char * const uart2grps[] = { "uart2grp0", "uart2grp1",
+ "uart2grp2" };
static const char * const uart3grps[] = { "uart3grp0" };
-static const char * const uart4grps[] = { "uart4grp0" };
-static const char * const uart5grps[] = { "uart5grp0", "uart5nocts" };
+static const char * const uart4grps[] = { "uart4grp0", "uart4grp1" };
+static const char * const uart5grps[] = { "uart5grp0", "uart5grp1",
+ "uart5nocts" };
static const char * const nandgrps[] = { "nandgrp0" };
static const char * const sdio0grps[] = { "sdio0grp0" };
static const char * const sdio1grps[] = { "sdio1grp0" };
@@ -601,7 +635,7 @@ static int artpec6_pmx_get_functions_count(struct pinctrl_dev *pctldev)
}
static const char *artpec6_pmx_get_fname(struct pinctrl_dev *pctldev,
- unsigned int function)
+ unsigned int function)
{
return artpec6_pmx_functions[function].name;
}
diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c
index 644c5beb05cb..022307dd4b54 100644
--- a/drivers/pinctrl/pinctrl-mcp23s08.c
+++ b/drivers/pinctrl/pinctrl-mcp23s08.c
@@ -771,6 +771,9 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
{
int status, ret;
bool mirror = false;
+ bool open_drain = false;
+ struct regmap_config *one_regmap_config = NULL;
+ int raw_chip_address = (addr & ~0x40) >> 1;
mutex_init(&mcp->lock);
@@ -791,19 +794,33 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
switch (type) {
#ifdef CONFIG_SPI_MASTER
case MCP_TYPE_S08:
- mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp,
- &mcp23x08_regmap);
- mcp->reg_shift = 0;
- mcp->chip.ngpio = 8;
- mcp->chip.label = "mcp23s08";
- break;
-
case MCP_TYPE_S17:
+ switch (type) {
+ case MCP_TYPE_S08:
+ one_regmap_config =
+ devm_kmemdup(dev, &mcp23x08_regmap,
+ sizeof(struct regmap_config), GFP_KERNEL);
+ mcp->reg_shift = 0;
+ mcp->chip.ngpio = 8;
+ mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL,
+ "mcp23s08.%d", raw_chip_address);
+ break;
+ case MCP_TYPE_S17:
+ one_regmap_config =
+ devm_kmemdup(dev, &mcp23x17_regmap,
+ sizeof(struct regmap_config), GFP_KERNEL);
+ mcp->reg_shift = 1;
+ mcp->chip.ngpio = 16;
+ mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL,
+ "mcp23s17.%d", raw_chip_address);
+ break;
+ }
+ if (!one_regmap_config)
+ return -ENOMEM;
+
+ one_regmap_config->name = devm_kasprintf(dev, GFP_KERNEL, "%d", raw_chip_address);
mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp,
- &mcp23x17_regmap);
- mcp->reg_shift = 1;
- mcp->chip.ngpio = 16;
- mcp->chip.label = "mcp23s17";
+ one_regmap_config);
break;
case MCP_TYPE_S18:
@@ -867,10 +884,11 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
"microchip,irq-active-high");
mirror = device_property_read_bool(dev, "microchip,irq-mirror");
+ open_drain = device_property_read_bool(dev, "drive-open-drain");
}
if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror ||
- mcp->irq_active_high) {
+ mcp->irq_active_high || open_drain) {
/* mcp23s17 has IOCON twice, make sure they are in sync */
status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8));
status |= IOCON_HAEN | (IOCON_HAEN << 8);
@@ -882,6 +900,9 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
if (mirror)
status |= IOCON_MIRROR | (IOCON_MIRROR << 8);
+ if (open_drain)
+ status |= IOCON_ODR | (IOCON_ODR << 8);
+
if (type == MCP_TYPE_S18 || type == MCP_TYPE_018)
status |= IOCON_INTCC | (IOCON_INTCC << 8);
@@ -900,7 +921,14 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
if (ret < 0)
goto fail;
- mcp->pinctrl_desc.name = "mcp23xxx-pinctrl";
+ if (one_regmap_config) {
+ mcp->pinctrl_desc.name = devm_kasprintf(dev, GFP_KERNEL,
+ "mcp23xxx-pinctrl.%d", raw_chip_address);
+ if (!mcp->pinctrl_desc.name)
+ return -ENOMEM;
+ } else {
+ mcp->pinctrl_desc.name = "mcp23xxx-pinctrl";
+ }
mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops;
mcp->pinctrl_desc.confops = &mcp_pinconf_ops;
mcp->pinctrl_desc.npins = mcp->chip.ngpio;
diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c
index 01a50d969111..b5b3547fdcb2 100644
--- a/drivers/pinctrl/pinctrl-ocelot.c
+++ b/drivers/pinctrl/pinctrl-ocelot.c
@@ -252,7 +252,7 @@ static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev,
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
regmap_update_bits(info->map, OCELOT_GPIO_OE, BIT(pin),
- input ? BIT(pin) : 0);
+ input ? 0 : BIT(pin));
return 0;
}
@@ -462,7 +462,7 @@ static const struct of_device_id ocelot_pinctrl_of_match[] = {
{},
};
-int ocelot_pinctrl_probe(struct platform_device *pdev)
+static int ocelot_pinctrl_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct ocelot_pinctrl *info;
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index cec75379f936..a7c5eb39b1eb 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -391,9 +391,25 @@ static int pcs_request_gpio(struct pinctrl_dev *pctldev,
|| pin < frange->offset)
continue;
mux_bytes = pcs->width / BITS_PER_BYTE;
- data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask;
- data |= frange->gpiofunc;
- pcs->write(data, pcs->base + pin * mux_bytes);
+
+ if (pcs->bits_per_mux) {
+ int byte_num, offset, pin_shift;
+
+ byte_num = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
+ offset = (byte_num / mux_bytes) * mux_bytes;
+ pin_shift = pin % (pcs->width / pcs->bits_per_pin) *
+ pcs->bits_per_pin;
+
+ data = pcs->read(pcs->base + offset);
+ data &= ~(pcs->fmask << pin_shift);
+ data |= frange->gpiofunc << pin_shift;
+ pcs->write(data, pcs->base + offset);
+ } else {
+ data = pcs->read(pcs->base + pin * mux_bytes);
+ data &= ~pcs->fmask;
+ data |= frange->gpiofunc;
+ pcs->write(data, pcs->base + pin * mux_bytes);
+ }
break;
}
return 0;
diff --git a/drivers/pinctrl/pinctrl-tz1090-pdc.c b/drivers/pinctrl/pinctrl-tz1090-pdc.c
deleted file mode 100644
index b16d1c96b7eb..000000000000
--- a/drivers/pinctrl/pinctrl-tz1090-pdc.c
+++ /dev/null
@@ -1,989 +0,0 @@
-/*
- * Pinctrl driver for the Toumaz Xenif TZ1090 PowerDown Controller pins
- *
- * Copyright (c) 2013, Imagination Technologies Ltd.
- *
- * Derived from Tegra code:
- * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
- *
- * Derived from code:
- * Copyright (C) 2010 Google, Inc.
- * Copyright (C) 2010 NVIDIA Corporation
- * Copyright (C) 2009-2011 ST-Ericsson AB
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/bitops.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/slab.h>
-
-/*
- * The registers may be shared with other threads/cores, so we need to use the
- * metag global lock2 for atomicity.
- */
-#include <asm/global_lock.h>
-
-#include "core.h"
-#include "pinconf.h"
-
-/* Register offsets from bank base address */
-#define REG_GPIO_CONTROL0 0x00
-#define REG_GPIO_CONTROL2 0x08
-
-/* Register field information */
-#define REG_GPIO_CONTROL2_PU_PD_S 16
-#define REG_GPIO_CONTROL2_PDC_POS_S 4
-#define REG_GPIO_CONTROL2_PDC_DR_S 2
-#define REG_GPIO_CONTROL2_PDC_SR_S 1
-#define REG_GPIO_CONTROL2_PDC_SCHMITT_S 0
-
-/* PU_PD field values */
-#define REG_PU_PD_TRISTATE 0
-#define REG_PU_PD_UP 1
-#define REG_PU_PD_DOWN 2
-#define REG_PU_PD_REPEATER 3
-
-/* DR field values */
-#define REG_DR_2mA 0
-#define REG_DR_4mA 1
-#define REG_DR_8mA 2
-#define REG_DR_12mA 3
-
-/**
- * struct tz1090_pdc_function - TZ1090 PDC pinctrl mux function
- * @name: The name of the function, exported to pinctrl core.
- * @groups: An array of pin groups that may select this function.
- * @ngroups: The number of entries in @groups.
- */
-struct tz1090_pdc_function {
- const char *name;
- const char * const *groups;
- unsigned int ngroups;
-};
-
-/**
- * struct tz1090_pdc_pingroup - TZ1090 PDC pin group
- * @name: Name of pin group.
- * @pins: Array of pin numbers in this pin group.
- * @npins: Number of pins in this pin group.
- * @func: Function enabled by the mux.
- * @reg: Mux register offset.
- * @bit: Mux register bit.
- * @drv: Drive control supported, otherwise it's a mux.
- * This means Schmitt, Slew, and Drive strength.
- *
- * A representation of a group of pins (possibly just one pin) in the TZ1090
- * PDC pin controller. Each group allows some parameter or parameters to be
- * configured. The most common is mux function selection.
- */
-struct tz1090_pdc_pingroup {
- const char *name;
- const unsigned int *pins;
- unsigned int npins;
- int func;
- u16 reg;
- u8 bit;
- bool drv;
-};
-
-/*
- * All PDC pins can be GPIOs. Define these first to match how the GPIO driver
- * names/numbers its pins.
- */
-
-enum tz1090_pdc_pin {
- TZ1090_PDC_PIN_GPIO0,
- TZ1090_PDC_PIN_GPIO1,
- TZ1090_PDC_PIN_SYS_WAKE0,
- TZ1090_PDC_PIN_SYS_WAKE1,
- TZ1090_PDC_PIN_SYS_WAKE2,
- TZ1090_PDC_PIN_IR_DATA,
- TZ1090_PDC_PIN_EXT_POWER,
-};
-
-/* Pin names */
-
-static const struct pinctrl_pin_desc tz1090_pdc_pins[] = {
- /* PDC GPIOs */
- PINCTRL_PIN(TZ1090_PDC_PIN_GPIO0, "gpio0"),
- PINCTRL_PIN(TZ1090_PDC_PIN_GPIO1, "gpio1"),
- PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE0, "sys_wake0"),
- PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE1, "sys_wake1"),
- PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE2, "sys_wake2"),
- PINCTRL_PIN(TZ1090_PDC_PIN_IR_DATA, "ir_data"),
- PINCTRL_PIN(TZ1090_PDC_PIN_EXT_POWER, "ext_power"),
-};
-
-/* Pin group pins */
-
-static const unsigned int gpio0_pins[] = {
- TZ1090_PDC_PIN_GPIO0,
-};
-
-static const unsigned int gpio1_pins[] = {
- TZ1090_PDC_PIN_GPIO1,
-};
-
-static const unsigned int pdc_pins[] = {
- TZ1090_PDC_PIN_GPIO0,
- TZ1090_PDC_PIN_GPIO1,
- TZ1090_PDC_PIN_SYS_WAKE0,
- TZ1090_PDC_PIN_SYS_WAKE1,
- TZ1090_PDC_PIN_SYS_WAKE2,
- TZ1090_PDC_PIN_IR_DATA,
- TZ1090_PDC_PIN_EXT_POWER,
-};
-
-/* Mux functions */
-
-enum tz1090_pdc_mux {
- /* PDC_GPIO0 mux */
- TZ1090_PDC_MUX_IR_MOD_STABLE_OUT,
- /* PDC_GPIO1 mux */
- TZ1090_PDC_MUX_IR_MOD_POWER_OUT,
-};
-
-/* Pin groups a function can be muxed to */
-
-static const char * const gpio0_groups[] = {
- "gpio0",
-};
-
-static const char * const gpio1_groups[] = {
- "gpio1",
-};
-
-#define FUNCTION(mux, fname, group) \
- [(TZ1090_PDC_MUX_ ## mux)] = { \
- .name = #fname, \
- .groups = group##_groups, \
- .ngroups = ARRAY_SIZE(group##_groups), \
- }
-
-/* Must correlate with enum tz1090_pdc_mux */
-static const struct tz1090_pdc_function tz1090_pdc_functions[] = {
- /* MUX fn pingroups */
- FUNCTION(IR_MOD_STABLE_OUT, ir_mod_stable_out, gpio0),
- FUNCTION(IR_MOD_POWER_OUT, ir_mod_power_out, gpio1),
-};
-
-/**
- * MUX_PG() - Initialise a pin group with mux control
- * @pg_name: Pin group name (stringified, _pins appended to get pins array)
- * @f0: Function 0 (TZ1090_PDC_MUX_ is prepended)
- * @mux_r: Mux register (REG_PINCTRL_ is prepended)
- * @mux_b: Bit number in register of mux field
- */
-#define MUX_PG(pg_name, f0, mux_r, mux_b) \
- { \
- .name = #pg_name, \
- .pins = pg_name##_pins, \
- .npins = ARRAY_SIZE(pg_name##_pins), \
- .func = TZ1090_PDC_MUX_ ## f0, \
- .reg = (REG_ ## mux_r), \
- .bit = (mux_b), \
- }
-
-/**
- * DRV_PG() - Initialise a pin group with drive control
- * @pg_name: Pin group name (stringified, _pins appended to get pins array)
- */
-#define DRV_PG(pg_name) \
- { \
- .name = #pg_name, \
- .pins = pg_name##_pins, \
- .npins = ARRAY_SIZE(pg_name##_pins), \
- .drv = true, \
- }
-
-static const struct tz1090_pdc_pingroup tz1090_pdc_groups[] = {
- /* Muxing pin groups */
- /* pg_name, f0, mux register, mux bit */
- MUX_PG(gpio0, IR_MOD_STABLE_OUT, GPIO_CONTROL0, 7),
- MUX_PG(gpio1, IR_MOD_POWER_OUT, GPIO_CONTROL0, 6),
-
- /* Drive pin groups */
- /* pg_name */
- DRV_PG(pdc),
-};
-
-/**
- * struct tz1090_pdc_pmx - Private pinctrl data
- * @dev: Platform device
- * @pctl: Pin control device
- * @regs: Register region
- * @lock: Lock protecting coherency of mux_en and gpio_en
- * @mux_en: Muxes that have been enabled
- * @gpio_en: Muxable GPIOs that have been enabled
- */
-struct tz1090_pdc_pmx {
- struct device *dev;
- struct pinctrl_dev *pctl;
- void __iomem *regs;
- spinlock_t lock;
- u32 mux_en;
- u32 gpio_en;
-};
-
-static inline u32 pmx_read(struct tz1090_pdc_pmx *pmx, u32 reg)
-{
- return ioread32(pmx->regs + reg);
-}
-
-static inline void pmx_write(struct tz1090_pdc_pmx *pmx, u32 val, u32 reg)
-{
- iowrite32(val, pmx->regs + reg);
-}
-
-/*
- * Pin control operations
- */
-
-static int tz1090_pdc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
-{
- return ARRAY_SIZE(tz1090_pdc_groups);
-}
-
-static const char *tz1090_pdc_pinctrl_get_group_name(struct pinctrl_dev *pctl,
- unsigned int group)
-{
- return tz1090_pdc_groups[group].name;
-}
-
-static int tz1090_pdc_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
- unsigned int group,
- const unsigned int **pins,
- unsigned int *num_pins)
-{
- *pins = tz1090_pdc_groups[group].pins;
- *num_pins = tz1090_pdc_groups[group].npins;
-
- return 0;
-}
-
-#ifdef CONFIG_DEBUG_FS
-static void tz1090_pdc_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
- struct seq_file *s,
- unsigned int offset)
-{
- seq_printf(s, " %s", dev_name(pctldev->dev));
-}
-#endif
-
-static int reserve_map(struct device *dev, struct pinctrl_map **map,
- unsigned int *reserved_maps, unsigned int *num_maps,
- unsigned int reserve)
-{
- unsigned int old_num = *reserved_maps;
- unsigned int new_num = *num_maps + reserve;
- struct pinctrl_map *new_map;
-
- if (old_num >= new_num)
- return 0;
-
- new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
- if (!new_map) {
- dev_err(dev, "krealloc(map) failed\n");
- return -ENOMEM;
- }
-
- memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
-
- *map = new_map;
- *reserved_maps = new_num;
-
- return 0;
-}
-
-static int add_map_mux(struct pinctrl_map **map, unsigned int *reserved_maps,
- unsigned int *num_maps, const char *group,
- const char *function)
-{
- if (WARN_ON(*num_maps == *reserved_maps))
- return -ENOSPC;
-
- (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
- (*map)[*num_maps].data.mux.group = group;
- (*map)[*num_maps].data.mux.function = function;
- (*num_maps)++;
-
- return 0;
-}
-
-/**
- * get_group_selector() - returns the group selector for a group
- * @pin_group: the pin group to look up
- *
- * This is the same as pinctrl_get_group_selector except it doesn't produce an
- * error message if the group isn't found or debug messages.
- */
-static int get_group_selector(const char *pin_group)
-{
- unsigned int group;
-
- for (group = 0; group < ARRAY_SIZE(tz1090_pdc_groups); ++group)
- if (!strcmp(tz1090_pdc_groups[group].name, pin_group))
- return group;
-
- return -EINVAL;
-}
-
-static int add_map_configs(struct device *dev,
- struct pinctrl_map **map,
- unsigned int *reserved_maps, unsigned int *num_maps,
- const char *group, unsigned long *configs,
- unsigned int num_configs)
-{
- unsigned long *dup_configs;
- enum pinctrl_map_type type;
-
- if (WARN_ON(*num_maps == *reserved_maps))
- return -ENOSPC;
-
- dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
- GFP_KERNEL);
- if (!dup_configs)
- return -ENOMEM;
-
- /*
- * We support both pins and pin groups, but we need to figure out which
- * one we have.
- */
- if (get_group_selector(group) >= 0)
- type = PIN_MAP_TYPE_CONFIGS_GROUP;
- else
- type = PIN_MAP_TYPE_CONFIGS_PIN;
- (*map)[*num_maps].type = type;
- (*map)[*num_maps].data.configs.group_or_pin = group;
- (*map)[*num_maps].data.configs.configs = dup_configs;
- (*map)[*num_maps].data.configs.num_configs = num_configs;
- (*num_maps)++;
-
- return 0;
-}
-
-static void tz1090_pdc_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
- struct pinctrl_map *map,
- unsigned int num_maps)
-{
- int i;
-
- for (i = 0; i < num_maps; i++)
- if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
- kfree(map[i].data.configs.configs);
-
- kfree(map);
-}
-
-static int tz1090_pdc_pinctrl_dt_subnode_to_map(struct device *dev,
- struct device_node *np,
- struct pinctrl_map **map,
- unsigned int *reserved_maps,
- unsigned int *num_maps)
-{
- int ret;
- const char *function;
- unsigned long *configs = NULL;
- unsigned int num_configs = 0;
- unsigned int reserve;
- struct property *prop;
- const char *group;
-
- ret = of_property_read_string(np, "tz1090,function", &function);
- if (ret < 0) {
- /* EINVAL=missing, which is fine since it's optional */
- if (ret != -EINVAL)
- dev_err(dev,
- "could not parse property function\n");
- function = NULL;
- }
-
- ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs);
- if (ret)
- return ret;
-
- reserve = 0;
- if (function != NULL)
- reserve++;
- if (num_configs)
- reserve++;
- ret = of_property_count_strings(np, "tz1090,pins");
- if (ret < 0) {
- dev_err(dev, "could not parse property pins\n");
- goto exit;
- }
- reserve *= ret;
-
- ret = reserve_map(dev, map, reserved_maps, num_maps, reserve);
- if (ret < 0)
- goto exit;
-
- of_property_for_each_string(np, "tz1090,pins", prop, group) {
- if (function) {
- ret = add_map_mux(map, reserved_maps, num_maps,
- group, function);
- if (ret < 0)
- goto exit;
- }
-
- if (num_configs) {
- ret = add_map_configs(dev, map, reserved_maps,
- num_maps, group, configs,
- num_configs);
- if (ret < 0)
- goto exit;
- }
- }
-
- ret = 0;
-
-exit:
- kfree(configs);
- return ret;
-}
-
-static int tz1090_pdc_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
- struct device_node *np_config,
- struct pinctrl_map **map,
- unsigned int *num_maps)
-{
- unsigned int reserved_maps;
- struct device_node *np;
- int ret;
-
- reserved_maps = 0;
- *map = NULL;
- *num_maps = 0;
-
- for_each_child_of_node(np_config, np) {
- ret = tz1090_pdc_pinctrl_dt_subnode_to_map(pctldev->dev, np,
- map, &reserved_maps,
- num_maps);
- if (ret < 0) {
- tz1090_pdc_pinctrl_dt_free_map(pctldev, *map,
- *num_maps);
- return ret;
- }
- }
-
- return 0;
-}
-
-static const struct pinctrl_ops tz1090_pdc_pinctrl_ops = {
- .get_groups_count = tz1090_pdc_pinctrl_get_groups_count,
- .get_group_name = tz1090_pdc_pinctrl_get_group_name,
- .get_group_pins = tz1090_pdc_pinctrl_get_group_pins,
-#ifdef CONFIG_DEBUG_FS
- .pin_dbg_show = tz1090_pdc_pinctrl_pin_dbg_show,
-#endif
- .dt_node_to_map = tz1090_pdc_pinctrl_dt_node_to_map,
- .dt_free_map = tz1090_pdc_pinctrl_dt_free_map,
-};
-
-/*
- * Pin mux operations
- */
-
-static int tz1090_pdc_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
-{
- return ARRAY_SIZE(tz1090_pdc_functions);
-}
-
-static const char *tz1090_pdc_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
- unsigned int function)
-{
- return tz1090_pdc_functions[function].name;
-}
-
-static int tz1090_pdc_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
- unsigned int function,
- const char * const **groups,
- unsigned int * const num_groups)
-{
- *groups = tz1090_pdc_functions[function].groups;
- *num_groups = tz1090_pdc_functions[function].ngroups;
-
- return 0;
-}
-
-/**
- * tz1090_pdc_pinctrl_mux() - update mux bit
- * @pmx: Pinmux data
- * @grp: Pin mux group
- */
-static void tz1090_pdc_pinctrl_mux(struct tz1090_pdc_pmx *pmx,
- const struct tz1090_pdc_pingroup *grp)
-{
- u32 reg, select;
- unsigned int pin_shift = grp->pins[0];
- unsigned long flags;
-
- /* select = mux && !gpio */
- select = ((pmx->mux_en & ~pmx->gpio_en) >> pin_shift) & 1;
-
- /* set up the mux */
- __global_lock2(flags);
- reg = pmx_read(pmx, grp->reg);
- reg &= ~BIT(grp->bit);
- reg |= select << grp->bit;
- pmx_write(pmx, reg, grp->reg);
- __global_unlock2(flags);
-}
-
-static int tz1090_pdc_pinctrl_set_mux(struct pinctrl_dev *pctldev,
- unsigned int function,
- unsigned int group)
-{
- struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
- const struct tz1090_pdc_pingroup *grp = &tz1090_pdc_groups[group];
-
- dev_dbg(pctldev->dev, "%s(func=%u (%s), group=%u (%s))\n",
- __func__,
- function, tz1090_pdc_functions[function].name,
- group, tz1090_pdc_groups[group].name);
-
- /* is it even a mux? */
- if (grp->drv)
- return -EINVAL;
-
- /* does this group even control the function? */
- if (function != grp->func)
- return -EINVAL;
-
- /* record the pin being muxed and update mux bit */
- spin_lock(&pmx->lock);
- pmx->mux_en |= BIT(grp->pins[0]);
- tz1090_pdc_pinctrl_mux(pmx, grp);
- spin_unlock(&pmx->lock);
- return 0;
-}
-
-static const struct tz1090_pdc_pingroup *find_mux_group(
- struct tz1090_pdc_pmx *pmx,
- unsigned int pin)
-{
- const struct tz1090_pdc_pingroup *grp;
- unsigned int group;
-
- grp = tz1090_pdc_groups;
- for (group = 0; group < ARRAY_SIZE(tz1090_pdc_groups); ++group, ++grp) {
- /* only match muxes */
- if (grp->drv)
- continue;
-
- /* with a matching pin */
- if (grp->pins[0] == pin)
- return grp;
- }
-
- return NULL;
-}
-
-static int tz1090_pdc_pinctrl_gpio_request_enable(
- struct pinctrl_dev *pctldev,
- struct pinctrl_gpio_range *range,
- unsigned int pin)
-{
- struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
- const struct tz1090_pdc_pingroup *grp = find_mux_group(pmx, pin);
-
- if (grp) {
- /* record the pin in GPIO use and update mux bit */
- spin_lock(&pmx->lock);
- pmx->gpio_en |= BIT(pin);
- tz1090_pdc_pinctrl_mux(pmx, grp);
- spin_unlock(&pmx->lock);
- }
- return 0;
-}
-
-static void tz1090_pdc_pinctrl_gpio_disable_free(
- struct pinctrl_dev *pctldev,
- struct pinctrl_gpio_range *range,
- unsigned int pin)
-{
- struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
- const struct tz1090_pdc_pingroup *grp = find_mux_group(pmx, pin);
-
- if (grp) {
- /* record the pin not in GPIO use and update mux bit */
- spin_lock(&pmx->lock);
- pmx->gpio_en &= ~BIT(pin);
- tz1090_pdc_pinctrl_mux(pmx, grp);
- spin_unlock(&pmx->lock);
- }
-}
-
-static const struct pinmux_ops tz1090_pdc_pinmux_ops = {
- .get_functions_count = tz1090_pdc_pinctrl_get_funcs_count,
- .get_function_name = tz1090_pdc_pinctrl_get_func_name,
- .get_function_groups = tz1090_pdc_pinctrl_get_func_groups,
- .set_mux = tz1090_pdc_pinctrl_set_mux,
- .gpio_request_enable = tz1090_pdc_pinctrl_gpio_request_enable,
- .gpio_disable_free = tz1090_pdc_pinctrl_gpio_disable_free,
-};
-
-/*
- * Pin config operations
- */
-
-static int tz1090_pdc_pinconf_reg(struct pinctrl_dev *pctldev,
- unsigned int pin,
- enum pin_config_param param,
- bool report_err,
- u32 *reg, u32 *width, u32 *mask, u32 *shift,
- u32 *val)
-{
- /* Find information about parameter's register */
- switch (param) {
- case PIN_CONFIG_BIAS_DISABLE:
- case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
- *val = REG_PU_PD_TRISTATE;
- break;
- case PIN_CONFIG_BIAS_PULL_UP:
- *val = REG_PU_PD_UP;
- break;
- case PIN_CONFIG_BIAS_PULL_DOWN:
- *val = REG_PU_PD_DOWN;
- break;
- case PIN_CONFIG_BIAS_BUS_HOLD:
- *val = REG_PU_PD_REPEATER;
- break;
- default:
- return -ENOTSUPP;
- }
-
- /* Only input bias parameters supported */
- *reg = REG_GPIO_CONTROL2;
- *shift = REG_GPIO_CONTROL2_PU_PD_S + pin*2;
- *width = 2;
-
- /* Calculate field information */
- *mask = (BIT(*width) - 1) << *shift;
-
- return 0;
-}
-
-static int tz1090_pdc_pinconf_get(struct pinctrl_dev *pctldev,
- unsigned int pin, unsigned long *config)
-{
- struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
- enum pin_config_param param = pinconf_to_config_param(*config);
- int ret;
- u32 reg, width, mask, shift, val, tmp, arg;
-
- /* Get register information */
- ret = tz1090_pdc_pinconf_reg(pctldev, pin, param, true,
- &reg, &width, &mask, &shift, &val);
- if (ret < 0)
- return ret;
-
- /* Extract field from register */
- tmp = pmx_read(pmx, reg);
- arg = ((tmp & mask) >> shift) == val;
-
- /* Config not active */
- if (!arg)
- return -EINVAL;
-
- /* And pack config */
- *config = pinconf_to_config_packed(param, arg);
-
- return 0;
-}
-
-static int tz1090_pdc_pinconf_set(struct pinctrl_dev *pctldev,
- unsigned int pin, unsigned long *configs,
- unsigned num_configs)
-{
- struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
- enum pin_config_param param;
- unsigned int arg;
- int ret;
- u32 reg, width, mask, shift, val, tmp;
- unsigned long flags;
- int i;
-
- for (i = 0; i < num_configs; i++) {
- param = pinconf_to_config_param(configs[i]);
- arg = pinconf_to_config_argument(configs[i]);
-
- dev_dbg(pctldev->dev, "%s(pin=%s, config=%#lx)\n",
- __func__, tz1090_pdc_pins[pin].name, configs[i]);
-
- /* Get register information */
- ret = tz1090_pdc_pinconf_reg(pctldev, pin, param, true,
- &reg, &width, &mask, &shift, &val);
- if (ret < 0)
- return ret;
-
- /* Unpack argument and range check it */
- if (arg > 1) {
- dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
- __func__, arg);
- return -EINVAL;
- }
-
- /* Write register field */
- __global_lock2(flags);
- tmp = pmx_read(pmx, reg);
- tmp &= ~mask;
- if (arg)
- tmp |= val << shift;
- pmx_write(pmx, tmp, reg);
- __global_unlock2(flags);
- } /* for each config */
-
- return 0;
-}
-
-static const int tz1090_pdc_boolean_map[] = {
- [0] = -EINVAL,
- [1] = 1,
-};
-
-static const int tz1090_pdc_dr_map[] = {
- [REG_DR_2mA] = 2,
- [REG_DR_4mA] = 4,
- [REG_DR_8mA] = 8,
- [REG_DR_12mA] = 12,
-};
-
-static int tz1090_pdc_pinconf_group_reg(struct pinctrl_dev *pctldev,
- const struct tz1090_pdc_pingroup *g,
- enum pin_config_param param,
- bool report_err, u32 *reg, u32 *width,
- u32 *mask, u32 *shift, const int **map)
-{
- /* Drive configuration applies in groups, but not to all groups. */
- if (!g->drv) {
- if (report_err)
- dev_dbg(pctldev->dev,
- "%s: group %s has no drive control\n",
- __func__, g->name);
- return -ENOTSUPP;
- }
-
- /* Find information about drive parameter's register */
- *reg = REG_GPIO_CONTROL2;
- switch (param) {
- case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
- *shift = REG_GPIO_CONTROL2_PDC_SCHMITT_S;
- *width = 1;
- *map = tz1090_pdc_boolean_map;
- break;
- case PIN_CONFIG_DRIVE_STRENGTH:
- *shift = REG_GPIO_CONTROL2_PDC_DR_S;
- *width = 2;
- *map = tz1090_pdc_dr_map;
- break;
- case PIN_CONFIG_LOW_POWER_MODE:
- *shift = REG_GPIO_CONTROL2_PDC_POS_S;
- *width = 1;
- *map = tz1090_pdc_boolean_map;
- break;
- default:
- return -ENOTSUPP;
- }
-
- /* Calculate field information */
- *mask = (BIT(*width) - 1) << *shift;
-
- return 0;
-}
-
-static int tz1090_pdc_pinconf_group_get(struct pinctrl_dev *pctldev,
- unsigned int group,
- unsigned long *config)
-{
- struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
- const struct tz1090_pdc_pingroup *g = &tz1090_pdc_groups[group];
- enum pin_config_param param = pinconf_to_config_param(*config);
- int ret, arg;
- u32 reg, width, mask, shift, val;
- const int *map;
-
- /* Get register information */
- ret = tz1090_pdc_pinconf_group_reg(pctldev, g, param, true,
- &reg, &width, &mask, &shift, &map);
- if (ret < 0)
- return ret;
-
- /* Extract field from register */
- val = pmx_read(pmx, reg);
- arg = map[(val & mask) >> shift];
- if (arg < 0)
- return arg;
-
- /* And pack config */
- *config = pinconf_to_config_packed(param, arg);
-
- return 0;
-}
-
-static int tz1090_pdc_pinconf_group_set(struct pinctrl_dev *pctldev,
- unsigned int group,
- unsigned long *configs,
- unsigned num_configs)
-{
- struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
- const struct tz1090_pdc_pingroup *g = &tz1090_pdc_groups[group];
- enum pin_config_param param;
- const unsigned int *pit;
- unsigned int i;
- int ret, arg;
- u32 reg, width, mask, shift, val;
- unsigned long flags;
- const int *map;
- int j;
-
- for (j = 0; j < num_configs; j++) {
- param = pinconf_to_config_param(configs[j]);
-
- dev_dbg(pctldev->dev, "%s(group=%s, config=%#lx)\n",
- __func__, g->name, configs[j]);
-
- /* Get register information */
- ret = tz1090_pdc_pinconf_group_reg(pctldev, g, param, true,
- &reg, &width, &mask, &shift,
- &map);
- if (ret < 0) {
- /*
- * Maybe we're trying to set a per-pin configuration
- * of a group, so do the pins one by one. This is
- * mainly as a convenience.
- */
- for (i = 0, pit = g->pins; i < g->npins; ++i, ++pit) {
- ret = tz1090_pdc_pinconf_set(pctldev, *pit,
- configs, num_configs);
- if (ret)
- return ret;
- }
- return 0;
- }
-
- /* Unpack argument and map it to register value */
- arg = pinconf_to_config_argument(configs[j]);
- for (i = 0; i < BIT(width); ++i) {
- if (map[i] == arg || (map[i] == -EINVAL && !arg)) {
- /* Write register field */
- __global_lock2(flags);
- val = pmx_read(pmx, reg);
- val &= ~mask;
- val |= i << shift;
- pmx_write(pmx, val, reg);
- __global_unlock2(flags);
- goto next_config;
- }
- }
-
- dev_dbg(pctldev->dev, "%s: arg %u not supported\n",
- __func__, arg);
- return 0;
-
-next_config:
- ;
- } /* for each config */
-
- return 0;
-}
-
-static const struct pinconf_ops tz1090_pdc_pinconf_ops = {
- .is_generic = true,
- .pin_config_get = tz1090_pdc_pinconf_get,
- .pin_config_set = tz1090_pdc_pinconf_set,
- .pin_config_group_get = tz1090_pdc_pinconf_group_get,
- .pin_config_group_set = tz1090_pdc_pinconf_group_set,
- .pin_config_config_dbg_show = pinconf_generic_dump_config,
-};
-
-/*
- * Pin control driver setup
- */
-
-static struct pinctrl_desc tz1090_pdc_pinctrl_desc = {
- .pctlops = &tz1090_pdc_pinctrl_ops,
- .pmxops = &tz1090_pdc_pinmux_ops,
- .confops = &tz1090_pdc_pinconf_ops,
- .owner = THIS_MODULE,
-};
-
-static int tz1090_pdc_pinctrl_probe(struct platform_device *pdev)
-{
- struct tz1090_pdc_pmx *pmx;
- struct resource *res;
-
- pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
- if (!pmx)
- return -ENOMEM;
-
- pmx->dev = &pdev->dev;
- spin_lock_init(&pmx->lock);
-
- tz1090_pdc_pinctrl_desc.name = dev_name(&pdev->dev);
- tz1090_pdc_pinctrl_desc.pins = tz1090_pdc_pins;
- tz1090_pdc_pinctrl_desc.npins = ARRAY_SIZE(tz1090_pdc_pins);
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- pmx->regs = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(pmx->regs))
- return PTR_ERR(pmx->regs);
-
- pmx->pctl = devm_pinctrl_register(&pdev->dev, &tz1090_pdc_pinctrl_desc,
- pmx);
- if (IS_ERR(pmx->pctl)) {
- dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
- return PTR_ERR(pmx->pctl);
- }
-
- platform_set_drvdata(pdev, pmx);
-
- dev_info(&pdev->dev, "TZ1090 PDC pinctrl driver initialised\n");
-
- return 0;
-}
-
-static const struct of_device_id tz1090_pdc_pinctrl_of_match[] = {
- { .compatible = "img,tz1090-pdc-pinctrl", },
- { },
-};
-
-static struct platform_driver tz1090_pdc_pinctrl_driver = {
- .driver = {
- .name = "tz1090-pdc-pinctrl",
- .of_match_table = tz1090_pdc_pinctrl_of_match,
- },
- .probe = tz1090_pdc_pinctrl_probe,
-};
-
-static int __init tz1090_pdc_pinctrl_init(void)
-{
- return platform_driver_register(&tz1090_pdc_pinctrl_driver);
-}
-arch_initcall(tz1090_pdc_pinctrl_init);
-
-static void __exit tz1090_pdc_pinctrl_exit(void)
-{
- platform_driver_unregister(&tz1090_pdc_pinctrl_driver);
-}
-module_exit(tz1090_pdc_pinctrl_exit);
-
-MODULE_AUTHOR("Imagination Technologies Ltd.");
-MODULE_DESCRIPTION("Toumaz Xenif TZ1090 PDC pinctrl driver");
-MODULE_LICENSE("GPL v2");
-MODULE_DEVICE_TABLE(of, tz1090_pdc_pinctrl_of_match);
diff --git a/drivers/pinctrl/pinctrl-tz1090.c b/drivers/pinctrl/pinctrl-tz1090.c
deleted file mode 100644
index 2379ce2be365..000000000000
--- a/drivers/pinctrl/pinctrl-tz1090.c
+++ /dev/null
@@ -1,2005 +0,0 @@
-/*
- * Pinctrl driver for the Toumaz Xenif TZ1090 SoC
- *
- * Copyright (c) 2013, Imagination Technologies Ltd.
- *
- * Derived from Tegra code:
- * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
- *
- * Derived from code:
- * Copyright (C) 2010 Google, Inc.
- * Copyright (C) 2010 NVIDIA Corporation
- * Copyright (C) 2009-2011 ST-Ericsson AB
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/bitops.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
-
-/*
- * The registers may be shared with other threads/cores, so we need to use the
- * metag global lock2 for atomicity.
- */
-#include <asm/global_lock.h>
-
-#include "core.h"
-#include "pinconf.h"
-
-/* Register offsets from bank base address */
-#define REG_PINCTRL_SELECT 0x10
-#define REG_PINCTRL_SCHMITT 0x90
-#define REG_PINCTRL_PU_PD 0xa0
-#define REG_PINCTRL_SR 0xc0
-#define REG_PINCTRL_DR 0xd0
-#define REG_PINCTRL_IF_CTL 0xe0
-
-/* REG_PINCTRL_PU_PD field values */
-#define REG_PU_PD_TRISTATE 0
-#define REG_PU_PD_UP 1
-#define REG_PU_PD_DOWN 2
-#define REG_PU_PD_REPEATER 3
-
-/* REG_PINCTRL_DR field values */
-#define REG_DR_2mA 0
-#define REG_DR_4mA 1
-#define REG_DR_8mA 2
-#define REG_DR_12mA 3
-
-/**
- * struct tz1090_function - TZ1090 pinctrl mux function
- * @name: The name of the function, exported to pinctrl core.
- * @groups: An array of pin groups that may select this function.
- * @ngroups: The number of entries in @groups.
- */
-struct tz1090_function {
- const char *name;
- const char * const *groups;
- unsigned int ngroups;
-};
-
-/**
- * struct tz1090_muxdesc - TZ1090 individual mux description
- * @funcs: Function for each mux value.
- * @reg: Mux register offset. 0 if unsupported.
- * @bit: Mux register bit. 0 if unsupported.
- * @width: Mux field width. 0 if unsupported.
- *
- * A representation of a group of signals (possibly just one signal) in the
- * TZ1090 which can be muxed to a set of functions or sub muxes.
- */
-struct tz1090_muxdesc {
- int funcs[5];
- u16 reg;
- u8 bit;
- u8 width;
-};
-
-/**
- * struct tz1090_pingroup - TZ1090 pin group
- * @name: Name of pin group.
- * @pins: Array of pin numbers in this pin group.
- * @npins: Number of pins in this pin group.
- * @mux: Top level mux.
- * @drv: Drive control supported, 0 if unsupported.
- * This means Schmitt, Slew, and Drive strength.
- * @slw_bit: Slew register bit. 0 if unsupported.
- * The same bit is used for Schmitt, and Drive (*2).
- * @func: Currently muxed function.
- * @func_count: Number of pins using current mux function.
- *
- * A representation of a group of pins (possibly just one pin) in the TZ1090
- * pin controller. Each group allows some parameter or parameters to be
- * configured. The most common is mux function selection.
- */
-struct tz1090_pingroup {
- const char *name;
- const unsigned int *pins;
- unsigned int npins;
- struct tz1090_muxdesc mux;
-
- bool drv;
- u8 slw_bit;
-
- int func;
- unsigned int func_count;
-};
-
-/*
- * Most pins affected by the pinmux can also be GPIOs. Define these first.
- * These must match how the GPIO driver names/numbers its pins.
- */
-
-enum tz1090_pin {
- /* GPIO pins */
- TZ1090_PIN_SDIO_CLK,
- TZ1090_PIN_SDIO_CMD,
- TZ1090_PIN_SDIO_D0,
- TZ1090_PIN_SDIO_D1,
- TZ1090_PIN_SDIO_D2,
- TZ1090_PIN_SDIO_D3,
- TZ1090_PIN_SDH_CD,
- TZ1090_PIN_SDH_WP,
- TZ1090_PIN_SPI0_MCLK,
- TZ1090_PIN_SPI0_CS0,
- TZ1090_PIN_SPI0_CS1,
- TZ1090_PIN_SPI0_CS2,
- TZ1090_PIN_SPI0_DOUT,
- TZ1090_PIN_SPI0_DIN,
- TZ1090_PIN_SPI1_MCLK,
- TZ1090_PIN_SPI1_CS0,
- TZ1090_PIN_SPI1_CS1,
- TZ1090_PIN_SPI1_CS2,
- TZ1090_PIN_SPI1_DOUT,
- TZ1090_PIN_SPI1_DIN,
- TZ1090_PIN_UART0_RXD,
- TZ1090_PIN_UART0_TXD,
- TZ1090_PIN_UART0_CTS,
- TZ1090_PIN_UART0_RTS,
- TZ1090_PIN_UART1_RXD,
- TZ1090_PIN_UART1_TXD,
- TZ1090_PIN_SCB0_SDAT,
- TZ1090_PIN_SCB0_SCLK,
- TZ1090_PIN_SCB1_SDAT,
- TZ1090_PIN_SCB1_SCLK,
- TZ1090_PIN_SCB2_SDAT,
- TZ1090_PIN_SCB2_SCLK,
- TZ1090_PIN_I2S_MCLK,
- TZ1090_PIN_I2S_BCLK_OUT,
- TZ1090_PIN_I2S_LRCLK_OUT,
- TZ1090_PIN_I2S_DOUT0,
- TZ1090_PIN_I2S_DOUT1,
- TZ1090_PIN_I2S_DOUT2,
- TZ1090_PIN_I2S_DIN,
- TZ1090_PIN_PDM_A,
- TZ1090_PIN_PDM_B,
- TZ1090_PIN_PDM_C,
- TZ1090_PIN_PDM_D,
- TZ1090_PIN_TFT_RED0,
- TZ1090_PIN_TFT_RED1,
- TZ1090_PIN_TFT_RED2,
- TZ1090_PIN_TFT_RED3,
- TZ1090_PIN_TFT_RED4,
- TZ1090_PIN_TFT_RED5,
- TZ1090_PIN_TFT_RED6,
- TZ1090_PIN_TFT_RED7,
- TZ1090_PIN_TFT_GREEN0,
- TZ1090_PIN_TFT_GREEN1,
- TZ1090_PIN_TFT_GREEN2,
- TZ1090_PIN_TFT_GREEN3,
- TZ1090_PIN_TFT_GREEN4,
- TZ1090_PIN_TFT_GREEN5,
- TZ1090_PIN_TFT_GREEN6,
- TZ1090_PIN_TFT_GREEN7,
- TZ1090_PIN_TFT_BLUE0,
- TZ1090_PIN_TFT_BLUE1,
- TZ1090_PIN_TFT_BLUE2,
- TZ1090_PIN_TFT_BLUE3,
- TZ1090_PIN_TFT_BLUE4,
- TZ1090_PIN_TFT_BLUE5,
- TZ1090_PIN_TFT_BLUE6,
- TZ1090_PIN_TFT_BLUE7,
- TZ1090_PIN_TFT_VDDEN_GD,
- TZ1090_PIN_TFT_PANELCLK,
- TZ1090_PIN_TFT_BLANK_LS,
- TZ1090_PIN_TFT_VSYNC_NS,
- TZ1090_PIN_TFT_HSYNC_NR,
- TZ1090_PIN_TFT_VD12ACB,
- TZ1090_PIN_TFT_PWRSAVE,
- TZ1090_PIN_TX_ON,
- TZ1090_PIN_RX_ON,
- TZ1090_PIN_PLL_ON,
- TZ1090_PIN_PA_ON,
- TZ1090_PIN_RX_HP,
- TZ1090_PIN_GAIN0,
- TZ1090_PIN_GAIN1,
- TZ1090_PIN_GAIN2,
- TZ1090_PIN_GAIN3,
- TZ1090_PIN_GAIN4,
- TZ1090_PIN_GAIN5,
- TZ1090_PIN_GAIN6,
- TZ1090_PIN_GAIN7,
- TZ1090_PIN_ANT_SEL0,
- TZ1090_PIN_ANT_SEL1,
- TZ1090_PIN_SDH_CLK_IN,
-
- /* Non-GPIO pins */
- TZ1090_PIN_TCK,
- TZ1090_PIN_TRST,
- TZ1090_PIN_TDI,
- TZ1090_PIN_TDO,
- TZ1090_PIN_TMS,
- TZ1090_PIN_CLK_OUT0,
- TZ1090_PIN_CLK_OUT1,
-
- NUM_GPIOS = TZ1090_PIN_TCK,
-};
-
-/* Pin names */
-
-static const struct pinctrl_pin_desc tz1090_pins[] = {
- /* GPIO pins */
- PINCTRL_PIN(TZ1090_PIN_SDIO_CLK, "sdio_clk"),
- PINCTRL_PIN(TZ1090_PIN_SDIO_CMD, "sdio_cmd"),
- PINCTRL_PIN(TZ1090_PIN_SDIO_D0, "sdio_d0"),
- PINCTRL_PIN(TZ1090_PIN_SDIO_D1, "sdio_d1"),
- PINCTRL_PIN(TZ1090_PIN_SDIO_D2, "sdio_d2"),
- PINCTRL_PIN(TZ1090_PIN_SDIO_D3, "sdio_d3"),
- PINCTRL_PIN(TZ1090_PIN_SDH_CD, "sdh_cd"),
- PINCTRL_PIN(TZ1090_PIN_SDH_WP, "sdh_wp"),
- PINCTRL_PIN(TZ1090_PIN_SPI0_MCLK, "spi0_mclk"),
- PINCTRL_PIN(TZ1090_PIN_SPI0_CS0, "spi0_cs0"),
- PINCTRL_PIN(TZ1090_PIN_SPI0_CS1, "spi0_cs1"),
- PINCTRL_PIN(TZ1090_PIN_SPI0_CS2, "spi0_cs2"),
- PINCTRL_PIN(TZ1090_PIN_SPI0_DOUT, "spi0_dout"),
- PINCTRL_PIN(TZ1090_PIN_SPI0_DIN, "spi0_din"),
- PINCTRL_PIN(TZ1090_PIN_SPI1_MCLK, "spi1_mclk"),
- PINCTRL_PIN(TZ1090_PIN_SPI1_CS0, "spi1_cs0"),
- PINCTRL_PIN(TZ1090_PIN_SPI1_CS1, "spi1_cs1"),
- PINCTRL_PIN(TZ1090_PIN_SPI1_CS2, "spi1_cs2"),
- PINCTRL_PIN(TZ1090_PIN_SPI1_DOUT, "spi1_dout"),
- PINCTRL_PIN(TZ1090_PIN_SPI1_DIN, "spi1_din"),
- PINCTRL_PIN(TZ1090_PIN_UART0_RXD, "uart0_rxd"),
- PINCTRL_PIN(TZ1090_PIN_UART0_TXD, "uart0_txd"),
- PINCTRL_PIN(TZ1090_PIN_UART0_CTS, "uart0_cts"),
- PINCTRL_PIN(TZ1090_PIN_UART0_RTS, "uart0_rts"),
- PINCTRL_PIN(TZ1090_PIN_UART1_RXD, "uart1_rxd"),
- PINCTRL_PIN(TZ1090_PIN_UART1_TXD, "uart1_txd"),
- PINCTRL_PIN(TZ1090_PIN_SCB0_SDAT, "scb0_sdat"),
- PINCTRL_PIN(TZ1090_PIN_SCB0_SCLK, "scb0_sclk"),
- PINCTRL_PIN(TZ1090_PIN_SCB1_SDAT, "scb1_sdat"),
- PINCTRL_PIN(TZ1090_PIN_SCB1_SCLK, "scb1_sclk"),
- PINCTRL_PIN(TZ1090_PIN_SCB2_SDAT, "scb2_sdat"),
- PINCTRL_PIN(TZ1090_PIN_SCB2_SCLK, "scb2_sclk"),
- PINCTRL_PIN(TZ1090_PIN_I2S_MCLK, "i2s_mclk"),
- PINCTRL_PIN(TZ1090_PIN_I2S_BCLK_OUT, "i2s_bclk_out"),
- PINCTRL_PIN(TZ1090_PIN_I2S_LRCLK_OUT, "i2s_lrclk_out"),
- PINCTRL_PIN(TZ1090_PIN_I2S_DOUT0, "i2s_dout0"),
- PINCTRL_PIN(TZ1090_PIN_I2S_DOUT1, "i2s_dout1"),
- PINCTRL_PIN(TZ1090_PIN_I2S_DOUT2, "i2s_dout2"),
- PINCTRL_PIN(TZ1090_PIN_I2S_DIN, "i2s_din"),
- PINCTRL_PIN(TZ1090_PIN_PDM_A, "pdm_a"),
- PINCTRL_PIN(TZ1090_PIN_PDM_B, "pdm_b"),
- PINCTRL_PIN(TZ1090_PIN_PDM_C, "pdm_c"),
- PINCTRL_PIN(TZ1090_PIN_PDM_D, "pdm_d"),
- PINCTRL_PIN(TZ1090_PIN_TFT_RED0, "tft_red0"),
- PINCTRL_PIN(TZ1090_PIN_TFT_RED1, "tft_red1"),
- PINCTRL_PIN(TZ1090_PIN_TFT_RED2, "tft_red2"),
- PINCTRL_PIN(TZ1090_PIN_TFT_RED3, "tft_red3"),
- PINCTRL_PIN(TZ1090_PIN_TFT_RED4, "tft_red4"),
- PINCTRL_PIN(TZ1090_PIN_TFT_RED5, "tft_red5"),
- PINCTRL_PIN(TZ1090_PIN_TFT_RED6, "tft_red6"),
- PINCTRL_PIN(TZ1090_PIN_TFT_RED7, "tft_red7"),
- PINCTRL_PIN(TZ1090_PIN_TFT_GREEN0, "tft_green0"),
- PINCTRL_PIN(TZ1090_PIN_TFT_GREEN1, "tft_green1"),
- PINCTRL_PIN(TZ1090_PIN_TFT_GREEN2, "tft_green2"),
- PINCTRL_PIN(TZ1090_PIN_TFT_GREEN3, "tft_green3"),
- PINCTRL_PIN(TZ1090_PIN_TFT_GREEN4, "tft_green4"),
- PINCTRL_PIN(TZ1090_PIN_TFT_GREEN5, "tft_green5"),
- PINCTRL_PIN(TZ1090_PIN_TFT_GREEN6, "tft_green6"),
- PINCTRL_PIN(TZ1090_PIN_TFT_GREEN7, "tft_green7"),
- PINCTRL_PIN(TZ1090_PIN_TFT_BLUE0, "tft_blue0"),
- PINCTRL_PIN(TZ1090_PIN_TFT_BLUE1, "tft_blue1"),
- PINCTRL_PIN(TZ1090_PIN_TFT_BLUE2, "tft_blue2"),
- PINCTRL_PIN(TZ1090_PIN_TFT_BLUE3, "tft_blue3"),
- PINCTRL_PIN(TZ1090_PIN_TFT_BLUE4, "tft_blue4"),
- PINCTRL_PIN(TZ1090_PIN_TFT_BLUE5, "tft_blue5"),
- PINCTRL_PIN(TZ1090_PIN_TFT_BLUE6, "tft_blue6"),
- PINCTRL_PIN(TZ1090_PIN_TFT_BLUE7, "tft_blue7"),
- PINCTRL_PIN(TZ1090_PIN_TFT_VDDEN_GD, "tft_vdden_gd"),
- PINCTRL_PIN(TZ1090_PIN_TFT_PANELCLK, "tft_panelclk"),
- PINCTRL_PIN(TZ1090_PIN_TFT_BLANK_LS, "tft_blank_ls"),
- PINCTRL_PIN(TZ1090_PIN_TFT_VSYNC_NS, "tft_vsync_ns"),
- PINCTRL_PIN(TZ1090_PIN_TFT_HSYNC_NR, "tft_hsync_nr"),
- PINCTRL_PIN(TZ1090_PIN_TFT_VD12ACB, "tft_vd12acb"),
- PINCTRL_PIN(TZ1090_PIN_TFT_PWRSAVE, "tft_pwrsave"),
- PINCTRL_PIN(TZ1090_PIN_TX_ON, "tx_on"),
- PINCTRL_PIN(TZ1090_PIN_RX_ON, "rx_on"),
- PINCTRL_PIN(TZ1090_PIN_PLL_ON, "pll_on"),
- PINCTRL_PIN(TZ1090_PIN_PA_ON, "pa_on"),
- PINCTRL_PIN(TZ1090_PIN_RX_HP, "rx_hp"),
- PINCTRL_PIN(TZ1090_PIN_GAIN0, "gain0"),
- PINCTRL_PIN(TZ1090_PIN_GAIN1, "gain1"),
- PINCTRL_PIN(TZ1090_PIN_GAIN2, "gain2"),
- PINCTRL_PIN(TZ1090_PIN_GAIN3, "gain3"),
- PINCTRL_PIN(TZ1090_PIN_GAIN4, "gain4"),
- PINCTRL_PIN(TZ1090_PIN_GAIN5, "gain5"),
- PINCTRL_PIN(TZ1090_PIN_GAIN6, "gain6"),
- PINCTRL_PIN(TZ1090_PIN_GAIN7, "gain7"),
- PINCTRL_PIN(TZ1090_PIN_ANT_SEL0, "ant_sel0"),
- PINCTRL_PIN(TZ1090_PIN_ANT_SEL1, "ant_sel1"),
- PINCTRL_PIN(TZ1090_PIN_SDH_CLK_IN, "sdh_clk_in"),
-
- /* Non-GPIO pins */
- PINCTRL_PIN(TZ1090_PIN_TCK, "tck"),
- PINCTRL_PIN(TZ1090_PIN_TRST, "trst"),
- PINCTRL_PIN(TZ1090_PIN_TDI, "tdi"),
- PINCTRL_PIN(TZ1090_PIN_TDO, "tdo"),
- PINCTRL_PIN(TZ1090_PIN_TMS, "tms"),
- PINCTRL_PIN(TZ1090_PIN_CLK_OUT0, "clk_out0"),
- PINCTRL_PIN(TZ1090_PIN_CLK_OUT1, "clk_out1"),
-};
-
-/* Pins in each pin group */
-
-static const unsigned int spi1_cs2_pins[] = {
- TZ1090_PIN_SPI1_CS2,
-};
-
-static const unsigned int pdm_d_pins[] = {
- TZ1090_PIN_PDM_D,
-};
-
-static const unsigned int tft_pins[] = {
- TZ1090_PIN_TFT_RED0,
- TZ1090_PIN_TFT_RED1,
- TZ1090_PIN_TFT_RED2,
- TZ1090_PIN_TFT_RED3,
- TZ1090_PIN_TFT_RED4,
- TZ1090_PIN_TFT_RED5,
- TZ1090_PIN_TFT_RED6,
- TZ1090_PIN_TFT_RED7,
- TZ1090_PIN_TFT_GREEN0,
- TZ1090_PIN_TFT_GREEN1,
- TZ1090_PIN_TFT_GREEN2,
- TZ1090_PIN_TFT_GREEN3,
- TZ1090_PIN_TFT_GREEN4,
- TZ1090_PIN_TFT_GREEN5,
- TZ1090_PIN_TFT_GREEN6,
- TZ1090_PIN_TFT_GREEN7,
- TZ1090_PIN_TFT_BLUE0,
- TZ1090_PIN_TFT_BLUE1,
- TZ1090_PIN_TFT_BLUE2,
- TZ1090_PIN_TFT_BLUE3,
- TZ1090_PIN_TFT_BLUE4,
- TZ1090_PIN_TFT_BLUE5,
- TZ1090_PIN_TFT_BLUE6,
- TZ1090_PIN_TFT_BLUE7,
- TZ1090_PIN_TFT_VDDEN_GD,
- TZ1090_PIN_TFT_PANELCLK,
- TZ1090_PIN_TFT_BLANK_LS,
- TZ1090_PIN_TFT_VSYNC_NS,
- TZ1090_PIN_TFT_HSYNC_NR,
- TZ1090_PIN_TFT_VD12ACB,
- TZ1090_PIN_TFT_PWRSAVE,
-};
-
-static const unsigned int afe_pins[] = {
- TZ1090_PIN_TX_ON,
- TZ1090_PIN_RX_ON,
- TZ1090_PIN_PLL_ON,
- TZ1090_PIN_PA_ON,
- TZ1090_PIN_RX_HP,
- TZ1090_PIN_ANT_SEL0,
- TZ1090_PIN_ANT_SEL1,
- TZ1090_PIN_GAIN0,
- TZ1090_PIN_GAIN1,
- TZ1090_PIN_GAIN2,
- TZ1090_PIN_GAIN3,
- TZ1090_PIN_GAIN4,
- TZ1090_PIN_GAIN5,
- TZ1090_PIN_GAIN6,
- TZ1090_PIN_GAIN7,
-};
-
-static const unsigned int sdio_pins[] = {
- TZ1090_PIN_SDIO_CLK,
- TZ1090_PIN_SDIO_CMD,
- TZ1090_PIN_SDIO_D0,
- TZ1090_PIN_SDIO_D1,
- TZ1090_PIN_SDIO_D2,
- TZ1090_PIN_SDIO_D3,
-};
-
-static const unsigned int sdh_pins[] = {
- TZ1090_PIN_SDH_CD,
- TZ1090_PIN_SDH_WP,
- TZ1090_PIN_SDH_CLK_IN,
-};
-
-static const unsigned int spi0_pins[] = {
- TZ1090_PIN_SPI0_MCLK,
- TZ1090_PIN_SPI0_CS0,
- TZ1090_PIN_SPI0_CS1,
- TZ1090_PIN_SPI0_CS2,
- TZ1090_PIN_SPI0_DOUT,
- TZ1090_PIN_SPI0_DIN,
-};
-
-static const unsigned int spi1_pins[] = {
- TZ1090_PIN_SPI1_MCLK,
- TZ1090_PIN_SPI1_CS0,
- TZ1090_PIN_SPI1_CS1,
- TZ1090_PIN_SPI1_CS2,
- TZ1090_PIN_SPI1_DOUT,
- TZ1090_PIN_SPI1_DIN,
-};
-
-static const unsigned int uart0_pins[] = {
- TZ1090_PIN_UART0_RTS,
- TZ1090_PIN_UART0_CTS,
- TZ1090_PIN_UART0_TXD,
- TZ1090_PIN_UART0_RXD,
-};
-
-static const unsigned int uart1_pins[] = {
- TZ1090_PIN_UART1_TXD,
- TZ1090_PIN_UART1_RXD,
-};
-
-static const unsigned int uart_pins[] = {
- TZ1090_PIN_UART1_TXD,
- TZ1090_PIN_UART1_RXD,
- TZ1090_PIN_UART0_RTS,
- TZ1090_PIN_UART0_CTS,
- TZ1090_PIN_UART0_TXD,
- TZ1090_PIN_UART0_RXD,
-};
-
-static const unsigned int scb0_pins[] = {
- TZ1090_PIN_SCB0_SDAT,
- TZ1090_PIN_SCB0_SCLK,
-};
-
-static const unsigned int scb1_pins[] = {
- TZ1090_PIN_SCB1_SDAT,
- TZ1090_PIN_SCB1_SCLK,
-};
-
-static const unsigned int scb2_pins[] = {
- TZ1090_PIN_SCB2_SDAT,
- TZ1090_PIN_SCB2_SCLK,
-};
-
-static const unsigned int i2s_pins[] = {
- TZ1090_PIN_I2S_MCLK,
- TZ1090_PIN_I2S_BCLK_OUT,
- TZ1090_PIN_I2S_LRCLK_OUT,
- TZ1090_PIN_I2S_DOUT0,
- TZ1090_PIN_I2S_DOUT1,
- TZ1090_PIN_I2S_DOUT2,
- TZ1090_PIN_I2S_DIN,
-};
-
-static const unsigned int jtag_pins[] = {
- TZ1090_PIN_TCK,
- TZ1090_PIN_TRST,
- TZ1090_PIN_TDI,
- TZ1090_PIN_TDO,
- TZ1090_PIN_TMS,
-};
-
-/* Pins in each drive pin group */
-
-static const unsigned int drive_sdio_pins[] = {
- TZ1090_PIN_SDIO_CLK,
- TZ1090_PIN_SDIO_CMD,
- TZ1090_PIN_SDIO_D0,
- TZ1090_PIN_SDIO_D1,
- TZ1090_PIN_SDIO_D2,
- TZ1090_PIN_SDIO_D3,
- TZ1090_PIN_SDH_WP,
- TZ1090_PIN_SDH_CD,
- TZ1090_PIN_SDH_CLK_IN,
-};
-
-static const unsigned int drive_i2s_pins[] = {
- TZ1090_PIN_CLK_OUT1,
- TZ1090_PIN_I2S_DIN,
- TZ1090_PIN_I2S_DOUT0,
- TZ1090_PIN_I2S_DOUT1,
- TZ1090_PIN_I2S_DOUT2,
- TZ1090_PIN_I2S_LRCLK_OUT,
- TZ1090_PIN_I2S_BCLK_OUT,
- TZ1090_PIN_I2S_MCLK,
-};
-
-static const unsigned int drive_scb0_pins[] = {
- TZ1090_PIN_SCB0_SCLK,
- TZ1090_PIN_SCB0_SDAT,
- TZ1090_PIN_PDM_D,
- TZ1090_PIN_PDM_C,
-};
-
-static const unsigned int drive_pdm_pins[] = {
- TZ1090_PIN_CLK_OUT0,
- TZ1090_PIN_PDM_B,
- TZ1090_PIN_PDM_A,
-};
-
-/* Pin groups each function can be muxed to */
-
-/*
- * The magic "perip" function allows otherwise non-muxing pins to be enabled in
- * peripheral mode.
- */
-static const char * const perip_groups[] = {
- /* non-muxing convenient gpio pingroups */
- "uart",
- "uart0",
- "uart1",
- "spi0",
- "spi1",
- "scb0",
- "scb1",
- "scb2",
- "i2s",
- /* individual pins not part of a pin mux group */
- "spi0_mclk",
- "spi0_cs0",
- "spi0_cs1",
- "spi0_cs2",
- "spi0_dout",
- "spi0_din",
- "spi1_mclk",
- "spi1_cs0",
- "spi1_cs1",
- "spi1_dout",
- "spi1_din",
- "uart0_rxd",
- "uart0_txd",
- "uart0_cts",
- "uart0_rts",
- "uart1_rxd",
- "uart1_txd",
- "scb0_sdat",
- "scb0_sclk",
- "scb1_sdat",
- "scb1_sclk",
- "scb2_sdat",
- "scb2_sclk",
- "i2s_mclk",
- "i2s_bclk_out",
- "i2s_lrclk_out",
- "i2s_dout0",
- "i2s_dout1",
- "i2s_dout2",
- "i2s_din",
- "pdm_a",
- "pdm_b",
- "pdm_c",
-};
-
-static const char * const sdh_sdio_groups[] = {
- "sdh",
- "sdio",
- /* sdh pins */
- "sdh_cd",
- "sdh_wp",
- "sdh_clk_in",
- /* sdio pins */
- "sdio_clk",
- "sdio_cmd",
- "sdio_d0",
- "sdio_d1",
- "sdio_d2",
- "sdio_d3",
-};
-
-static const char * const spi1_cs2_groups[] = {
- "spi1_cs2",
-};
-
-static const char * const pdm_dac_groups[] = {
- "pdm_d",
-};
-
-static const char * const usb_vbus_groups[] = {
- "spi1_cs2",
- "pdm_d",
-};
-
-static const char * const afe_groups[] = {
- "afe",
- /* afe pins */
- "tx_on",
- "rx_on",
- "pll_on",
- "pa_on",
- "rx_hp",
- "ant_sel0",
- "ant_sel1",
- "gain0",
- "gain1",
- "gain2",
- "gain3",
- "gain4",
- "gain5",
- "gain6",
- "gain7",
-};
-
-static const char * const tft_groups[] = {
- "tft",
- /* tft pins */
- "tft_red0",
- "tft_red1",
- "tft_red2",
- "tft_red3",
- "tft_red4",
- "tft_red5",
- "tft_red6",
- "tft_red7",
- "tft_green0",
- "tft_green1",
- "tft_green2",
- "tft_green3",
- "tft_green4",
- "tft_green5",
- "tft_green6",
- "tft_green7",
- "tft_blue0",
- "tft_blue1",
- "tft_blue2",
- "tft_blue3",
- "tft_blue4",
- "tft_blue5",
- "tft_blue6",
- "tft_blue7",
- "tft_vdden_gd",
- "tft_panelclk",
- "tft_blank_ls",
- "tft_vsync_ns",
- "tft_hsync_nr",
- "tft_vd12acb",
- "tft_pwrsave",
-};
-
-/* Mux functions that can be used by a mux */
-
-enum tz1090_mux {
- /* internal placeholder */
- TZ1090_MUX_NA = -1,
- /* magic per-non-muxing-GPIO-pin peripheral mode mux */
- TZ1090_MUX_PERIP,
- /* SDH/SDIO mux */
- TZ1090_MUX_SDH,
- TZ1090_MUX_SDIO,
- /* USB_VBUS muxes */
- TZ1090_MUX_SPI1_CS2,
- TZ1090_MUX_PDM_DAC,
- TZ1090_MUX_USB_VBUS,
- /* AFE mux */
- TZ1090_MUX_AFE,
- TZ1090_MUX_TS_OUT_0,
- /* EXT_DAC mux */
- TZ1090_MUX_DAC,
- TZ1090_MUX_NOT_IQADC_STB,
- TZ1090_MUX_IQDAC_STB,
- /* TFT mux */
- TZ1090_MUX_TFT,
- TZ1090_MUX_EXT_DAC,
- TZ1090_MUX_TS_OUT_1,
- TZ1090_MUX_LCD_TRACE,
- TZ1090_MUX_PHY_RINGOSC,
-};
-
-#define FUNCTION(mux, fname, group) \
- [(TZ1090_MUX_ ## mux)] = { \
- .name = #fname, \
- .groups = group##_groups, \
- .ngroups = ARRAY_SIZE(group##_groups), \
- }
-/* For intermediate functions with submuxes */
-#define NULL_FUNCTION(mux, fname) \
- [(TZ1090_MUX_ ## mux)] = { \
- .name = #fname, \
- }
-
-/* Must correlate with enum tz1090_mux */
-static const struct tz1090_function tz1090_functions[] = {
- /* FUNCTION function name pingroups */
- FUNCTION(PERIP, perip, perip),
- FUNCTION(SDH, sdh, sdh_sdio),
- FUNCTION(SDIO, sdio, sdh_sdio),
- FUNCTION(SPI1_CS2, spi1_cs2, spi1_cs2),
- FUNCTION(PDM_DAC, pdm_dac, pdm_dac),
- FUNCTION(USB_VBUS, usb_vbus, usb_vbus),
- FUNCTION(AFE, afe, afe),
- FUNCTION(TS_OUT_0, ts_out_0, afe),
- FUNCTION(DAC, ext_dac, tft),
- FUNCTION(NOT_IQADC_STB, not_iqadc_stb, tft),
- FUNCTION(IQDAC_STB, iqdac_stb, tft),
- FUNCTION(TFT, tft, tft),
- NULL_FUNCTION(EXT_DAC, _ext_dac),
- FUNCTION(TS_OUT_1, ts_out_1, tft),
- FUNCTION(LCD_TRACE, lcd_trace, tft),
- FUNCTION(PHY_RINGOSC, phy_ringosc, tft),
-};
-
-/* Sub muxes */
-
-/**
- * MUX() - Initialise a mux description.
- * @f0: Function 0 (TZ1090_MUX_ is prepended, NA for none)
- * @f1: Function 1 (TZ1090_MUX_ is prepended, NA for none)
- * @f2: Function 2 (TZ1090_MUX_ is prepended, NA for none)
- * @f3: Function 3 (TZ1090_MUX_ is prepended, NA for none)
- * @f4: Function 4 (TZ1090_MUX_ is prepended, NA for none)
- * @mux_r: Mux register (REG_PINCTRL_ is prepended)
- * @mux_b: Bit number in register that the mux field begins
- * @mux_w: Width of mux field in register
- */
-#define MUX(f0, f1, f2, f3, f4, mux_r, mux_b, mux_w) \
- { \
- .funcs = { \
- TZ1090_MUX_ ## f0, \
- TZ1090_MUX_ ## f1, \
- TZ1090_MUX_ ## f2, \
- TZ1090_MUX_ ## f3, \
- TZ1090_MUX_ ## f4, \
- }, \
- .reg = (REG_PINCTRL_ ## mux_r), \
- .bit = (mux_b), \
- .width = (mux_w), \
- }
-
-/**
- * DEFINE_SUBMUX() - Defines a submux description separate from a pin group.
- * @mux: Mux name (_submux is appended)
- * @f0: Function 0 (TZ1090_MUX_ is prepended, NA for none)
- * @f1: Function 1 (TZ1090_MUX_ is prepended, NA for none)
- * @f2: Function 2 (TZ1090_MUX_ is prepended, NA for none)
- * @f3: Function 3 (TZ1090_MUX_ is prepended, NA for none)
- * @f4: Function 4 (TZ1090_MUX_ is prepended, NA for none)
- * @mux_r: Mux register (REG_PINCTRL_ is prepended)
- * @mux_b: Bit number in register that the mux field begins
- * @mux_w: Width of mux field in register
- *
- * A sub mux is a nested mux that can be bound to a magic function number used
- * by another mux description. For example value 4 of the top level mux might
- * correspond to a function which has a submux pointed to in tz1090_submux[].
- * The outer mux can then take on any function in the top level mux or the
- * submux, and if a submux function is chosen both muxes are updated to route
- * the signal from the submux.
- *
- * The submux can be defined with DEFINE_SUBMUX and pointed to from
- * tz1090_submux[] using SUBMUX.
- */
-#define DEFINE_SUBMUX(mux, f0, f1, f2, f3, f4, mux_r, mux_b, mux_w) \
- static struct tz1090_muxdesc mux ## _submux = \
- MUX(f0, f1, f2, f3, f4, mux_r, mux_b, mux_w)
-
-/**
- * SUBMUX() - Link a submux to a function number.
- * @f: Function name (TZ1090_MUX_ is prepended)
- * @submux: Submux name (_submux is appended)
- *
- * For use in tz1090_submux[] initialisation to link an intermediate function
- * number to a particular submux description. It indicates that when the
- * function is chosen the signal is connected to the submux.
- */
-#define SUBMUX(f, submux) [(TZ1090_MUX_ ## f)] = &(submux ## _submux)
-
-/**
- * MUX_PG() - Initialise a pin group with mux control
- * @pg_name: Pin group name (stringified, _pins appended to get pins array)
- * @f0: Function 0 (TZ1090_MUX_ is prepended, NA for none)
- * @f1: Function 1 (TZ1090_MUX_ is prepended, NA for none)
- * @f2: Function 2 (TZ1090_MUX_ is prepended, NA for none)
- * @f3: Function 3 (TZ1090_MUX_ is prepended, NA for none)
- * @f4: Function 4 (TZ1090_MUX_ is prepended, NA for none)
- * @mux_r: Mux register (REG_PINCTRL_ is prepended)
- * @mux_b: Bit number in register that the mux field begins
- * @mux_w: Width of mux field in register
- */
-#define MUX_PG(pg_name, f0, f1, f2, f3, f4, \
- mux_r, mux_b, mux_w) \
- { \
- .name = #pg_name, \
- .pins = pg_name##_pins, \
- .npins = ARRAY_SIZE(pg_name##_pins), \
- .mux = MUX(f0, f1, f2, f3, f4, \
- mux_r, mux_b, mux_w), \
- }
-
-/**
- * SIMPLE_PG() - Initialise a simple convenience pin group
- * @pg_name: Pin group name (stringified, _pins appended to get pins array)
- *
- * A simple pin group is simply used for binding pins together so they can be
- * referred to by a single name instead of having to list every pin
- * individually.
- */
-#define SIMPLE_PG(pg_name) \
- { \
- .name = #pg_name, \
- .pins = pg_name##_pins, \
- .npins = ARRAY_SIZE(pg_name##_pins), \
- }
-
-/**
- * DRV_PG() - Initialise a pin group with drive control
- * @pg_name: Pin group name (stringified, _pins appended to get pins array)
- * @slw_b: Slew register bit.
- * The same bit is used for Schmitt, and Drive (*2).
- */
-#define DRV_PG(pg_name, slw_b) \
- { \
- .name = #pg_name, \
- .pins = pg_name##_pins, \
- .npins = ARRAY_SIZE(pg_name##_pins), \
- .drv = true, \
- .slw_bit = (slw_b), \
- }
-
-/*
- * Define main muxing pin groups
- */
-
-/* submuxes */
-
-/* name f0, f1, f2, f3, f4, mux r/b/w */
-DEFINE_SUBMUX(ext_dac, DAC, NOT_IQADC_STB, IQDAC_STB, NA, NA, IF_CTL, 6, 2);
-
-/* bind submuxes to internal functions */
-static struct tz1090_muxdesc *tz1090_submux[] = {
- SUBMUX(EXT_DAC, ext_dac),
-};
-
-/*
- * These are the pin mux groups. Pin muxing can be enabled and disabled for each
- * pin individually so these groups are internal. The mapping of pins to pin mux
- * group is below (tz1090_mux_pins).
- */
-static struct tz1090_pingroup tz1090_mux_groups[] = {
- /* Muxing pin groups */
- /* pg_name, f0, f1, f2, f3, f4, mux r/b/w */
- MUX_PG(sdh, SDH, SDIO, NA, NA, NA, IF_CTL, 20, 2),
- MUX_PG(sdio, SDIO, SDH, NA, NA, NA, IF_CTL, 16, 2),
- MUX_PG(spi1_cs2, SPI1_CS2, USB_VBUS, NA, NA, NA, IF_CTL, 10, 2),
- MUX_PG(pdm_d, PDM_DAC, USB_VBUS, NA, NA, NA, IF_CTL, 8, 2),
- MUX_PG(afe, AFE, TS_OUT_0, NA, NA, NA, IF_CTL, 4, 2),
- MUX_PG(tft, TFT, EXT_DAC, TS_OUT_1, LCD_TRACE, PHY_RINGOSC, IF_CTL, 0, 3),
-};
-
-/*
- * This is the mapping from GPIO pins to pin mux groups in tz1090_mux_groups[].
- * Pins which aren't muxable to multiple peripherals are set to
- * TZ1090_MUX_GROUP_MAX to enable the "perip" function to enable/disable
- * peripheral control of the pin.
- *
- * This array is initialised in tz1090_init_mux_pins().
- */
-static u8 tz1090_mux_pins[NUM_GPIOS];
-
-/* TZ1090_MUX_GROUP_MAX is used in tz1090_mux_pins[] for non-muxing pins */
-#define TZ1090_MUX_GROUP_MAX ARRAY_SIZE(tz1090_mux_groups)
-
-/**
- * tz1090_init_mux_pins() - Initialise GPIO pin to mux group mapping.
- *
- * Initialises the tz1090_mux_pins[] array to be the inverse of the pin lists in
- * each pin mux group in tz1090_mux_groups[].
- *
- * It is assumed that no pin mux groups overlap (share pins).
- */
-static void __init tz1090_init_mux_pins(void)
-{
- unsigned int g, p;
- const struct tz1090_pingroup *grp;
- const unsigned int *pin;
-
- for (p = 0; p < NUM_GPIOS; ++p)
- tz1090_mux_pins[p] = TZ1090_MUX_GROUP_MAX;
-
- grp = tz1090_mux_groups;
- for (g = 0, grp = tz1090_mux_groups;
- g < ARRAY_SIZE(tz1090_mux_groups); ++g, ++grp)
- for (pin = grp->pins, p = 0; p < grp->npins; ++p, ++pin)
- tz1090_mux_pins[*pin] = g;
-}
-
-/*
- * These are the externally visible pin groups. Some of them allow group control
- * of drive configuration. Some are just simple convenience pingroups. All the
- * internal pin mux groups in tz1090_mux_groups[] are mirrored here with the
- * same pins.
- * Pseudo pin groups follow in the group numbers after this array for each GPIO
- * pin. Any group used for muxing must have all pins belonging to the same pin
- * mux group.
- */
-static struct tz1090_pingroup tz1090_groups[] = {
- /* Pin groups with drive control (with no out of place pins) */
- /* pg_name, slw/schmitt/drv b */
- DRV_PG(jtag, 11 /* 11, 22 */),
- DRV_PG(tft, 10 /* 10, 20 */),
- DRV_PG(scb2, 9 /* 9, 18 */),
- DRV_PG(spi0, 7 /* 7, 14 */),
- DRV_PG(uart, 5 /* 5, 10 */),
- DRV_PG(scb1, 4 /* 4, 8 */),
- DRV_PG(spi1, 3 /* 3, 6 */),
- DRV_PG(afe, 0 /* 0, 0 */),
-
- /*
- * Drive specific pin groups (with odd combinations of pins which makes
- * the pin group naming somewhat arbitrary)
- */
- /* pg_name, slw/schmitt/drv b */
- DRV_PG(drive_sdio, 8 /* 8, 16 */), /* sdio_* + sdh_* */
- DRV_PG(drive_i2s, 6 /* 6, 12 */), /* i2s_* + clk_out1 */
- DRV_PG(drive_scb0, 2 /* 2, 4 */), /* scb0_* + pdm_{c,d} */
- DRV_PG(drive_pdm, 1 /* 1, 2 */), /* pdm_{a,b} + clk_out0 */
-
- /* Convenience pin groups */
- /* pg_name */
- SIMPLE_PG(uart0),
- SIMPLE_PG(uart1),
- SIMPLE_PG(scb0),
- SIMPLE_PG(i2s),
- SIMPLE_PG(sdh),
- SIMPLE_PG(sdio),
-
- /* pseudo-pingroups for each GPIO pin follow */
-};
-
-/**
- * struct tz1090_pmx - Private pinctrl data
- * @dev: Platform device
- * @pctl: Pin control device
- * @regs: Register region
- * @lock: Lock protecting coherency of pin_en, gpio_en, and SELECT regs
- * @pin_en: Pins that have been enabled (32 pins packed into each element)
- * @gpio_en: GPIOs that have been enabled (32 pins packed into each element)
- */
-struct tz1090_pmx {
- struct device *dev;
- struct pinctrl_dev *pctl;
- void __iomem *regs;
- spinlock_t lock;
- u32 pin_en[3];
- u32 gpio_en[3];
-};
-
-static inline u32 pmx_read(struct tz1090_pmx *pmx, u32 reg)
-{
- return ioread32(pmx->regs + reg);
-}
-
-static inline void pmx_write(struct tz1090_pmx *pmx, u32 val, u32 reg)
-{
- iowrite32(val, pmx->regs + reg);
-}
-
-/*
- * Pin control operations
- */
-
-/* each GPIO pin has it's own pseudo pingroup containing only itself */
-
-static int tz1090_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
-{
- return ARRAY_SIZE(tz1090_groups) + NUM_GPIOS;
-}
-
-static const char *tz1090_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
- unsigned int group)
-{
- if (group < ARRAY_SIZE(tz1090_groups)) {
- /* normal pingroup */
- return tz1090_groups[group].name;
- } else {
- /* individual gpio pin pseudo-pingroup */
- unsigned int pin = group - ARRAY_SIZE(tz1090_groups);
- return tz1090_pins[pin].name;
- }
-}
-
-static int tz1090_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
- unsigned int group,
- const unsigned int **pins,
- unsigned int *num_pins)
-{
- if (group < ARRAY_SIZE(tz1090_groups)) {
- /* normal pingroup */
- *pins = tz1090_groups[group].pins;
- *num_pins = tz1090_groups[group].npins;
- } else {
- /* individual gpio pin pseudo-pingroup */
- unsigned int pin = group - ARRAY_SIZE(tz1090_groups);
- *pins = &tz1090_pins[pin].number;
- *num_pins = 1;
- }
-
- return 0;
-}
-
-#ifdef CONFIG_DEBUG_FS
-static void tz1090_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
- struct seq_file *s,
- unsigned int offset)
-{
- seq_printf(s, " %s", dev_name(pctldev->dev));
-}
-#endif
-
-static int reserve_map(struct device *dev, struct pinctrl_map **map,
- unsigned int *reserved_maps, unsigned int *num_maps,
- unsigned int reserve)
-{
- unsigned int old_num = *reserved_maps;
- unsigned int new_num = *num_maps + reserve;
- struct pinctrl_map *new_map;
-
- if (old_num >= new_num)
- return 0;
-
- new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
- if (!new_map) {
- dev_err(dev, "krealloc(map) failed\n");
- return -ENOMEM;
- }
-
- memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
-
- *map = new_map;
- *reserved_maps = new_num;
-
- return 0;
-}
-
-static int add_map_mux(struct pinctrl_map **map, unsigned int *reserved_maps,
- unsigned int *num_maps, const char *group,
- const char *function)
-{
- if (WARN_ON(*num_maps == *reserved_maps))
- return -ENOSPC;
-
- (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
- (*map)[*num_maps].data.mux.group = group;
- (*map)[*num_maps].data.mux.function = function;
- (*num_maps)++;
-
- return 0;
-}
-
-static int add_map_configs(struct device *dev,
- struct pinctrl_map **map,
- unsigned int *reserved_maps, unsigned int *num_maps,
- const char *group, unsigned long *configs,
- unsigned int num_configs)
-{
- unsigned long *dup_configs;
-
- if (WARN_ON(*num_maps == *reserved_maps))
- return -ENOSPC;
-
- dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
- GFP_KERNEL);
- if (!dup_configs)
- return -ENOMEM;
-
- (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
- (*map)[*num_maps].data.configs.group_or_pin = group;
- (*map)[*num_maps].data.configs.configs = dup_configs;
- (*map)[*num_maps].data.configs.num_configs = num_configs;
- (*num_maps)++;
-
- return 0;
-}
-
-static void tz1090_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
- struct pinctrl_map *map,
- unsigned int num_maps)
-{
- int i;
-
- for (i = 0; i < num_maps; i++)
- if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
- kfree(map[i].data.configs.configs);
-
- kfree(map);
-}
-
-static int tz1090_pinctrl_dt_subnode_to_map(struct device *dev,
- struct device_node *np,
- struct pinctrl_map **map,
- unsigned int *reserved_maps,
- unsigned int *num_maps)
-{
- int ret;
- const char *function;
- unsigned long *configs = NULL;
- unsigned int num_configs = 0;
- unsigned int reserve;
- struct property *prop;
- const char *group;
-
- ret = of_property_read_string(np, "tz1090,function", &function);
- if (ret < 0) {
- /* EINVAL=missing, which is fine since it's optional */
- if (ret != -EINVAL)
- dev_err(dev, "could not parse property function\n");
- function = NULL;
- }
-
- ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs);
- if (ret)
- return ret;
-
- reserve = 0;
- if (function != NULL)
- reserve++;
- if (num_configs)
- reserve++;
- ret = of_property_count_strings(np, "tz1090,pins");
- if (ret < 0) {
- dev_err(dev, "could not parse property pins\n");
- goto exit;
- }
- reserve *= ret;
-
- ret = reserve_map(dev, map, reserved_maps, num_maps, reserve);
- if (ret < 0)
- goto exit;
-
- of_property_for_each_string(np, "tz1090,pins", prop, group) {
- if (function) {
- ret = add_map_mux(map, reserved_maps, num_maps,
- group, function);
- if (ret < 0)
- goto exit;
- }
-
- if (num_configs) {
- ret = add_map_configs(dev, map, reserved_maps,
- num_maps, group, configs,
- num_configs);
- if (ret < 0)
- goto exit;
- }
- }
-
- ret = 0;
-
-exit:
- kfree(configs);
- return ret;
-}
-
-static int tz1090_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
- struct device_node *np_config,
- struct pinctrl_map **map,
- unsigned int *num_maps)
-{
- unsigned int reserved_maps;
- struct device_node *np;
- int ret;
-
- reserved_maps = 0;
- *map = NULL;
- *num_maps = 0;
-
- for_each_child_of_node(np_config, np) {
- ret = tz1090_pinctrl_dt_subnode_to_map(pctldev->dev, np, map,
- &reserved_maps,
- num_maps);
- if (ret < 0) {
- tz1090_pinctrl_dt_free_map(pctldev, *map, *num_maps);
- return ret;
- }
- }
-
- return 0;
-}
-
-static const struct pinctrl_ops tz1090_pinctrl_ops = {
- .get_groups_count = tz1090_pinctrl_get_groups_count,
- .get_group_name = tz1090_pinctrl_get_group_name,
- .get_group_pins = tz1090_pinctrl_get_group_pins,
-#ifdef CONFIG_DEBUG_FS
- .pin_dbg_show = tz1090_pinctrl_pin_dbg_show,
-#endif
- .dt_node_to_map = tz1090_pinctrl_dt_node_to_map,
- .dt_free_map = tz1090_pinctrl_dt_free_map,
-};
-
-/*
- * Pin mux operations
- */
-
-static int tz1090_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
-{
- return ARRAY_SIZE(tz1090_functions);
-}
-
-static const char *tz1090_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
- unsigned int function)
-{
- return tz1090_functions[function].name;
-}
-
-static int tz1090_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
- unsigned int function,
- const char * const **groups,
- unsigned int * const num_groups)
-{
- /* pingroup functions */
- *groups = tz1090_functions[function].groups;
- *num_groups = tz1090_functions[function].ngroups;
- return 0;
-}
-
-/**
- * tz1090_pinctrl_select() - update bit in SELECT register
- * @pmx: Pinmux data
- * @pin: Pin number (must be within GPIO range)
- */
-static void tz1090_pinctrl_select(struct tz1090_pmx *pmx,
- unsigned int pin)
-{
- u32 reg, reg_shift, select, val;
- unsigned int pmx_index, pmx_shift;
- unsigned long flags;
-
- /* uses base 32 instead of base 30 */
- pmx_index = pin >> 5;
- pmx_shift = pin & 0x1f;
-
- /* select = !perip || gpio */
- select = ((~pmx->pin_en[pmx_index] |
- pmx->gpio_en[pmx_index]) >> pmx_shift) & 1;
-
- /* find register and bit offset (base 30) */
- reg = REG_PINCTRL_SELECT + 4*(pin / 30);
- reg_shift = pin % 30;
-
- /* modify gpio select bit */
- __global_lock2(flags);
- val = pmx_read(pmx, reg);
- val &= ~BIT(reg_shift);
- val |= select << reg_shift;
- pmx_write(pmx, val, reg);
- __global_unlock2(flags);
-}
-
-/**
- * tz1090_pinctrl_gpio_select() - enable/disable GPIO usage for a pin
- * @pmx: Pinmux data
- * @pin: Pin number
- * @gpio_select: true to enable pin as GPIO,
- * false to leave control to whatever function is enabled
- *
- * Records that GPIO usage is enabled/disabled so that enabling a function
- * doesn't override the SELECT register bit.
- */
-static void tz1090_pinctrl_gpio_select(struct tz1090_pmx *pmx,
- unsigned int pin,
- bool gpio_select)
-{
- unsigned int index, shift;
- u32 gpio_en;
-
- if (pin >= NUM_GPIOS)
- return;
-
- /* uses base 32 instead of base 30 */
- index = pin >> 5;
- shift = pin & 0x1f;
-
- spin_lock(&pmx->lock);
-
- /* keep a record whether gpio is selected */
- gpio_en = pmx->gpio_en[index];
- gpio_en &= ~BIT(shift);
- if (gpio_select)
- gpio_en |= BIT(shift);
- pmx->gpio_en[index] = gpio_en;
-
- /* update the select bit */
- tz1090_pinctrl_select(pmx, pin);
-
- spin_unlock(&pmx->lock);
-}
-
-/**
- * tz1090_pinctrl_perip_select() - enable/disable peripheral interface for a pin
- * @pmx: Pinmux data
- * @pin: Pin number
- * @perip_select: true to enable peripheral interface when not GPIO,
- * false to leave pin in GPIO mode
- *
- * Records that peripheral usage is enabled/disabled so that SELECT register can
- * be set appropriately when GPIO is disabled.
- */
-static void tz1090_pinctrl_perip_select(struct tz1090_pmx *pmx,
- unsigned int pin,
- bool perip_select)
-{
- unsigned int index, shift;
- u32 pin_en;
-
- if (pin >= NUM_GPIOS)
- return;
-
- /* uses base 32 instead of base 30 */
- index = pin >> 5;
- shift = pin & 0x1f;
-
- spin_lock(&pmx->lock);
-
- /* keep a record whether peripheral is selected */
- pin_en = pmx->pin_en[index];
- pin_en &= ~BIT(shift);
- if (perip_select)
- pin_en |= BIT(shift);
- pmx->pin_en[index] = pin_en;
-
- /* update the select bit */
- tz1090_pinctrl_select(pmx, pin);
-
- spin_unlock(&pmx->lock);
-}
-
-/**
- * tz1090_pinctrl_enable_mux() - Switch a pin mux group to a function.
- * @pmx: Pinmux data
- * @desc: Pinmux description
- * @function: Function to switch to
- *
- * Enable a particular function on a pin mux group. Since pin mux descriptions
- * are nested this function is recursive.
- */
-static int tz1090_pinctrl_enable_mux(struct tz1090_pmx *pmx,
- const struct tz1090_muxdesc *desc,
- unsigned int function)
-{
- const int *fit;
- unsigned long flags;
- int mux;
- unsigned int func, ret;
- u32 reg, mask;
-
- /* find the mux value for this function, searching recursively */
- for (mux = 0, fit = desc->funcs;
- mux < ARRAY_SIZE(desc->funcs); ++mux, ++fit) {
- func = *fit;
- if (func == function)
- goto found_mux;
-
- /* maybe it's a sub-mux */
- if (func < ARRAY_SIZE(tz1090_submux) && tz1090_submux[func]) {
- ret = tz1090_pinctrl_enable_mux(pmx,
- tz1090_submux[func],
- function);
- if (!ret)
- goto found_mux;
- }
- }
-
- return -EINVAL;
-found_mux:
-
- /* Set up the mux */
- if (desc->width) {
- mask = (BIT(desc->width) - 1) << desc->bit;
- __global_lock2(flags);
- reg = pmx_read(pmx, desc->reg);
- reg &= ~mask;
- reg |= (mux << desc->bit) & mask;
- pmx_write(pmx, reg, desc->reg);
- __global_unlock2(flags);
- }
-
- return 0;
-}
-
-/**
- * tz1090_pinctrl_enable() - Enable a function on a pin group.
- * @pctldev: Pin control data
- * @function: Function index to enable
- * @group: Group index to enable
- *
- * Enable a particular function on a group of pins. The per GPIO pin pseudo pin
- * groups can be used (in which case the pin will be enabled in peripheral mode
- * and if it belongs to a pin mux group the mux will be switched if it isn't
- * already in use. Some convenience pin groups can also be used in which case
- * the effect is the same as enabling the function on each individual pin in the
- * group.
- */
-static int tz1090_pinctrl_set_mux(struct pinctrl_dev *pctldev,
- unsigned int function, unsigned int group)
-{
- struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
- struct tz1090_pingroup *grp;
- int ret;
- unsigned int pin_num, mux_group, i, npins;
- const unsigned int *pins;
-
- /* group of pins? */
- if (group < ARRAY_SIZE(tz1090_groups)) {
- grp = &tz1090_groups[group];
- npins = grp->npins;
- pins = grp->pins;
- /*
- * All pins in the group must belong to the same mux group,
- * which allows us to just use the mux group of the first pin.
- * By explicitly listing permitted pingroups for each function
- * the pinmux core should ensure this is always the case.
- */
- } else {
- pin_num = group - ARRAY_SIZE(tz1090_groups);
- npins = 1;
- pins = &pin_num;
- }
- mux_group = tz1090_mux_pins[*pins];
-
- /* no mux group, but can still be individually muxed to peripheral */
- if (mux_group >= TZ1090_MUX_GROUP_MAX) {
- if (function == TZ1090_MUX_PERIP)
- goto mux_pins;
- return -EINVAL;
- }
-
- /* mux group already set to a different function? */
- grp = &tz1090_mux_groups[mux_group];
- if (grp->func_count && grp->func != function) {
- dev_err(pctldev->dev,
- "%s: can't mux pin(s) to '%s', group already muxed to '%s'\n",
- __func__, tz1090_functions[function].name,
- tz1090_functions[grp->func].name);
- return -EBUSY;
- }
-
- dev_dbg(pctldev->dev, "%s: muxing %u pin(s) in '%s' to '%s'\n",
- __func__, npins, grp->name, tz1090_functions[function].name);
-
- /* if first pin in mux group to be enabled, enable the group mux */
- if (!grp->func_count) {
- grp->func = function;
- ret = tz1090_pinctrl_enable_mux(pmx, &grp->mux, function);
- if (ret)
- return ret;
- }
- /* add pins to ref count and mux individually to peripheral */
- grp->func_count += npins;
-mux_pins:
- for (i = 0; i < npins; ++i)
- tz1090_pinctrl_perip_select(pmx, pins[i], true);
-
- return 0;
-}
-
-/**
- * tz1090_pinctrl_gpio_request_enable() - Put pin in GPIO mode.
- * @pctldev: Pin control data
- * @range: GPIO range
- * @pin: Pin number
- *
- * Puts a particular pin into GPIO mode, disabling peripheral control until it's
- * disabled again.
- */
-static int tz1090_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
- struct pinctrl_gpio_range *range,
- unsigned int pin)
-{
- struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
- tz1090_pinctrl_gpio_select(pmx, pin, true);
- return 0;
-}
-
-/**
- * tz1090_pinctrl_gpio_disable_free() - Take pin out of GPIO mode.
- * @pctldev: Pin control data
- * @range: GPIO range
- * @pin: Pin number
- *
- * Take a particular pin out of GPIO mode. If the pin is enabled for a
- * peripheral it will return to peripheral mode.
- */
-static void tz1090_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev,
- struct pinctrl_gpio_range *range,
- unsigned int pin)
-{
- struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
- tz1090_pinctrl_gpio_select(pmx, pin, false);
-}
-
-static const struct pinmux_ops tz1090_pinmux_ops = {
- .get_functions_count = tz1090_pinctrl_get_funcs_count,
- .get_function_name = tz1090_pinctrl_get_func_name,
- .get_function_groups = tz1090_pinctrl_get_func_groups,
- .set_mux = tz1090_pinctrl_set_mux,
- .gpio_request_enable = tz1090_pinctrl_gpio_request_enable,
- .gpio_disable_free = tz1090_pinctrl_gpio_disable_free,
-};
-
-/*
- * Pin config operations
- */
-
-struct tz1090_pinconf_pullup {
- unsigned char index;
- unsigned char shift;
-};
-
-/* The mapping of pin to pull up/down register index and shift */
-static struct tz1090_pinconf_pullup tz1090_pinconf_pullup[] = {
- {5, 22}, /* 0 - TZ1090_PIN_SDIO_CLK */
- {0, 14}, /* 1 - TZ1090_PIN_SDIO_CMD */
- {0, 6}, /* 2 - TZ1090_PIN_SDIO_D0 */
- {0, 8}, /* 3 - TZ1090_PIN_SDIO_D1 */
- {0, 10}, /* 4 - TZ1090_PIN_SDIO_D2 */
- {0, 12}, /* 5 - TZ1090_PIN_SDIO_D3 */
- {0, 2}, /* 6 - TZ1090_PIN_SDH_CD */
- {0, 4}, /* 7 - TZ1090_PIN_SDH_WP */
- {0, 16}, /* 8 - TZ1090_PIN_SPI0_MCLK */
- {0, 18}, /* 9 - TZ1090_PIN_SPI0_CS0 */
- {0, 20}, /* 10 - TZ1090_PIN_SPI0_CS1 */
- {0, 22}, /* 11 - TZ1090_PIN_SPI0_CS2 */
- {0, 24}, /* 12 - TZ1090_PIN_SPI0_DOUT */
- {0, 26}, /* 13 - TZ1090_PIN_SPI0_DIN */
- {0, 28}, /* 14 - TZ1090_PIN_SPI1_MCLK */
- {0, 30}, /* 15 - TZ1090_PIN_SPI1_CS0 */
- {1, 0}, /* 16 - TZ1090_PIN_SPI1_CS1 */
- {1, 2}, /* 17 - TZ1090_PIN_SPI1_CS2 */
- {1, 4}, /* 18 - TZ1090_PIN_SPI1_DOUT */
- {1, 6}, /* 19 - TZ1090_PIN_SPI1_DIN */
- {1, 8}, /* 20 - TZ1090_PIN_UART0_RXD */
- {1, 10}, /* 21 - TZ1090_PIN_UART0_TXD */
- {1, 12}, /* 22 - TZ1090_PIN_UART0_CTS */
- {1, 14}, /* 23 - TZ1090_PIN_UART0_RTS */
- {1, 16}, /* 24 - TZ1090_PIN_UART1_RXD */
- {1, 18}, /* 25 - TZ1090_PIN_UART1_TXD */
- {1, 20}, /* 26 - TZ1090_PIN_SCB0_SDAT */
- {1, 22}, /* 27 - TZ1090_PIN_SCB0_SCLK */
- {1, 24}, /* 28 - TZ1090_PIN_SCB1_SDAT */
- {1, 26}, /* 29 - TZ1090_PIN_SCB1_SCLK */
-
- {1, 28}, /* 30 - TZ1090_PIN_SCB2_SDAT */
- {1, 30}, /* 31 - TZ1090_PIN_SCB2_SCLK */
- {2, 0}, /* 32 - TZ1090_PIN_I2S_MCLK */
- {2, 2}, /* 33 - TZ1090_PIN_I2S_BCLK_OUT */
- {2, 4}, /* 34 - TZ1090_PIN_I2S_LRCLK_OUT */
- {2, 6}, /* 35 - TZ1090_PIN_I2S_DOUT0 */
- {2, 8}, /* 36 - TZ1090_PIN_I2S_DOUT1 */
- {2, 10}, /* 37 - TZ1090_PIN_I2S_DOUT2 */
- {2, 12}, /* 38 - TZ1090_PIN_I2S_DIN */
- {4, 12}, /* 39 - TZ1090_PIN_PDM_A */
- {4, 14}, /* 40 - TZ1090_PIN_PDM_B */
- {4, 18}, /* 41 - TZ1090_PIN_PDM_C */
- {4, 20}, /* 42 - TZ1090_PIN_PDM_D */
- {2, 14}, /* 43 - TZ1090_PIN_TFT_RED0 */
- {2, 16}, /* 44 - TZ1090_PIN_TFT_RED1 */
- {2, 18}, /* 45 - TZ1090_PIN_TFT_RED2 */
- {2, 20}, /* 46 - TZ1090_PIN_TFT_RED3 */
- {2, 22}, /* 47 - TZ1090_PIN_TFT_RED4 */
- {2, 24}, /* 48 - TZ1090_PIN_TFT_RED5 */
- {2, 26}, /* 49 - TZ1090_PIN_TFT_RED6 */
- {2, 28}, /* 50 - TZ1090_PIN_TFT_RED7 */
- {2, 30}, /* 51 - TZ1090_PIN_TFT_GREEN0 */
- {3, 0}, /* 52 - TZ1090_PIN_TFT_GREEN1 */
- {3, 2}, /* 53 - TZ1090_PIN_TFT_GREEN2 */
- {3, 4}, /* 54 - TZ1090_PIN_TFT_GREEN3 */
- {3, 6}, /* 55 - TZ1090_PIN_TFT_GREEN4 */
- {3, 8}, /* 56 - TZ1090_PIN_TFT_GREEN5 */
- {3, 10}, /* 57 - TZ1090_PIN_TFT_GREEN6 */
- {3, 12}, /* 58 - TZ1090_PIN_TFT_GREEN7 */
- {3, 14}, /* 59 - TZ1090_PIN_TFT_BLUE0 */
-
- {3, 16}, /* 60 - TZ1090_PIN_TFT_BLUE1 */
- {3, 18}, /* 61 - TZ1090_PIN_TFT_BLUE2 */
- {3, 20}, /* 62 - TZ1090_PIN_TFT_BLUE3 */
- {3, 22}, /* 63 - TZ1090_PIN_TFT_BLUE4 */
- {3, 24}, /* 64 - TZ1090_PIN_TFT_BLUE5 */
- {3, 26}, /* 65 - TZ1090_PIN_TFT_BLUE6 */
- {3, 28}, /* 66 - TZ1090_PIN_TFT_BLUE7 */
- {3, 30}, /* 67 - TZ1090_PIN_TFT_VDDEN_GD */
- {4, 0}, /* 68 - TZ1090_PIN_TFT_PANELCLK */
- {4, 2}, /* 69 - TZ1090_PIN_TFT_BLANK_LS */
- {4, 4}, /* 70 - TZ1090_PIN_TFT_VSYNC_NS */
- {4, 6}, /* 71 - TZ1090_PIN_TFT_HSYNC_NR */
- {4, 8}, /* 72 - TZ1090_PIN_TFT_VD12ACB */
- {4, 10}, /* 73 - TZ1090_PIN_TFT_PWRSAVE */
- {4, 24}, /* 74 - TZ1090_PIN_TX_ON */
- {4, 26}, /* 75 - TZ1090_PIN_RX_ON */
- {4, 28}, /* 76 - TZ1090_PIN_PLL_ON */
- {4, 30}, /* 77 - TZ1090_PIN_PA_ON */
- {5, 0}, /* 78 - TZ1090_PIN_RX_HP */
- {5, 6}, /* 79 - TZ1090_PIN_GAIN0 */
- {5, 8}, /* 80 - TZ1090_PIN_GAIN1 */
- {5, 10}, /* 81 - TZ1090_PIN_GAIN2 */
- {5, 12}, /* 82 - TZ1090_PIN_GAIN3 */
- {5, 14}, /* 83 - TZ1090_PIN_GAIN4 */
- {5, 16}, /* 84 - TZ1090_PIN_GAIN5 */
- {5, 18}, /* 85 - TZ1090_PIN_GAIN6 */
- {5, 20}, /* 86 - TZ1090_PIN_GAIN7 */
- {5, 2}, /* 87 - TZ1090_PIN_ANT_SEL0 */
- {5, 4}, /* 88 - TZ1090_PIN_ANT_SEL1 */
- {0, 0}, /* 89 - TZ1090_PIN_SDH_CLK_IN */
-
- {5, 24}, /* 90 - TZ1090_PIN_TCK */
- {5, 26}, /* 91 - TZ1090_PIN_TRST */
- {5, 28}, /* 92 - TZ1090_PIN_TDI */
- {5, 30}, /* 93 - TZ1090_PIN_TDO */
- {6, 0}, /* 94 - TZ1090_PIN_TMS */
- {4, 16}, /* 95 - TZ1090_PIN_CLK_OUT0 */
- {4, 22}, /* 96 - TZ1090_PIN_CLK_OUT1 */
-};
-
-static int tz1090_pinconf_reg(struct pinctrl_dev *pctldev,
- unsigned int pin,
- enum pin_config_param param,
- bool report_err,
- u32 *reg, u32 *width, u32 *mask, u32 *shift,
- u32 *val)
-{
- struct tz1090_pinconf_pullup *pu;
-
- /* All supported pins have controllable input bias */
- switch (param) {
- case PIN_CONFIG_BIAS_DISABLE:
- case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
- *val = REG_PU_PD_TRISTATE;
- break;
- case PIN_CONFIG_BIAS_PULL_UP:
- *val = REG_PU_PD_UP;
- break;
- case PIN_CONFIG_BIAS_PULL_DOWN:
- *val = REG_PU_PD_DOWN;
- break;
- case PIN_CONFIG_BIAS_BUS_HOLD:
- *val = REG_PU_PD_REPEATER;
- break;
- default:
- return -ENOTSUPP;
- }
-
- /* Only input bias parameters supported */
- pu = &tz1090_pinconf_pullup[pin];
- *reg = REG_PINCTRL_PU_PD + 4*pu->index;
- *shift = pu->shift;
- *width = 2;
-
- /* Calculate field information */
- *mask = (BIT(*width) - 1) << *shift;
-
- return 0;
-}
-
-static int tz1090_pinconf_get(struct pinctrl_dev *pctldev,
- unsigned int pin, unsigned long *config)
-{
- struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
- enum pin_config_param param = pinconf_to_config_param(*config);
- int ret;
- u32 reg, width, mask, shift, val, tmp, arg;
-
- /* Get register information */
- ret = tz1090_pinconf_reg(pctldev, pin, param, true,
- &reg, &width, &mask, &shift, &val);
- if (ret < 0)
- return ret;
-
- /* Extract field from register */
- tmp = pmx_read(pmx, reg);
- arg = ((tmp & mask) >> shift) == val;
-
- /* Config not active */
- if (!arg)
- return -EINVAL;
-
- /* And pack config */
- *config = pinconf_to_config_packed(param, arg);
-
- return 0;
-}
-
-static int tz1090_pinconf_set(struct pinctrl_dev *pctldev,
- unsigned int pin, unsigned long *configs,
- unsigned num_configs)
-{
- struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
- enum pin_config_param param;
- unsigned int arg;
- int ret;
- u32 reg, width, mask, shift, val, tmp;
- unsigned long flags;
- int i;
-
- for (i = 0; i < num_configs; i++) {
- param = pinconf_to_config_param(configs[i]);
- arg = pinconf_to_config_argument(configs[i]);
-
- dev_dbg(pctldev->dev, "%s(pin=%s, config=%#lx)\n",
- __func__, tz1090_pins[pin].name, configs[i]);
-
- /* Get register information */
- ret = tz1090_pinconf_reg(pctldev, pin, param, true,
- &reg, &width, &mask, &shift, &val);
- if (ret < 0)
- return ret;
-
- /* Unpack argument and range check it */
- if (arg > 1) {
- dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
- __func__, arg);
- return -EINVAL;
- }
-
- /* Write register field */
- __global_lock2(flags);
- tmp = pmx_read(pmx, reg);
- tmp &= ~mask;
- if (arg)
- tmp |= val << shift;
- pmx_write(pmx, tmp, reg);
- __global_unlock2(flags);
- } /* for each config */
-
- return 0;
-}
-
-static const int tz1090_boolean_map[] = {
- [0] = -EINVAL,
- [1] = 1,
-};
-
-static const int tz1090_dr_map[] = {
- [REG_DR_2mA] = 2,
- [REG_DR_4mA] = 4,
- [REG_DR_8mA] = 8,
- [REG_DR_12mA] = 12,
-};
-
-static int tz1090_pinconf_group_reg(struct pinctrl_dev *pctldev,
- const struct tz1090_pingroup *g,
- enum pin_config_param param,
- bool report_err,
- u32 *reg, u32 *width, u32 *mask, u32 *shift,
- const int **map)
-{
- /* Drive configuration applies in groups, but not to all groups. */
- if (!g->drv) {
- if (report_err)
- dev_dbg(pctldev->dev,
- "%s: group %s has no drive control\n",
- __func__, g->name);
- return -ENOTSUPP;
- }
-
- /* Find information about drive parameter's register */
- switch (param) {
- case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
- *reg = REG_PINCTRL_SCHMITT;
- *width = 1;
- *map = tz1090_boolean_map;
- break;
- case PIN_CONFIG_DRIVE_STRENGTH:
- *reg = REG_PINCTRL_DR;
- *width = 2;
- *map = tz1090_dr_map;
- break;
- default:
- return -ENOTSUPP;
- }
-
- /* Calculate field information */
- *shift = g->slw_bit * *width;
- *mask = (BIT(*width) - 1) << *shift;
-
- return 0;
-}
-
-static int tz1090_pinconf_group_get(struct pinctrl_dev *pctldev,
- unsigned int group,
- unsigned long *config)
-{
- struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
- const struct tz1090_pingroup *g;
- enum pin_config_param param = pinconf_to_config_param(*config);
- int ret, arg;
- unsigned int pin;
- u32 reg, width, mask, shift, val;
- const int *map;
-
- if (group >= ARRAY_SIZE(tz1090_groups)) {
- pin = group - ARRAY_SIZE(tz1090_groups);
- return tz1090_pinconf_get(pctldev, pin, config);
- }
-
- g = &tz1090_groups[group];
- if (g->npins == 1) {
- pin = g->pins[0];
- ret = tz1090_pinconf_get(pctldev, pin, config);
- if (ret != -ENOTSUPP)
- return ret;
- }
-
- /* Get register information */
- ret = tz1090_pinconf_group_reg(pctldev, g, param, true,
- &reg, &width, &mask, &shift, &map);
- if (ret < 0)
- return ret;
-
- /* Extract field from register */
- val = pmx_read(pmx, reg);
- arg = map[(val & mask) >> shift];
- if (arg < 0)
- return arg;
-
- /* And pack config */
- *config = pinconf_to_config_packed(param, arg);
-
- return 0;
-}
-
-static int tz1090_pinconf_group_set(struct pinctrl_dev *pctldev,
- unsigned int group, unsigned long *configs,
- unsigned num_configs)
-{
- struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
- const struct tz1090_pingroup *g;
- enum pin_config_param param;
- unsigned int arg, pin, i;
- const unsigned int *pit;
- int ret;
- u32 reg, width, mask, shift, val;
- unsigned long flags;
- const int *map;
- int j;
-
- if (group >= ARRAY_SIZE(tz1090_groups)) {
- pin = group - ARRAY_SIZE(tz1090_groups);
- return tz1090_pinconf_set(pctldev, pin, configs, num_configs);
- }
-
- g = &tz1090_groups[group];
- if (g->npins == 1) {
- pin = g->pins[0];
- ret = tz1090_pinconf_set(pctldev, pin, configs, num_configs);
- if (ret != -ENOTSUPP)
- return ret;
- }
-
- for (j = 0; j < num_configs; j++) {
- param = pinconf_to_config_param(configs[j]);
-
- dev_dbg(pctldev->dev, "%s(group=%s, config=%#lx)\n",
- __func__, g->name, configs[j]);
-
- /* Get register information */
- ret = tz1090_pinconf_group_reg(pctldev, g, param, true, &reg,
- &width, &mask, &shift, &map);
- if (ret < 0) {
- /*
- * Maybe we're trying to set a per-pin configuration
- * of a group, so do the pins one by one. This is
- * mainly as a convenience.
- */
- for (i = 0, pit = g->pins; i < g->npins; ++i, ++pit) {
- ret = tz1090_pinconf_set(pctldev, *pit, configs,
- num_configs);
- if (ret)
- return ret;
- }
- return 0;
- }
-
- /* Unpack argument and map it to register value */
- arg = pinconf_to_config_argument(configs[j]);
- for (i = 0; i < BIT(width); ++i) {
- if (map[i] == arg || (map[i] == -EINVAL && !arg)) {
- /* Write register field */
- __global_lock2(flags);
- val = pmx_read(pmx, reg);
- val &= ~mask;
- val |= i << shift;
- pmx_write(pmx, val, reg);
- __global_unlock2(flags);
- goto next_config;
- }
- }
-
- dev_dbg(pctldev->dev, "%s: arg %u not supported\n",
- __func__, arg);
- return -EINVAL;
-
-next_config:
- ;
- } /* for each config */
-
- return 0;
-}
-
-static const struct pinconf_ops tz1090_pinconf_ops = {
- .is_generic = true,
- .pin_config_get = tz1090_pinconf_get,
- .pin_config_set = tz1090_pinconf_set,
- .pin_config_group_get = tz1090_pinconf_group_get,
- .pin_config_group_set = tz1090_pinconf_group_set,
- .pin_config_config_dbg_show = pinconf_generic_dump_config,
-};
-
-/*
- * Pin control driver setup
- */
-
-static struct pinctrl_desc tz1090_pinctrl_desc = {
- .pctlops = &tz1090_pinctrl_ops,
- .pmxops = &tz1090_pinmux_ops,
- .confops = &tz1090_pinconf_ops,
- .owner = THIS_MODULE,
-};
-
-static int tz1090_pinctrl_probe(struct platform_device *pdev)
-{
- struct tz1090_pmx *pmx;
- struct resource *res;
-
- pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
- if (!pmx)
- return -ENOMEM;
-
- pmx->dev = &pdev->dev;
- spin_lock_init(&pmx->lock);
-
- tz1090_pinctrl_desc.name = dev_name(&pdev->dev);
- tz1090_pinctrl_desc.pins = tz1090_pins;
- tz1090_pinctrl_desc.npins = ARRAY_SIZE(tz1090_pins);
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- pmx->regs = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(pmx->regs))
- return PTR_ERR(pmx->regs);
-
- pmx->pctl = devm_pinctrl_register(&pdev->dev, &tz1090_pinctrl_desc,
- pmx);
- if (IS_ERR(pmx->pctl)) {
- dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
- return PTR_ERR(pmx->pctl);
- }
-
- platform_set_drvdata(pdev, pmx);
-
- dev_info(&pdev->dev, "TZ1090 pinctrl driver initialised\n");
-
- return 0;
-}
-
-static const struct of_device_id tz1090_pinctrl_of_match[] = {
- { .compatible = "img,tz1090-pinctrl", },
- { },
-};
-
-static struct platform_driver tz1090_pinctrl_driver = {
- .driver = {
- .name = "tz1090-pinctrl",
- .of_match_table = tz1090_pinctrl_of_match,
- },
- .probe = tz1090_pinctrl_probe,
-};
-
-static int __init tz1090_pinctrl_init(void)
-{
- tz1090_init_mux_pins();
- return platform_driver_register(&tz1090_pinctrl_driver);
-}
-arch_initcall(tz1090_pinctrl_init);
-
-static void __exit tz1090_pinctrl_exit(void)
-{
- platform_driver_unregister(&tz1090_pinctrl_driver);
-}
-module_exit(tz1090_pinctrl_exit);
-
-MODULE_AUTHOR("Imagination Technologies Ltd.");
-MODULE_DESCRIPTION("Toumaz Xenif TZ1090 pinctrl driver");
-MODULE_LICENSE("GPL v2");
-MODULE_DEVICE_TABLE(of, tz1090_pinctrl_of_match);
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index fcaaa92d76df..195492033075 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -147,4 +147,13 @@ config PINCTRL_QCOM_SSBI_PMIC
which are using SSBI for communication with SoC. Example PMIC's
devices are pm8058 and pm8921.
+config PINCTRL_SDM845
+ tristate "Qualcomm Technologies Inc SDM845 pin controller driver"
+ depends on GPIOLIB && OF
+ select PINCTRL_MSM
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc TLMM block found on the Qualcomm
+ Technologies Inc SDM845 platform.
+
endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 8cb45bbd2e7f..0c6f3ddc296d 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o
obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o
obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o
+obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 495432f3341b..95e5c5ea40af 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -818,7 +818,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
return -EINVAL;
chip = &pctrl->chip;
- chip->base = 0;
+ chip->base = -1;
chip->ngpio = ngpio;
chip->label = dev_name(pctrl->dev);
chip->parent = pctrl->dev;
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8998.c b/drivers/pinctrl/qcom/pinctrl-msm8998.c
index c33953183013..00d7b94bc3f1 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm8998.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8998.c
@@ -1566,7 +1566,6 @@ static const struct of_device_id msm8998_pinctrl_of_match[] = {
static struct platform_driver msm8998_pinctrl_driver = {
.driver = {
.name = "msm8998-pinctrl",
- .owner = THIS_MODULE,
.of_match_table = msm8998_pinctrl_of_match,
},
.probe = msm8998_pinctrl_probe,
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c
new file mode 100644
index 000000000000..2ab7a8885757
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c
@@ -0,0 +1,1323 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-msm.h"
+
+#define FUNCTION(fname) \
+ [msm_mux_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define NORTH 0x00500000
+#define SOUTH 0x00900000
+#define EAST 0x00100000
+#define REG_SIZE 0x1000
+#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins, \
+ .npins = ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ msm_mux_gpio, /* gpio mode */ \
+ msm_mux_##f1, \
+ msm_mux_##f2, \
+ msm_mux_##f3, \
+ msm_mux_##f4, \
+ msm_mux_##f5, \
+ msm_mux_##f6, \
+ msm_mux_##f7, \
+ msm_mux_##f8, \
+ msm_mux_##f9, \
+ msm_mux_##f10 \
+ }, \
+ .nfuncs = 11, \
+ .ctl_reg = base + REG_SIZE * id, \
+ .io_reg = base + 0x4 + REG_SIZE * id, \
+ .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \
+ .intr_status_reg = base + 0xc + REG_SIZE * id, \
+ .intr_target_reg = base + 0x8 + REG_SIZE * id, \
+ .mux_bit = 2, \
+ .pull_bit = 0, \
+ .drv_bit = 6, \
+ .oe_bit = 9, \
+ .in_bit = 0, \
+ .out_bit = 1, \
+ .intr_enable_bit = 0, \
+ .intr_status_bit = 0, \
+ .intr_target_bit = 5, \
+ .intr_target_kpss_val = 3, \
+ .intr_raw_status_bit = 4, \
+ .intr_polarity_bit = 1, \
+ .intr_detection_bit = 2, \
+ .intr_detection_width = 2, \
+ }
+
+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
+ { \
+ .name = #pg_name, \
+ .pins = pg_name##_pins, \
+ .npins = ARRAY_SIZE(pg_name##_pins), \
+ .ctl_reg = ctl, \
+ .io_reg = 0, \
+ .intr_cfg_reg = 0, \
+ .intr_status_reg = 0, \
+ .intr_target_reg = 0, \
+ .mux_bit = -1, \
+ .pull_bit = pull, \
+ .drv_bit = drv, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = -1, \
+ .intr_enable_bit = -1, \
+ .intr_status_bit = -1, \
+ .intr_target_bit = -1, \
+ .intr_raw_status_bit = -1, \
+ .intr_polarity_bit = -1, \
+ .intr_detection_bit = -1, \
+ .intr_detection_width = -1, \
+ }
+
+#define UFS_RESET(pg_name, offset) \
+ { \
+ .name = #pg_name, \
+ .pins = pg_name##_pins, \
+ .npins = ARRAY_SIZE(pg_name##_pins), \
+ .ctl_reg = offset, \
+ .io_reg = offset + 0x4, \
+ .intr_cfg_reg = 0, \
+ .intr_status_reg = 0, \
+ .intr_target_reg = 0, \
+ .mux_bit = -1, \
+ .pull_bit = 3, \
+ .drv_bit = 0, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = 0, \
+ .intr_enable_bit = -1, \
+ .intr_status_bit = -1, \
+ .intr_target_bit = -1, \
+ .intr_raw_status_bit = -1, \
+ .intr_polarity_bit = -1, \
+ .intr_detection_bit = -1, \
+ .intr_detection_width = -1, \
+ }
+static const struct pinctrl_pin_desc sdm845_pins[] = {
+ PINCTRL_PIN(0, "GPIO_0"),
+ PINCTRL_PIN(1, "GPIO_1"),
+ PINCTRL_PIN(2, "GPIO_2"),
+ PINCTRL_PIN(3, "GPIO_3"),
+ PINCTRL_PIN(4, "GPIO_4"),
+ PINCTRL_PIN(5, "GPIO_5"),
+ PINCTRL_PIN(6, "GPIO_6"),
+ PINCTRL_PIN(7, "GPIO_7"),
+ PINCTRL_PIN(8, "GPIO_8"),
+ PINCTRL_PIN(9, "GPIO_9"),
+ PINCTRL_PIN(10, "GPIO_10"),
+ PINCTRL_PIN(11, "GPIO_11"),
+ PINCTRL_PIN(12, "GPIO_12"),
+ PINCTRL_PIN(13, "GPIO_13"),
+ PINCTRL_PIN(14, "GPIO_14"),
+ PINCTRL_PIN(15, "GPIO_15"),
+ PINCTRL_PIN(16, "GPIO_16"),
+ PINCTRL_PIN(17, "GPIO_17"),
+ PINCTRL_PIN(18, "GPIO_18"),
+ PINCTRL_PIN(19, "GPIO_19"),
+ PINCTRL_PIN(20, "GPIO_20"),
+ PINCTRL_PIN(21, "GPIO_21"),
+ PINCTRL_PIN(22, "GPIO_22"),
+ PINCTRL_PIN(23, "GPIO_23"),
+ PINCTRL_PIN(24, "GPIO_24"),
+ PINCTRL_PIN(25, "GPIO_25"),
+ PINCTRL_PIN(26, "GPIO_26"),
+ PINCTRL_PIN(27, "GPIO_27"),
+ PINCTRL_PIN(28, "GPIO_28"),
+ PINCTRL_PIN(29, "GPIO_29"),
+ PINCTRL_PIN(30, "GPIO_30"),
+ PINCTRL_PIN(31, "GPIO_31"),
+ PINCTRL_PIN(32, "GPIO_32"),
+ PINCTRL_PIN(33, "GPIO_33"),
+ PINCTRL_PIN(34, "GPIO_34"),
+ PINCTRL_PIN(35, "GPIO_35"),
+ PINCTRL_PIN(36, "GPIO_36"),
+ PINCTRL_PIN(37, "GPIO_37"),
+ PINCTRL_PIN(38, "GPIO_38"),
+ PINCTRL_PIN(39, "GPIO_39"),
+ PINCTRL_PIN(40, "GPIO_40"),
+ PINCTRL_PIN(41, "GPIO_41"),
+ PINCTRL_PIN(42, "GPIO_42"),
+ PINCTRL_PIN(43, "GPIO_43"),
+ PINCTRL_PIN(44, "GPIO_44"),
+ PINCTRL_PIN(45, "GPIO_45"),
+ PINCTRL_PIN(46, "GPIO_46"),
+ PINCTRL_PIN(47, "GPIO_47"),
+ PINCTRL_PIN(48, "GPIO_48"),
+ PINCTRL_PIN(49, "GPIO_49"),
+ PINCTRL_PIN(50, "GPIO_50"),
+ PINCTRL_PIN(51, "GPIO_51"),
+ PINCTRL_PIN(52, "GPIO_52"),
+ PINCTRL_PIN(53, "GPIO_53"),
+ PINCTRL_PIN(54, "GPIO_54"),
+ PINCTRL_PIN(55, "GPIO_55"),
+ PINCTRL_PIN(56, "GPIO_56"),
+ PINCTRL_PIN(57, "GPIO_57"),
+ PINCTRL_PIN(58, "GPIO_58"),
+ PINCTRL_PIN(59, "GPIO_59"),
+ PINCTRL_PIN(60, "GPIO_60"),
+ PINCTRL_PIN(61, "GPIO_61"),
+ PINCTRL_PIN(62, "GPIO_62"),
+ PINCTRL_PIN(63, "GPIO_63"),
+ PINCTRL_PIN(64, "GPIO_64"),
+ PINCTRL_PIN(65, "GPIO_65"),
+ PINCTRL_PIN(66, "GPIO_66"),
+ PINCTRL_PIN(67, "GPIO_67"),
+ PINCTRL_PIN(68, "GPIO_68"),
+ PINCTRL_PIN(69, "GPIO_69"),
+ PINCTRL_PIN(70, "GPIO_70"),
+ PINCTRL_PIN(71, "GPIO_71"),
+ PINCTRL_PIN(72, "GPIO_72"),
+ PINCTRL_PIN(73, "GPIO_73"),
+ PINCTRL_PIN(74, "GPIO_74"),
+ PINCTRL_PIN(75, "GPIO_75"),
+ PINCTRL_PIN(76, "GPIO_76"),
+ PINCTRL_PIN(77, "GPIO_77"),
+ PINCTRL_PIN(78, "GPIO_78"),
+ PINCTRL_PIN(79, "GPIO_79"),
+ PINCTRL_PIN(80, "GPIO_80"),
+ PINCTRL_PIN(81, "GPIO_81"),
+ PINCTRL_PIN(82, "GPIO_82"),
+ PINCTRL_PIN(83, "GPIO_83"),
+ PINCTRL_PIN(84, "GPIO_84"),
+ PINCTRL_PIN(85, "GPIO_85"),
+ PINCTRL_PIN(86, "GPIO_86"),
+ PINCTRL_PIN(87, "GPIO_87"),
+ PINCTRL_PIN(88, "GPIO_88"),
+ PINCTRL_PIN(89, "GPIO_89"),
+ PINCTRL_PIN(90, "GPIO_90"),
+ PINCTRL_PIN(91, "GPIO_91"),
+ PINCTRL_PIN(92, "GPIO_92"),
+ PINCTRL_PIN(93, "GPIO_93"),
+ PINCTRL_PIN(94, "GPIO_94"),
+ PINCTRL_PIN(95, "GPIO_95"),
+ PINCTRL_PIN(96, "GPIO_96"),
+ PINCTRL_PIN(97, "GPIO_97"),
+ PINCTRL_PIN(98, "GPIO_98"),
+ PINCTRL_PIN(99, "GPIO_99"),
+ PINCTRL_PIN(100, "GPIO_100"),
+ PINCTRL_PIN(101, "GPIO_101"),
+ PINCTRL_PIN(102, "GPIO_102"),
+ PINCTRL_PIN(103, "GPIO_103"),
+ PINCTRL_PIN(104, "GPIO_104"),
+ PINCTRL_PIN(105, "GPIO_105"),
+ PINCTRL_PIN(106, "GPIO_106"),
+ PINCTRL_PIN(107, "GPIO_107"),
+ PINCTRL_PIN(108, "GPIO_108"),
+ PINCTRL_PIN(109, "GPIO_109"),
+ PINCTRL_PIN(110, "GPIO_110"),
+ PINCTRL_PIN(111, "GPIO_111"),
+ PINCTRL_PIN(112, "GPIO_112"),
+ PINCTRL_PIN(113, "GPIO_113"),
+ PINCTRL_PIN(114, "GPIO_114"),
+ PINCTRL_PIN(115, "GPIO_115"),
+ PINCTRL_PIN(116, "GPIO_116"),
+ PINCTRL_PIN(117, "GPIO_117"),
+ PINCTRL_PIN(118, "GPIO_118"),
+ PINCTRL_PIN(119, "GPIO_119"),
+ PINCTRL_PIN(120, "GPIO_120"),
+ PINCTRL_PIN(121, "GPIO_121"),
+ PINCTRL_PIN(122, "GPIO_122"),
+ PINCTRL_PIN(123, "GPIO_123"),
+ PINCTRL_PIN(124, "GPIO_124"),
+ PINCTRL_PIN(125, "GPIO_125"),
+ PINCTRL_PIN(126, "GPIO_126"),
+ PINCTRL_PIN(127, "GPIO_127"),
+ PINCTRL_PIN(128, "GPIO_128"),
+ PINCTRL_PIN(129, "GPIO_129"),
+ PINCTRL_PIN(130, "GPIO_130"),
+ PINCTRL_PIN(131, "GPIO_131"),
+ PINCTRL_PIN(132, "GPIO_132"),
+ PINCTRL_PIN(133, "GPIO_133"),
+ PINCTRL_PIN(134, "GPIO_134"),
+ PINCTRL_PIN(135, "GPIO_135"),
+ PINCTRL_PIN(136, "GPIO_136"),
+ PINCTRL_PIN(137, "GPIO_137"),
+ PINCTRL_PIN(138, "GPIO_138"),
+ PINCTRL_PIN(139, "GPIO_139"),
+ PINCTRL_PIN(140, "GPIO_140"),
+ PINCTRL_PIN(141, "GPIO_141"),
+ PINCTRL_PIN(142, "GPIO_142"),
+ PINCTRL_PIN(143, "GPIO_143"),
+ PINCTRL_PIN(144, "GPIO_144"),
+ PINCTRL_PIN(145, "GPIO_145"),
+ PINCTRL_PIN(146, "GPIO_146"),
+ PINCTRL_PIN(147, "GPIO_147"),
+ PINCTRL_PIN(148, "GPIO_148"),
+ PINCTRL_PIN(149, "GPIO_149"),
+ PINCTRL_PIN(150, "SDC2_CLK"),
+ PINCTRL_PIN(151, "SDC2_CMD"),
+ PINCTRL_PIN(152, "SDC2_DATA"),
+ PINCTRL_PIN(153, "UFS_RESET"),
+};
+
+#define DECLARE_MSM_GPIO_PINS(pin) \
+ static const unsigned int gpio##pin##_pins[] = { pin }
+DECLARE_MSM_GPIO_PINS(0);
+DECLARE_MSM_GPIO_PINS(1);
+DECLARE_MSM_GPIO_PINS(2);
+DECLARE_MSM_GPIO_PINS(3);
+DECLARE_MSM_GPIO_PINS(4);
+DECLARE_MSM_GPIO_PINS(5);
+DECLARE_MSM_GPIO_PINS(6);
+DECLARE_MSM_GPIO_PINS(7);
+DECLARE_MSM_GPIO_PINS(8);
+DECLARE_MSM_GPIO_PINS(9);
+DECLARE_MSM_GPIO_PINS(10);
+DECLARE_MSM_GPIO_PINS(11);
+DECLARE_MSM_GPIO_PINS(12);
+DECLARE_MSM_GPIO_PINS(13);
+DECLARE_MSM_GPIO_PINS(14);
+DECLARE_MSM_GPIO_PINS(15);
+DECLARE_MSM_GPIO_PINS(16);
+DECLARE_MSM_GPIO_PINS(17);
+DECLARE_MSM_GPIO_PINS(18);
+DECLARE_MSM_GPIO_PINS(19);
+DECLARE_MSM_GPIO_PINS(20);
+DECLARE_MSM_GPIO_PINS(21);
+DECLARE_MSM_GPIO_PINS(22);
+DECLARE_MSM_GPIO_PINS(23);
+DECLARE_MSM_GPIO_PINS(24);
+DECLARE_MSM_GPIO_PINS(25);
+DECLARE_MSM_GPIO_PINS(26);
+DECLARE_MSM_GPIO_PINS(27);
+DECLARE_MSM_GPIO_PINS(28);
+DECLARE_MSM_GPIO_PINS(29);
+DECLARE_MSM_GPIO_PINS(30);
+DECLARE_MSM_GPIO_PINS(31);
+DECLARE_MSM_GPIO_PINS(32);
+DECLARE_MSM_GPIO_PINS(33);
+DECLARE_MSM_GPIO_PINS(34);
+DECLARE_MSM_GPIO_PINS(35);
+DECLARE_MSM_GPIO_PINS(36);
+DECLARE_MSM_GPIO_PINS(37);
+DECLARE_MSM_GPIO_PINS(38);
+DECLARE_MSM_GPIO_PINS(39);
+DECLARE_MSM_GPIO_PINS(40);
+DECLARE_MSM_GPIO_PINS(41);
+DECLARE_MSM_GPIO_PINS(42);
+DECLARE_MSM_GPIO_PINS(43);
+DECLARE_MSM_GPIO_PINS(44);
+DECLARE_MSM_GPIO_PINS(45);
+DECLARE_MSM_GPIO_PINS(46);
+DECLARE_MSM_GPIO_PINS(47);
+DECLARE_MSM_GPIO_PINS(48);
+DECLARE_MSM_GPIO_PINS(49);
+DECLARE_MSM_GPIO_PINS(50);
+DECLARE_MSM_GPIO_PINS(51);
+DECLARE_MSM_GPIO_PINS(52);
+DECLARE_MSM_GPIO_PINS(53);
+DECLARE_MSM_GPIO_PINS(54);
+DECLARE_MSM_GPIO_PINS(55);
+DECLARE_MSM_GPIO_PINS(56);
+DECLARE_MSM_GPIO_PINS(57);
+DECLARE_MSM_GPIO_PINS(58);
+DECLARE_MSM_GPIO_PINS(59);
+DECLARE_MSM_GPIO_PINS(60);
+DECLARE_MSM_GPIO_PINS(61);
+DECLARE_MSM_GPIO_PINS(62);
+DECLARE_MSM_GPIO_PINS(63);
+DECLARE_MSM_GPIO_PINS(64);
+DECLARE_MSM_GPIO_PINS(65);
+DECLARE_MSM_GPIO_PINS(66);
+DECLARE_MSM_GPIO_PINS(67);
+DECLARE_MSM_GPIO_PINS(68);
+DECLARE_MSM_GPIO_PINS(69);
+DECLARE_MSM_GPIO_PINS(70);
+DECLARE_MSM_GPIO_PINS(71);
+DECLARE_MSM_GPIO_PINS(72);
+DECLARE_MSM_GPIO_PINS(73);
+DECLARE_MSM_GPIO_PINS(74);
+DECLARE_MSM_GPIO_PINS(75);
+DECLARE_MSM_GPIO_PINS(76);
+DECLARE_MSM_GPIO_PINS(77);
+DECLARE_MSM_GPIO_PINS(78);
+DECLARE_MSM_GPIO_PINS(79);
+DECLARE_MSM_GPIO_PINS(80);
+DECLARE_MSM_GPIO_PINS(81);
+DECLARE_MSM_GPIO_PINS(82);
+DECLARE_MSM_GPIO_PINS(83);
+DECLARE_MSM_GPIO_PINS(84);
+DECLARE_MSM_GPIO_PINS(85);
+DECLARE_MSM_GPIO_PINS(86);
+DECLARE_MSM_GPIO_PINS(87);
+DECLARE_MSM_GPIO_PINS(88);
+DECLARE_MSM_GPIO_PINS(89);
+DECLARE_MSM_GPIO_PINS(90);
+DECLARE_MSM_GPIO_PINS(91);
+DECLARE_MSM_GPIO_PINS(92);
+DECLARE_MSM_GPIO_PINS(93);
+DECLARE_MSM_GPIO_PINS(94);
+DECLARE_MSM_GPIO_PINS(95);
+DECLARE_MSM_GPIO_PINS(96);
+DECLARE_MSM_GPIO_PINS(97);
+DECLARE_MSM_GPIO_PINS(98);
+DECLARE_MSM_GPIO_PINS(99);
+DECLARE_MSM_GPIO_PINS(100);
+DECLARE_MSM_GPIO_PINS(101);
+DECLARE_MSM_GPIO_PINS(102);
+DECLARE_MSM_GPIO_PINS(103);
+DECLARE_MSM_GPIO_PINS(104);
+DECLARE_MSM_GPIO_PINS(105);
+DECLARE_MSM_GPIO_PINS(106);
+DECLARE_MSM_GPIO_PINS(107);
+DECLARE_MSM_GPIO_PINS(108);
+DECLARE_MSM_GPIO_PINS(109);
+DECLARE_MSM_GPIO_PINS(110);
+DECLARE_MSM_GPIO_PINS(111);
+DECLARE_MSM_GPIO_PINS(112);
+DECLARE_MSM_GPIO_PINS(113);
+DECLARE_MSM_GPIO_PINS(114);
+DECLARE_MSM_GPIO_PINS(115);
+DECLARE_MSM_GPIO_PINS(116);
+DECLARE_MSM_GPIO_PINS(117);
+DECLARE_MSM_GPIO_PINS(118);
+DECLARE_MSM_GPIO_PINS(119);
+DECLARE_MSM_GPIO_PINS(120);
+DECLARE_MSM_GPIO_PINS(121);
+DECLARE_MSM_GPIO_PINS(122);
+DECLARE_MSM_GPIO_PINS(123);
+DECLARE_MSM_GPIO_PINS(124);
+DECLARE_MSM_GPIO_PINS(125);
+DECLARE_MSM_GPIO_PINS(126);
+DECLARE_MSM_GPIO_PINS(127);
+DECLARE_MSM_GPIO_PINS(128);
+DECLARE_MSM_GPIO_PINS(129);
+DECLARE_MSM_GPIO_PINS(130);
+DECLARE_MSM_GPIO_PINS(131);
+DECLARE_MSM_GPIO_PINS(132);
+DECLARE_MSM_GPIO_PINS(133);
+DECLARE_MSM_GPIO_PINS(134);
+DECLARE_MSM_GPIO_PINS(135);
+DECLARE_MSM_GPIO_PINS(136);
+DECLARE_MSM_GPIO_PINS(137);
+DECLARE_MSM_GPIO_PINS(138);
+DECLARE_MSM_GPIO_PINS(139);
+DECLARE_MSM_GPIO_PINS(140);
+DECLARE_MSM_GPIO_PINS(141);
+DECLARE_MSM_GPIO_PINS(142);
+DECLARE_MSM_GPIO_PINS(143);
+DECLARE_MSM_GPIO_PINS(144);
+DECLARE_MSM_GPIO_PINS(145);
+DECLARE_MSM_GPIO_PINS(146);
+DECLARE_MSM_GPIO_PINS(147);
+DECLARE_MSM_GPIO_PINS(148);
+DECLARE_MSM_GPIO_PINS(149);
+
+static const unsigned int sdc2_clk_pins[] = { 150 };
+static const unsigned int sdc2_cmd_pins[] = { 151 };
+static const unsigned int sdc2_data_pins[] = { 152 };
+static const unsigned int ufs_reset_pins[] = { 153 };
+
+enum sdm845_functions {
+ msm_mux_gpio,
+ msm_mux_adsp_ext,
+ msm_mux_agera_pll,
+ msm_mux_atest_char,
+ msm_mux_atest_tsens,
+ msm_mux_atest_tsens2,
+ msm_mux_atest_usb1,
+ msm_mux_atest_usb10,
+ msm_mux_atest_usb11,
+ msm_mux_atest_usb12,
+ msm_mux_atest_usb13,
+ msm_mux_atest_usb2,
+ msm_mux_atest_usb20,
+ msm_mux_atest_usb21,
+ msm_mux_atest_usb22,
+ msm_mux_atest_usb23,
+ msm_mux_audio_ref,
+ msm_mux_btfm_slimbus,
+ msm_mux_cam_mclk,
+ msm_mux_cci_async,
+ msm_mux_cci_i2c,
+ msm_mux_cci_timer0,
+ msm_mux_cci_timer1,
+ msm_mux_cci_timer2,
+ msm_mux_cci_timer3,
+ msm_mux_cci_timer4,
+ msm_mux_cri_trng,
+ msm_mux_cri_trng0,
+ msm_mux_cri_trng1,
+ msm_mux_dbg_out,
+ msm_mux_ddr_bist,
+ msm_mux_ddr_pxi0,
+ msm_mux_ddr_pxi1,
+ msm_mux_ddr_pxi2,
+ msm_mux_ddr_pxi3,
+ msm_mux_edp_hot,
+ msm_mux_edp_lcd,
+ msm_mux_gcc_gp1,
+ msm_mux_gcc_gp2,
+ msm_mux_gcc_gp3,
+ msm_mux_jitter_bist,
+ msm_mux_ldo_en,
+ msm_mux_ldo_update,
+ msm_mux_lpass_slimbus,
+ msm_mux_m_voc,
+ msm_mux_mdp_vsync,
+ msm_mux_mdp_vsync0,
+ msm_mux_mdp_vsync1,
+ msm_mux_mdp_vsync2,
+ msm_mux_mdp_vsync3,
+ msm_mux_mss_lte,
+ msm_mux_nav_pps,
+ msm_mux_pa_indicator,
+ msm_mux_pci_e0,
+ msm_mux_pci_e1,
+ msm_mux_phase_flag,
+ msm_mux_pll_bist,
+ msm_mux_pll_bypassnl,
+ msm_mux_pll_reset,
+ msm_mux_pri_mi2s,
+ msm_mux_pri_mi2s_ws,
+ msm_mux_prng_rosc,
+ msm_mux_qdss_cti,
+ msm_mux_qdss,
+ msm_mux_qlink_enable,
+ msm_mux_qlink_request,
+ msm_mux_qspi_clk,
+ msm_mux_qspi_cs,
+ msm_mux_qspi_data,
+ msm_mux_qua_mi2s,
+ msm_mux_qup0,
+ msm_mux_qup1,
+ msm_mux_qup10,
+ msm_mux_qup11,
+ msm_mux_qup12,
+ msm_mux_qup13,
+ msm_mux_qup14,
+ msm_mux_qup15,
+ msm_mux_qup2,
+ msm_mux_qup3,
+ msm_mux_qup4,
+ msm_mux_qup5,
+ msm_mux_qup6,
+ msm_mux_qup7,
+ msm_mux_qup8,
+ msm_mux_qup9,
+ msm_mux_qup_l4,
+ msm_mux_qup_l5,
+ msm_mux_qup_l6,
+ msm_mux_sd_write,
+ msm_mux_sdc4_clk,
+ msm_mux_sdc4_cmd,
+ msm_mux_sdc4_data,
+ msm_mux_sec_mi2s,
+ msm_mux_sp_cmu,
+ msm_mux_spkr_i2s,
+ msm_mux_ter_mi2s,
+ msm_mux_tgu_ch0,
+ msm_mux_tgu_ch1,
+ msm_mux_tgu_ch2,
+ msm_mux_tgu_ch3,
+ msm_mux_tsense_pwm1,
+ msm_mux_tsense_pwm2,
+ msm_mux_tsif1_clk,
+ msm_mux_tsif1_data,
+ msm_mux_tsif1_en,
+ msm_mux_tsif1_error,
+ msm_mux_tsif1_sync,
+ msm_mux_tsif2_clk,
+ msm_mux_tsif2_data,
+ msm_mux_tsif2_en,
+ msm_mux_tsif2_error,
+ msm_mux_tsif2_sync,
+ msm_mux_uim1_clk,
+ msm_mux_uim1_data,
+ msm_mux_uim1_present,
+ msm_mux_uim1_reset,
+ msm_mux_uim2_clk,
+ msm_mux_uim2_data,
+ msm_mux_uim2_present,
+ msm_mux_uim2_reset,
+ msm_mux_uim_batt,
+ msm_mux_usb_phy,
+ msm_mux_vfr_1,
+ msm_mux_vsense_trigger,
+ msm_mux_wlan1_adc0,
+ msm_mux_wlan1_adc1,
+ msm_mux_wlan2_adc0,
+ msm_mux_wlan2_adc1,
+ msm_mux__,
+};
+
+static const char * const ddr_pxi3_groups[] = {
+ "gpio12", "gpio13",
+};
+static const char * const cam_mclk_groups[] = {
+ "gpio13", "gpio14", "gpio15", "gpio16",
+};
+static const char * const pll_bypassnl_groups[] = {
+ "gpio13",
+};
+static const char * const qdss_groups[] = {
+ "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
+ "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26",
+ "gpio27", "gpio28", "gpio29", "gpio30", "gpio41", "gpio42", "gpio43",
+ "gpio44", "gpio75", "gpio76", "gpio77", "gpio79", "gpio80", "gpio93",
+ "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
+ "gpio123", "gpio124",
+};
+static const char * const pll_reset_groups[] = {
+ "gpio14",
+};
+static const char * const cci_i2c_groups[] = {
+ "gpio17", "gpio18", "gpio19", "gpio20",
+};
+static const char * const qup1_groups[] = {
+ "gpio17", "gpio18", "gpio19", "gpio20",
+};
+static const char * const cci_timer0_groups[] = {
+ "gpio21",
+};
+static const char * const gcc_gp2_groups[] = {
+ "gpio21", "gpio58",
+};
+static const char * const cci_timer1_groups[] = {
+ "gpio22",
+};
+static const char * const gcc_gp3_groups[] = {
+ "gpio22", "gpio59",
+};
+static const char * const cci_timer2_groups[] = {
+ "gpio23",
+};
+static const char * const cci_timer3_groups[] = {
+ "gpio24",
+};
+static const char * const cci_async_groups[] = {
+ "gpio24", "gpio25", "gpio26",
+};
+static const char * const cci_timer4_groups[] = {
+ "gpio25",
+};
+static const char * const qup2_groups[] = {
+ "gpio27", "gpio28", "gpio29", "gpio30",
+};
+static const char * const phase_flag_groups[] = {
+ "gpio29", "gpio30", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
+ "gpio64", "gpio74", "gpio75", "gpio76", "gpio77", "gpio89", "gpio90",
+ "gpio96", "gpio99", "gpio100", "gpio103", "gpio137", "gpio138",
+ "gpio139", "gpio140", "gpio141", "gpio142", "gpio143",
+};
+static const char * const qup11_groups[] = {
+ "gpio31", "gpio32", "gpio33", "gpio34",
+};
+static const char * const qup14_groups[] = {
+ "gpio31", "gpio32", "gpio33", "gpio34",
+};
+static const char * const pci_e0_groups[] = {
+ "gpio35", "gpio36",
+};
+static const char * const jitter_bist_groups[] = {
+ "gpio35",
+};
+static const char * const pll_bist_groups[] = {
+ "gpio36",
+};
+static const char * const atest_tsens_groups[] = {
+ "gpio36",
+};
+static const char * const agera_pll_groups[] = {
+ "gpio37",
+};
+static const char * const usb_phy_groups[] = {
+ "gpio38",
+};
+static const char * const lpass_slimbus_groups[] = {
+ "gpio39", "gpio70", "gpio71", "gpio72",
+};
+static const char * const sd_write_groups[] = {
+ "gpio40",
+};
+static const char * const tsif1_error_groups[] = {
+ "gpio40",
+};
+static const char * const qup3_groups[] = {
+ "gpio41", "gpio42", "gpio43", "gpio44",
+};
+static const char * const qup6_groups[] = {
+ "gpio45", "gpio46", "gpio47", "gpio48",
+};
+static const char * const qup12_groups[] = {
+ "gpio49", "gpio50", "gpio51", "gpio52",
+};
+static const char * const qup10_groups[] = {
+ "gpio53", "gpio54", "gpio55", "gpio56",
+};
+static const char * const qua_mi2s_groups[] = {
+ "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
+};
+static const char * const gcc_gp1_groups[] = {
+ "gpio57", "gpio78",
+};
+static const char * const cri_trng0_groups[] = {
+ "gpio60",
+};
+static const char * const cri_trng1_groups[] = {
+ "gpio61",
+};
+static const char * const cri_trng_groups[] = {
+ "gpio62",
+};
+static const char * const pri_mi2s_groups[] = {
+ "gpio64", "gpio65", "gpio67", "gpio68",
+};
+static const char * const sp_cmu_groups[] = {
+ "gpio64",
+};
+static const char * const qup8_groups[] = {
+ "gpio65", "gpio66", "gpio67", "gpio68",
+};
+static const char * const pri_mi2s_ws_groups[] = {
+ "gpio66",
+};
+static const char * const spkr_i2s_groups[] = {
+ "gpio69", "gpio70", "gpio71", "gpio72",
+};
+static const char * const audio_ref_groups[] = {
+ "gpio69",
+};
+static const char * const tsense_pwm1_groups[] = {
+ "gpio71",
+};
+static const char * const tsense_pwm2_groups[] = {
+ "gpio71",
+};
+static const char * const btfm_slimbus_groups[] = {
+ "gpio73", "gpio74",
+};
+static const char * const atest_usb2_groups[] = {
+ "gpio73",
+};
+static const char * const ter_mi2s_groups[] = {
+ "gpio74", "gpio75", "gpio76", "gpio77", "gpio78",
+};
+static const char * const atest_usb23_groups[] = {
+ "gpio74",
+};
+static const char * const atest_usb22_groups[] = {
+ "gpio75",
+};
+static const char * const atest_usb21_groups[] = {
+ "gpio76",
+};
+static const char * const atest_usb20_groups[] = {
+ "gpio77",
+};
+static const char * const sec_mi2s_groups[] = {
+ "gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
+};
+static const char * const qup15_groups[] = {
+ "gpio81", "gpio82", "gpio83", "gpio84",
+};
+static const char * const qup5_groups[] = {
+ "gpio85", "gpio86", "gpio87", "gpio88",
+};
+static const char * const tsif1_clk_groups[] = {
+ "gpio89",
+};
+static const char * const qup4_groups[] = {
+ "gpio89", "gpio90", "gpio91", "gpio92",
+};
+static const char * const qspi_cs_groups[] = {
+ "gpio89", "gpio90",
+};
+static const char * const tgu_ch3_groups[] = {
+ "gpio89",
+};
+static const char * const tsif1_en_groups[] = {
+ "gpio90",
+};
+static const char * const mdp_vsync0_groups[] = {
+ "gpio90",
+};
+static const char * const mdp_vsync1_groups[] = {
+ "gpio90",
+};
+static const char * const mdp_vsync2_groups[] = {
+ "gpio90",
+};
+static const char * const mdp_vsync3_groups[] = {
+ "gpio90",
+};
+static const char * const tgu_ch0_groups[] = {
+ "gpio90",
+};
+static const char * const tsif1_data_groups[] = {
+ "gpio91",
+};
+static const char * const sdc4_cmd_groups[] = {
+ "gpio91",
+};
+static const char * const qspi_data_groups[] = {
+ "gpio91", "gpio92", "gpio93", "gpio94",
+};
+static const char * const tgu_ch1_groups[] = {
+ "gpio91",
+};
+static const char * const tsif2_error_groups[] = {
+ "gpio92",
+};
+static const char * const sdc4_data_groups[] = {
+ "gpio92",
+ "gpio94",
+ "gpio95",
+ "gpio96",
+};
+static const char * const vfr_1_groups[] = {
+ "gpio92",
+};
+static const char * const tgu_ch2_groups[] = {
+ "gpio92",
+};
+static const char * const tsif2_clk_groups[] = {
+ "gpio93",
+};
+static const char * const sdc4_clk_groups[] = {
+ "gpio93",
+};
+static const char * const qup7_groups[] = {
+ "gpio93", "gpio94", "gpio95", "gpio96",
+};
+static const char * const tsif2_en_groups[] = {
+ "gpio94",
+};
+static const char * const tsif2_data_groups[] = {
+ "gpio95",
+};
+static const char * const qspi_clk_groups[] = {
+ "gpio95",
+};
+static const char * const tsif2_sync_groups[] = {
+ "gpio96",
+};
+static const char * const ldo_en_groups[] = {
+ "gpio97",
+};
+static const char * const ldo_update_groups[] = {
+ "gpio98",
+};
+static const char * const pci_e1_groups[] = {
+ "gpio102", "gpio103",
+};
+static const char * const prng_rosc_groups[] = {
+ "gpio102",
+};
+static const char * const uim2_data_groups[] = {
+ "gpio105",
+};
+static const char * const qup13_groups[] = {
+ "gpio105", "gpio106", "gpio107", "gpio108",
+};
+static const char * const uim2_clk_groups[] = {
+ "gpio106",
+};
+static const char * const uim2_reset_groups[] = {
+ "gpio107",
+};
+static const char * const uim2_present_groups[] = {
+ "gpio108",
+};
+static const char * const uim1_data_groups[] = {
+ "gpio109",
+};
+static const char * const uim1_clk_groups[] = {
+ "gpio110",
+};
+static const char * const uim1_reset_groups[] = {
+ "gpio111",
+};
+static const char * const uim1_present_groups[] = {
+ "gpio112",
+};
+static const char * const uim_batt_groups[] = {
+ "gpio113",
+};
+static const char * const edp_hot_groups[] = {
+ "gpio113",
+};
+static const char * const nav_pps_groups[] = {
+ "gpio114", "gpio114", "gpio115", "gpio115", "gpio128", "gpio128",
+ "gpio129", "gpio129", "gpio143", "gpio143",
+};
+static const char * const atest_char_groups[] = {
+ "gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
+};
+static const char * const adsp_ext_groups[] = {
+ "gpio118",
+};
+static const char * const qlink_request_groups[] = {
+ "gpio130",
+};
+static const char * const qlink_enable_groups[] = {
+ "gpio131",
+};
+static const char * const pa_indicator_groups[] = {
+ "gpio135",
+};
+static const char * const mss_lte_groups[] = {
+ "gpio144", "gpio145",
+};
+static const char * const qup0_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3",
+};
+static const char * const gpio_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
+ "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
+ "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
+ "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
+ "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
+ "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
+ "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
+ "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
+ "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
+ "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
+ "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
+ "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
+ "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
+ "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
+ "gpio147", "gpio148", "gpio149",
+};
+static const char * const qup9_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7",
+};
+static const char * const qdss_cti_groups[] = {
+ "gpio4", "gpio5", "gpio51", "gpio52", "gpio62", "gpio63", "gpio90",
+ "gpio91",
+};
+static const char * const ddr_pxi0_groups[] = {
+ "gpio6", "gpio7",
+};
+static const char * const ddr_bist_groups[] = {
+ "gpio7", "gpio8", "gpio9", "gpio10",
+};
+static const char * const atest_tsens2_groups[] = {
+ "gpio7",
+};
+static const char * const vsense_trigger_groups[] = {
+ "gpio7",
+};
+static const char * const atest_usb1_groups[] = {
+ "gpio7",
+};
+static const char * const qup_l4_groups[] = {
+ "gpio8", "gpio35", "gpio105", "gpio123",
+};
+static const char * const wlan1_adc1_groups[] = {
+ "gpio8",
+};
+static const char * const atest_usb13_groups[] = {
+ "gpio8",
+};
+static const char * const ddr_pxi1_groups[] = {
+ "gpio8", "gpio9",
+};
+static const char * const qup_l5_groups[] = {
+ "gpio9", "gpio36", "gpio106", "gpio124",
+};
+static const char * const wlan1_adc0_groups[] = {
+ "gpio9",
+};
+static const char * const atest_usb12_groups[] = {
+ "gpio9",
+};
+static const char * const mdp_vsync_groups[] = {
+ "gpio10", "gpio11", "gpio12", "gpio97", "gpio98",
+};
+static const char * const qup_l6_groups[] = {
+ "gpio10", "gpio37", "gpio107", "gpio125",
+};
+static const char * const wlan2_adc1_groups[] = {
+ "gpio10",
+};
+static const char * const atest_usb11_groups[] = {
+ "gpio10",
+};
+static const char * const ddr_pxi2_groups[] = {
+ "gpio10", "gpio11",
+};
+static const char * const edp_lcd_groups[] = {
+ "gpio11",
+};
+static const char * const dbg_out_groups[] = {
+ "gpio11",
+};
+static const char * const wlan2_adc0_groups[] = {
+ "gpio11",
+};
+static const char * const atest_usb10_groups[] = {
+ "gpio11",
+};
+static const char * const m_voc_groups[] = {
+ "gpio12",
+};
+static const char * const tsif1_sync_groups[] = {
+ "gpio12",
+};
+
+static const struct msm_function sdm845_functions[] = {
+ FUNCTION(gpio),
+ FUNCTION(adsp_ext),
+ FUNCTION(agera_pll),
+ FUNCTION(atest_char),
+ FUNCTION(atest_tsens),
+ FUNCTION(atest_tsens2),
+ FUNCTION(atest_usb1),
+ FUNCTION(atest_usb10),
+ FUNCTION(atest_usb11),
+ FUNCTION(atest_usb12),
+ FUNCTION(atest_usb13),
+ FUNCTION(atest_usb2),
+ FUNCTION(atest_usb20),
+ FUNCTION(atest_usb21),
+ FUNCTION(atest_usb22),
+ FUNCTION(atest_usb23),
+ FUNCTION(audio_ref),
+ FUNCTION(btfm_slimbus),
+ FUNCTION(cam_mclk),
+ FUNCTION(cci_async),
+ FUNCTION(cci_i2c),
+ FUNCTION(cci_timer0),
+ FUNCTION(cci_timer1),
+ FUNCTION(cci_timer2),
+ FUNCTION(cci_timer3),
+ FUNCTION(cci_timer4),
+ FUNCTION(cri_trng),
+ FUNCTION(cri_trng0),
+ FUNCTION(cri_trng1),
+ FUNCTION(dbg_out),
+ FUNCTION(ddr_bist),
+ FUNCTION(ddr_pxi0),
+ FUNCTION(ddr_pxi1),
+ FUNCTION(ddr_pxi2),
+ FUNCTION(ddr_pxi3),
+ FUNCTION(edp_hot),
+ FUNCTION(edp_lcd),
+ FUNCTION(gcc_gp1),
+ FUNCTION(gcc_gp2),
+ FUNCTION(gcc_gp3),
+ FUNCTION(jitter_bist),
+ FUNCTION(ldo_en),
+ FUNCTION(ldo_update),
+ FUNCTION(lpass_slimbus),
+ FUNCTION(m_voc),
+ FUNCTION(mdp_vsync),
+ FUNCTION(mdp_vsync0),
+ FUNCTION(mdp_vsync1),
+ FUNCTION(mdp_vsync2),
+ FUNCTION(mdp_vsync3),
+ FUNCTION(mss_lte),
+ FUNCTION(nav_pps),
+ FUNCTION(pa_indicator),
+ FUNCTION(pci_e0),
+ FUNCTION(pci_e1),
+ FUNCTION(phase_flag),
+ FUNCTION(pll_bist),
+ FUNCTION(pll_bypassnl),
+ FUNCTION(pll_reset),
+ FUNCTION(pri_mi2s),
+ FUNCTION(pri_mi2s_ws),
+ FUNCTION(prng_rosc),
+ FUNCTION(qdss_cti),
+ FUNCTION(qdss),
+ FUNCTION(qlink_enable),
+ FUNCTION(qlink_request),
+ FUNCTION(qspi_clk),
+ FUNCTION(qspi_cs),
+ FUNCTION(qspi_data),
+ FUNCTION(qua_mi2s),
+ FUNCTION(qup0),
+ FUNCTION(qup1),
+ FUNCTION(qup10),
+ FUNCTION(qup11),
+ FUNCTION(qup12),
+ FUNCTION(qup13),
+ FUNCTION(qup14),
+ FUNCTION(qup15),
+ FUNCTION(qup2),
+ FUNCTION(qup3),
+ FUNCTION(qup4),
+ FUNCTION(qup5),
+ FUNCTION(qup6),
+ FUNCTION(qup7),
+ FUNCTION(qup8),
+ FUNCTION(qup9),
+ FUNCTION(qup_l4),
+ FUNCTION(qup_l5),
+ FUNCTION(qup_l6),
+ FUNCTION(sd_write),
+ FUNCTION(sdc4_clk),
+ FUNCTION(sdc4_cmd),
+ FUNCTION(sdc4_data),
+ FUNCTION(sec_mi2s),
+ FUNCTION(sp_cmu),
+ FUNCTION(spkr_i2s),
+ FUNCTION(ter_mi2s),
+ FUNCTION(tgu_ch0),
+ FUNCTION(tgu_ch1),
+ FUNCTION(tgu_ch2),
+ FUNCTION(tgu_ch3),
+ FUNCTION(tsense_pwm1),
+ FUNCTION(tsense_pwm2),
+ FUNCTION(tsif1_clk),
+ FUNCTION(tsif1_data),
+ FUNCTION(tsif1_en),
+ FUNCTION(tsif1_error),
+ FUNCTION(tsif1_sync),
+ FUNCTION(tsif2_clk),
+ FUNCTION(tsif2_data),
+ FUNCTION(tsif2_en),
+ FUNCTION(tsif2_error),
+ FUNCTION(tsif2_sync),
+ FUNCTION(uim1_clk),
+ FUNCTION(uim1_data),
+ FUNCTION(uim1_present),
+ FUNCTION(uim1_reset),
+ FUNCTION(uim2_clk),
+ FUNCTION(uim2_data),
+ FUNCTION(uim2_present),
+ FUNCTION(uim2_reset),
+ FUNCTION(uim_batt),
+ FUNCTION(usb_phy),
+ FUNCTION(vfr_1),
+ FUNCTION(vsense_trigger),
+ FUNCTION(wlan1_adc0),
+ FUNCTION(wlan1_adc1),
+ FUNCTION(wlan2_adc0),
+ FUNCTION(wlan2_adc1),
+};
+
+/* Every pin is maintained as a single group, and missing or non-existing pin
+ * would be maintained as dummy group to synchronize pin group index with
+ * pin descriptor registered with pinctrl core.
+ * Clients would not be able to request these dummy pin groups.
+ */
+static const struct msm_pingroup sdm845_groups[] = {
+ PINGROUP(0, EAST, qup0, _, _, _, _, _, _, _, _, _),
+ PINGROUP(1, EAST, qup0, _, _, _, _, _, _, _, _, _),
+ PINGROUP(2, EAST, qup0, _, _, _, _, _, _, _, _, _),
+ PINGROUP(3, EAST, qup0, _, _, _, _, _, _, _, _, _),
+ PINGROUP(4, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _, _),
+ PINGROUP(5, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _, _),
+ PINGROUP(6, NORTH, qup9, _, ddr_pxi0, _, _, _, _, _, _, _),
+ PINGROUP(7, NORTH, qup9, ddr_bist, _, atest_tsens2, vsense_trigger, atest_usb1, ddr_pxi0, _, _, _),
+ PINGROUP(8, EAST, qup_l4, _, ddr_bist, _, _, wlan1_adc1, atest_usb13, ddr_pxi1, _, _),
+ PINGROUP(9, EAST, qup_l5, ddr_bist, _, wlan1_adc0, atest_usb12, ddr_pxi1, _, _, _, _),
+ PINGROUP(10, EAST, mdp_vsync, qup_l6, ddr_bist, wlan2_adc1, atest_usb11, ddr_pxi2, _, _, _, _),
+ PINGROUP(11, EAST, mdp_vsync, edp_lcd, dbg_out, wlan2_adc0, atest_usb10, ddr_pxi2, _, _, _, _),
+ PINGROUP(12, SOUTH, mdp_vsync, m_voc, tsif1_sync, ddr_pxi3, _, _, _, _, _, _),
+ PINGROUP(13, SOUTH, cam_mclk, pll_bypassnl, qdss, ddr_pxi3, _, _, _, _, _, _),
+ PINGROUP(14, SOUTH, cam_mclk, pll_reset, qdss, _, _, _, _, _, _, _),
+ PINGROUP(15, SOUTH, cam_mclk, qdss, _, _, _, _, _, _, _, _),
+ PINGROUP(16, SOUTH, cam_mclk, qdss, _, _, _, _, _, _, _, _),
+ PINGROUP(17, SOUTH, cci_i2c, qup1, qdss, _, _, _, _, _, _, _),
+ PINGROUP(18, SOUTH, cci_i2c, qup1, _, qdss, _, _, _, _, _, _),
+ PINGROUP(19, SOUTH, cci_i2c, qup1, _, qdss, _, _, _, _, _, _),
+ PINGROUP(20, SOUTH, cci_i2c, qup1, _, qdss, _, _, _, _, _, _),
+ PINGROUP(21, SOUTH, cci_timer0, gcc_gp2, qdss, _, _, _, _, _, _, _),
+ PINGROUP(22, SOUTH, cci_timer1, gcc_gp3, qdss, _, _, _, _, _, _, _),
+ PINGROUP(23, SOUTH, cci_timer2, qdss, _, _, _, _, _, _, _, _),
+ PINGROUP(24, SOUTH, cci_timer3, cci_async, qdss, _, _, _, _, _, _, _),
+ PINGROUP(25, SOUTH, cci_timer4, cci_async, qdss, _, _, _, _, _, _, _),
+ PINGROUP(26, SOUTH, cci_async, qdss, _, _, _, _, _, _, _, _),
+ PINGROUP(27, EAST, qup2, qdss, _, _, _, _, _, _, _, _),
+ PINGROUP(28, EAST, qup2, qdss, _, _, _, _, _, _, _, _),
+ PINGROUP(29, EAST, qup2, _, phase_flag, qdss, _, _, _, _, _, _),
+ PINGROUP(30, EAST, qup2, phase_flag, qdss, _, _, _, _, _, _, _),
+ PINGROUP(31, NORTH, qup11, qup14, _, _, _, _, _, _, _, _),
+ PINGROUP(32, NORTH, qup11, qup14, _, _, _, _, _, _, _, _),
+ PINGROUP(33, NORTH, qup11, qup14, _, _, _, _, _, _, _, _),
+ PINGROUP(34, NORTH, qup11, qup14, _, _, _, _, _, _, _, _),
+ PINGROUP(35, SOUTH, pci_e0, qup_l4, jitter_bist, _, _, _, _, _, _, _),
+ PINGROUP(36, SOUTH, pci_e0, qup_l5, pll_bist, _, atest_tsens, _, _, _, _, _),
+ PINGROUP(37, SOUTH, qup_l6, agera_pll, _, _, _, _, _, _, _, _),
+ PINGROUP(38, NORTH, usb_phy, _, _, _, _, _, _, _, _, _),
+ PINGROUP(39, EAST, lpass_slimbus, _, _, _, _, _, _, _, _, _),
+ PINGROUP(40, SOUTH, sd_write, tsif1_error, _, _, _, _, _, _, _, _),
+ PINGROUP(41, EAST, qup3, _, qdss, _, _, _, _, _, _, _),
+ PINGROUP(42, EAST, qup3, _, qdss, _, _, _, _, _, _, _),
+ PINGROUP(43, EAST, qup3, _, qdss, _, _, _, _, _, _, _),
+ PINGROUP(44, EAST, qup3, _, qdss, _, _, _, _, _, _, _),
+ PINGROUP(45, EAST, qup6, _, _, _, _, _, _, _, _, _),
+ PINGROUP(46, EAST, qup6, _, _, _, _, _, _, _, _, _),
+ PINGROUP(47, EAST, qup6, _, _, _, _, _, _, _, _, _),
+ PINGROUP(48, EAST, qup6, _, _, _, _, _, _, _, _, _),
+ PINGROUP(49, NORTH, qup12, _, _, _, _, _, _, _, _, _),
+ PINGROUP(50, NORTH, qup12, _, _, _, _, _, _, _, _, _),
+ PINGROUP(51, NORTH, qup12, qdss_cti, _, _, _, _, _, _, _, _),
+ PINGROUP(52, NORTH, qup12, phase_flag, qdss_cti, _, _, _, _, _, _, _),
+ PINGROUP(53, NORTH, qup10, phase_flag, _, _, _, _, _, _, _, _),
+ PINGROUP(54, NORTH, qup10, _, phase_flag, _, _, _, _, _, _, _),
+ PINGROUP(55, NORTH, qup10, phase_flag, _, _, _, _, _, _, _, _),
+ PINGROUP(56, NORTH, qup10, phase_flag, _, _, _, _, _, _, _, _),
+ PINGROUP(57, NORTH, qua_mi2s, gcc_gp1, phase_flag, _, _, _, _, _, _, _),
+ PINGROUP(58, NORTH, qua_mi2s, gcc_gp2, phase_flag, _, _, _, _, _, _, _),
+ PINGROUP(59, NORTH, qua_mi2s, gcc_gp3, phase_flag, _, _, _, _, _, _, _),
+ PINGROUP(60, NORTH, qua_mi2s, cri_trng0, phase_flag, _, _, _, _, _, _, _),
+ PINGROUP(61, NORTH, qua_mi2s, cri_trng1, phase_flag, _, _, _, _, _, _, _),
+ PINGROUP(62, NORTH, qua_mi2s, cri_trng, phase_flag, qdss_cti, _, _, _, _, _, _),
+ PINGROUP(63, NORTH, qua_mi2s, _, phase_flag, qdss_cti, _, _, _, _, _, _),
+ PINGROUP(64, NORTH, pri_mi2s, sp_cmu, phase_flag, _, _, _, _, _, _, _),
+ PINGROUP(65, NORTH, pri_mi2s, qup8, _, _, _, _, _, _, _, _),
+ PINGROUP(66, NORTH, pri_mi2s_ws, qup8, _, _, _, _, _, _, _, _),
+ PINGROUP(67, NORTH, pri_mi2s, qup8, _, _, _, _, _, _, _, _),
+ PINGROUP(68, NORTH, pri_mi2s, qup8, _, _, _, _, _, _, _, _),
+ PINGROUP(69, EAST, spkr_i2s, audio_ref, _, _, _, _, _, _, _, _),
+ PINGROUP(70, EAST, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _, _),
+ PINGROUP(71, EAST, lpass_slimbus, spkr_i2s, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _),
+ PINGROUP(72, EAST, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _, _),
+ PINGROUP(73, EAST, btfm_slimbus, atest_usb2, _, _, _, _, _, _, _, _),
+ PINGROUP(74, EAST, btfm_slimbus, ter_mi2s, phase_flag, atest_usb23, _, _, _, _, _, _),
+ PINGROUP(75, EAST, ter_mi2s, phase_flag, qdss, atest_usb22, _, _, _, _, _, _),
+ PINGROUP(76, EAST, ter_mi2s, phase_flag, qdss, atest_usb21, _, _, _, _, _, _),
+ PINGROUP(77, EAST, ter_mi2s, phase_flag, qdss, atest_usb20, _, _, _, _, _, _),
+ PINGROUP(78, EAST, ter_mi2s, gcc_gp1, _, _, _, _, _, _, _, _),
+ PINGROUP(79, NORTH, sec_mi2s, _, _, qdss, _, _, _, _, _, _),
+ PINGROUP(80, NORTH, sec_mi2s, _, qdss, _, _, _, _, _, _, _),
+ PINGROUP(81, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _, _),
+ PINGROUP(82, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _, _),
+ PINGROUP(83, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _, _),
+ PINGROUP(84, NORTH, qup15, _, _, _, _, _, _, _, _, _),
+ PINGROUP(85, EAST, qup5, _, _, _, _, _, _, _, _, _),
+ PINGROUP(86, EAST, qup5, _, _, _, _, _, _, _, _, _),
+ PINGROUP(87, EAST, qup5, _, _, _, _, _, _, _, _, _),
+ PINGROUP(88, EAST, qup5, _, _, _, _, _, _, _, _, _),
+ PINGROUP(89, SOUTH, tsif1_clk, qup4, qspi_cs, tgu_ch3, phase_flag, _, _, _, _, _),
+ PINGROUP(90, SOUTH, tsif1_en, mdp_vsync0, qup4, qspi_cs, mdp_vsync1,
+ mdp_vsync2, mdp_vsync3, tgu_ch0, phase_flag, qdss_cti),
+ PINGROUP(91, SOUTH, tsif1_data, sdc4_cmd, qup4, qspi_data, tgu_ch1, _, qdss_cti, _, _, _),
+ PINGROUP(92, SOUTH, tsif2_error, sdc4_data, qup4, qspi_data, vfr_1, tgu_ch2, _, _, _, _),
+ PINGROUP(93, SOUTH, tsif2_clk, sdc4_clk, qup7, qspi_data, _, qdss, _, _, _, _),
+ PINGROUP(94, SOUTH, tsif2_en, sdc4_data, qup7, qspi_data, _, _, _, _, _, _),
+ PINGROUP(95, SOUTH, tsif2_data, sdc4_data, qup7, qspi_clk, _, _, _, _, _, _),
+ PINGROUP(96, SOUTH, tsif2_sync, sdc4_data, qup7, phase_flag, _, _, _, _, _, _),
+ PINGROUP(97, NORTH, _, _, mdp_vsync, ldo_en, _, _, _, _, _, _),
+ PINGROUP(98, NORTH, _, mdp_vsync, ldo_update, _, _, _, _, _, _, _),
+ PINGROUP(99, NORTH, phase_flag, _, _, _, _, _, _, _, _, _),
+ PINGROUP(100, NORTH, phase_flag, _, _, _, _, _, _, _, _, _),
+ PINGROUP(101, NORTH, _, _, _, _, _, _, _, _, _, _),
+ PINGROUP(102, NORTH, pci_e1, prng_rosc, _, _, _, _, _, _, _, _),
+ PINGROUP(103, NORTH, pci_e1, phase_flag, _, _, _, _, _, _, _, _),
+ PINGROUP(104, NORTH, _, _, _, _, _, _, _, _, _, _),
+ PINGROUP(105, NORTH, uim2_data, qup13, qup_l4, _, _, _, _, _, _, _),
+ PINGROUP(106, NORTH, uim2_clk, qup13, qup_l5, _, _, _, _, _, _, _),
+ PINGROUP(107, NORTH, uim2_reset, qup13, qup_l6, _, _, _, _, _, _, _),
+ PINGROUP(108, NORTH, uim2_present, qup13, _, _, _, _, _, _, _, _),
+ PINGROUP(109, NORTH, uim1_data, _, _, _, _, _, _, _, _, _),
+ PINGROUP(110, NORTH, uim1_clk, _, _, _, _, _, _, _, _, _),
+ PINGROUP(111, NORTH, uim1_reset, _, _, _, _, _, _, _, _, _),
+ PINGROUP(112, NORTH, uim1_present, _, _, _, _, _, _, _, _, _),
+ PINGROUP(113, NORTH, uim_batt, edp_hot, _, _, _, _, _, _, _, _),
+ PINGROUP(114, NORTH, _, nav_pps, nav_pps, _, _, _, _, _, _, _),
+ PINGROUP(115, NORTH, _, nav_pps, nav_pps, _, _, _, _, _, _, _),
+ PINGROUP(116, NORTH, _, _, _, _, _, _, _, _, _, _),
+ PINGROUP(117, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _),
+ PINGROUP(118, NORTH, adsp_ext, _, qdss, atest_char, _, _, _, _, _, _),
+ PINGROUP(119, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _),
+ PINGROUP(120, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _),
+ PINGROUP(121, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _),
+ PINGROUP(122, EAST, _, qdss, _, _, _, _, _, _, _, _),
+ PINGROUP(123, EAST, qup_l4, _, qdss, _, _, _, _, _, _, _),
+ PINGROUP(124, EAST, qup_l5, _, qdss, _, _, _, _, _, _, _),
+ PINGROUP(125, EAST, qup_l6, _, _, _, _, _, _, _, _, _),
+ PINGROUP(126, EAST, _, _, _, _, _, _, _, _, _, _),
+ PINGROUP(127, NORTH, _, _, _, _, _, _, _, _, _, _),
+ PINGROUP(128, NORTH, nav_pps, nav_pps, _, _, _, _, _, _, _, _),
+ PINGROUP(129, NORTH, nav_pps, nav_pps, _, _, _, _, _, _, _, _),
+ PINGROUP(130, NORTH, qlink_request, _, _, _, _, _, _, _, _, _),
+ PINGROUP(131, NORTH, qlink_enable, _, _, _, _, _, _, _, _, _),
+ PINGROUP(132, NORTH, _, _, _, _, _, _, _, _, _, _),
+ PINGROUP(133, NORTH, _, _, _, _, _, _, _, _, _, _),
+ PINGROUP(134, NORTH, _, _, _, _, _, _, _, _, _, _),
+ PINGROUP(135, NORTH, _, pa_indicator, _, _, _, _, _, _, _, _),
+ PINGROUP(136, NORTH, _, _, _, _, _, _, _, _, _, _),
+ PINGROUP(137, NORTH, _, _, phase_flag, _, _, _, _, _, _, _),
+ PINGROUP(138, NORTH, _, _, phase_flag, _, _, _, _, _, _, _),
+ PINGROUP(139, NORTH, _, phase_flag, _, _, _, _, _, _, _, _),
+ PINGROUP(140, NORTH, _, _, phase_flag, _, _, _, _, _, _, _),
+ PINGROUP(141, NORTH, _, phase_flag, _, _, _, _, _, _, _, _),
+ PINGROUP(142, NORTH, _, phase_flag, _, _, _, _, _, _, _, _),
+ PINGROUP(143, NORTH, _, nav_pps, nav_pps, _, phase_flag, _, _, _, _, _),
+ PINGROUP(144, NORTH, mss_lte, _, _, _, _, _, _, _, _, _),
+ PINGROUP(145, NORTH, mss_lte, _, _, _, _, _, _, _, _, _),
+ PINGROUP(146, NORTH, _, _, _, _, _, _, _, _, _, _),
+ PINGROUP(147, NORTH, _, _, _, _, _, _, _, _, _, _),
+ PINGROUP(148, NORTH, _, _, _, _, _, _, _, _, _, _),
+ PINGROUP(149, NORTH, _, _, _, _, _, _, _, _, _, _),
+ SDC_QDSD_PINGROUP(sdc2_clk, 0x99a000, 14, 6),
+ SDC_QDSD_PINGROUP(sdc2_cmd, 0x99a000, 11, 3),
+ SDC_QDSD_PINGROUP(sdc2_data, 0x99a000, 9, 0),
+ UFS_RESET(ufs_reset, 0x99f000),
+};
+
+static const struct msm_pinctrl_soc_data sdm845_pinctrl = {
+ .pins = sdm845_pins,
+ .npins = ARRAY_SIZE(sdm845_pins),
+ .functions = sdm845_functions,
+ .nfunctions = ARRAY_SIZE(sdm845_functions),
+ .groups = sdm845_groups,
+ .ngroups = ARRAY_SIZE(sdm845_groups),
+ .ngpios = 150,
+};
+
+static int sdm845_pinctrl_probe(struct platform_device *pdev)
+{
+ return msm_pinctrl_probe(pdev, &sdm845_pinctrl);
+}
+
+static const struct of_device_id sdm845_pinctrl_of_match[] = {
+ { .compatible = "qcom,sdm845-pinctrl", },
+ { },
+};
+
+static struct platform_driver sdm845_pinctrl_driver = {
+ .driver = {
+ .name = "sdm845-pinctrl",
+ .of_match_table = sdm845_pinctrl_of_match,
+ },
+ .probe = sdm845_pinctrl_probe,
+ .remove = msm_pinctrl_remove,
+};
+
+static int __init sdm845_pinctrl_init(void)
+{
+ return platform_driver_register(&sdm845_pinctrl_driver);
+}
+arch_initcall(sdm845_pinctrl_init);
+
+static void __exit sdm845_pinctrl_exit(void)
+{
+ platform_driver_unregister(&sdm845_pinctrl_driver);
+}
+module_exit(sdm845_pinctrl_exit);
+
+MODULE_DESCRIPTION("QTI sdm845 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, sdm845_pinctrl_of_match);
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index 4ed3761418f9..c11b789ec583 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -89,11 +89,21 @@ config PINCTRL_PFC_R8A7796
depends on ARCH_R8A7796
select PINCTRL_SH_PFC
+config PINCTRL_PFC_R8A77965
+ def_bool y
+ depends on ARCH_R8A77965
+ select PINCTRL_SH_PFC
+
config PINCTRL_PFC_R8A77970
def_bool y
depends on ARCH_R8A77970
select PINCTRL_SH_PFC
+config PINCTRL_PFC_R8A77980
+ def_bool y
+ depends on ARCH_R8A77980
+ select PINCTRL_SH_PFC
+
config PINCTRL_PFC_R8A77995
def_bool y
depends on ARCH_R8A77995
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index 22e758ce1fc2..463775f28cf1 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -16,7 +16,9 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795-es1.o
obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
+obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o
obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
+obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o
obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index e9eb7a7c6fac..74861b7b5b0d 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -557,12 +557,24 @@ static const struct of_device_id sh_pfc_of_table[] = {
.data = &r8a7796_pinmux_info,
},
#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A77965
+ {
+ .compatible = "renesas,pfc-r8a77965",
+ .data = &r8a77965_pinmux_info,
+ },
+#endif
#ifdef CONFIG_PINCTRL_PFC_R8A77970
{
.compatible = "renesas,pfc-r8a77970",
.data = &r8a77970_pinmux_info,
},
#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A77980
+ {
+ .compatible = "renesas,pfc-r8a77980",
+ .data = &r8a77980_pinmux_info,
+ },
+#endif
#ifdef CONFIG_PINCTRL_PFC_R8A77995
{
.compatible = "renesas,pfc-r8a77995",
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index b769c05480da..f6332f247368 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -1835,8 +1835,8 @@ static const unsigned int avb_mii_pins[] = {
RCAR_GP_PIN(2, 2),
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
- RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 10),
- RCAR_GP_PIN(3, 12),
+ RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 12),
};
static const unsigned int avb_mii_mux[] = {
AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
@@ -1846,8 +1846,8 @@ static const unsigned int avb_mii_mux[] = {
AVB_RXD3_MARK,
AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
- AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_CLK_MARK,
- AVB_COL_MARK,
+ AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
+ AVB_TX_CLK_MARK, AVB_COL_MARK,
};
static const unsigned int avb_gmii_pins[] = {
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
index 292e35d4d2f4..82a1c411c952 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
@@ -1,7 +1,7 @@
/*
* R8A7795 ES1.x processor support - PFC hardware block.
*
- * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015-2017 Renesas Electronics Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -1652,11 +1652,11 @@ static const unsigned int avb_phy_int_pins[] = {
static const unsigned int avb_phy_int_mux[] = {
AVB_PHY_INT_MARK,
};
-static const unsigned int avb_mdc_pins[] = {
+static const unsigned int avb_mdio_pins[] = {
/* AVB_MDC, AVB_MDIO */
RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
};
-static const unsigned int avb_mdc_mux[] = {
+static const unsigned int avb_mdio_mux[] = {
AVB_MDC_MARK, AVB_MDIO_MARK,
};
static const unsigned int avb_mii_pins[] = {
@@ -2067,6 +2067,22 @@ static const unsigned int du_disp_pins[] = {
static const unsigned int du_disp_mux[] = {
DU_DISP_MARK,
};
+/* - HDMI ------------------------------------------------------------------- */
+static const unsigned int hdmi0_cec_pins[] = {
+ /* HDMI0_CEC */
+ RCAR_GP_PIN(7, 2),
+};
+static const unsigned int hdmi0_cec_mux[] = {
+ HDMI0_CEC_MARK,
+};
+static const unsigned int hdmi1_cec_pins[] = {
+ /* HDMI1_CEC */
+ RCAR_GP_PIN(7, 3),
+};
+static const unsigned int hdmi1_cec_mux[] = {
+ HDMI1_CEC_MARK,
+};
+
/* - HSCIF0 ----------------------------------------------------------------- */
static const unsigned int hscif0_data_pins[] = {
/* RX, TX */
@@ -3750,6 +3766,36 @@ static const unsigned int ssi9_ctrl_b_mux[] = {
SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
};
+/* - TMU -------------------------------------------------------------------- */
+static const unsigned int tmu_tclk1_a_pins[] = {
+ /* TCLK */
+ RCAR_GP_PIN(6, 23),
+};
+static const unsigned int tmu_tclk1_a_mux[] = {
+ TCLK1_A_MARK,
+};
+static const unsigned int tmu_tclk1_b_pins[] = {
+ /* TCLK */
+ RCAR_GP_PIN(5, 19),
+};
+static const unsigned int tmu_tclk1_b_mux[] = {
+ TCLK1_B_MARK,
+};
+static const unsigned int tmu_tclk2_a_pins[] = {
+ /* TCLK */
+ RCAR_GP_PIN(6, 19),
+};
+static const unsigned int tmu_tclk2_a_mux[] = {
+ TCLK2_A_MARK,
+};
+static const unsigned int tmu_tclk2_b_pins[] = {
+ /* TCLK */
+ RCAR_GP_PIN(6, 28),
+};
+static const unsigned int tmu_tclk2_b_mux[] = {
+ TCLK2_B_MARK,
+};
+
/* - USB0 ------------------------------------------------------------------- */
static const unsigned int usb0_pins[] = {
/* PWEN, OVC */
@@ -3813,7 +3859,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(avb_link),
SH_PFC_PIN_GROUP(avb_magic),
SH_PFC_PIN_GROUP(avb_phy_int),
- SH_PFC_PIN_GROUP(avb_mdc),
+ SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
+ SH_PFC_PIN_GROUP(avb_mdio),
SH_PFC_PIN_GROUP(avb_mii),
SH_PFC_PIN_GROUP(avb_avtp_pps),
SH_PFC_PIN_GROUP(avb_avtp_match_a),
@@ -3865,6 +3912,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(du_oddf),
SH_PFC_PIN_GROUP(du_cde),
SH_PFC_PIN_GROUP(du_disp),
+ SH_PFC_PIN_GROUP(hdmi0_cec),
+ SH_PFC_PIN_GROUP(hdmi1_cec),
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_ctrl),
@@ -4095,6 +4144,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(ssi9_data_b),
SH_PFC_PIN_GROUP(ssi9_ctrl_a),
SH_PFC_PIN_GROUP(ssi9_ctrl_b),
+ SH_PFC_PIN_GROUP(tmu_tclk1_a),
+ SH_PFC_PIN_GROUP(tmu_tclk1_b),
+ SH_PFC_PIN_GROUP(tmu_tclk2_a),
+ SH_PFC_PIN_GROUP(tmu_tclk2_b),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb2),
@@ -4126,7 +4179,8 @@ static const char * const avb_groups[] = {
"avb_link",
"avb_magic",
"avb_phy_int",
- "avb_mdc",
+ "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
+ "avb_mdio",
"avb_mii",
"avb_avtp_pps",
"avb_avtp_match_a",
@@ -4210,6 +4264,14 @@ static const char * const du_groups[] = {
"du_disp",
};
+static const char * const hdmi0_groups[] = {
+ "hdmi0_cec",
+};
+
+static const char * const hdmi1_groups[] = {
+ "hdmi1_cec",
+};
+
static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
@@ -4545,6 +4607,13 @@ static const char * const ssi_groups[] = {
"ssi9_ctrl_b",
};
+static const char * const tmu_groups[] = {
+ "tmu_tclk1_a",
+ "tmu_tclk1_b",
+ "tmu_tclk2_a",
+ "tmu_tclk2_b",
+};
+
static const char * const usb0_groups[] = {
"usb0",
};
@@ -4578,6 +4647,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
SH_PFC_FUNCTION(du),
+ SH_PFC_FUNCTION(hdmi0),
+ SH_PFC_FUNCTION(hdmi1),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2),
@@ -4613,6 +4684,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(sdhi2),
SH_PFC_FUNCTION(sdhi3),
SH_PFC_FUNCTION(ssi),
+ SH_PFC_FUNCTION(tmu),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(usb2),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 35951e7b89d2..7100a2dd65f8 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -1,7 +1,7 @@
/*
* R8A7795 ES2.0+ processor support - PFC hardware block.
*
- * Copyright (C) 2015-2016 Renesas Electronics Corporation
+ * Copyright (C) 2015-2017 Renesas Electronics Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -472,7 +472,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
#define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1)
#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
-#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
+#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
@@ -1218,7 +1218,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
- PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1),
+ PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
@@ -1226,14 +1226,14 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
- PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1),
+ PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
- PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1),
+ PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
@@ -1241,7 +1241,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
- PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0),
+ PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
@@ -1250,7 +1250,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
- PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0),
+ PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
@@ -1265,7 +1265,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
- PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0),
+ PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1),
@@ -1274,7 +1274,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
- PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0),
+ PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
@@ -1302,10 +1302,10 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
/* IPSR15 */
- PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0),
+ PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
- PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0),
- PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1),
+ PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
+ PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
@@ -1394,11 +1394,11 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
- PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0),
+ PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
- PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1),
+ PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
@@ -1430,7 +1430,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
- PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0),
+ PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
@@ -1440,7 +1440,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
- PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0),
+ PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
@@ -1450,7 +1450,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
- PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
+ PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
@@ -1462,7 +1462,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
- PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1),
+ PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
@@ -1473,7 +1473,7 @@ static const u16 pinmux_data[] = {
/* IPSR18 */
PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN),
PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
- PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1),
+ PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
@@ -1483,7 +1483,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC),
PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
- PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1),
+ PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
@@ -1711,11 +1711,11 @@ static const unsigned int avb_phy_int_pins[] = {
static const unsigned int avb_phy_int_mux[] = {
AVB_PHY_INT_MARK,
};
-static const unsigned int avb_mdc_pins[] = {
+static const unsigned int avb_mdio_pins[] = {
/* AVB_MDC, AVB_MDIO */
RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
};
-static const unsigned int avb_mdc_mux[] = {
+static const unsigned int avb_mdio_mux[] = {
AVB_MDC_MARK, AVB_MDIO_MARK,
};
static const unsigned int avb_mii_pins[] = {
@@ -2127,6 +2127,22 @@ static const unsigned int du_disp_mux[] = {
DU_DISP_MARK,
};
+/* - HDMI ------------------------------------------------------------------- */
+static const unsigned int hdmi0_cec_pins[] = {
+ /* HDMI0_CEC */
+ RCAR_GP_PIN(7, 2),
+};
+static const unsigned int hdmi0_cec_mux[] = {
+ HDMI0_CEC_MARK,
+};
+static const unsigned int hdmi1_cec_pins[] = {
+ /* HDMI1_CEC */
+ RCAR_GP_PIN(7, 3),
+};
+static const unsigned int hdmi1_cec_mux[] = {
+ HDMI1_CEC_MARK,
+};
+
/* - HSCIF0 ----------------------------------------------------------------- */
static const unsigned int hscif0_data_pins[] = {
/* RX, TX */
@@ -3839,6 +3855,36 @@ static const unsigned int ssi9_ctrl_b_mux[] = {
SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
};
+/* - TMU -------------------------------------------------------------------- */
+static const unsigned int tmu_tclk1_a_pins[] = {
+ /* TCLK */
+ RCAR_GP_PIN(6, 23),
+};
+static const unsigned int tmu_tclk1_a_mux[] = {
+ TCLK1_A_MARK,
+};
+static const unsigned int tmu_tclk1_b_pins[] = {
+ /* TCLK */
+ RCAR_GP_PIN(5, 19),
+};
+static const unsigned int tmu_tclk1_b_mux[] = {
+ TCLK1_B_MARK,
+};
+static const unsigned int tmu_tclk2_a_pins[] = {
+ /* TCLK */
+ RCAR_GP_PIN(6, 19),
+};
+static const unsigned int tmu_tclk2_a_mux[] = {
+ TCLK2_A_MARK,
+};
+static const unsigned int tmu_tclk2_b_pins[] = {
+ /* TCLK */
+ RCAR_GP_PIN(6, 28),
+};
+static const unsigned int tmu_tclk2_b_mux[] = {
+ TCLK2_B_MARK,
+};
+
/* - USB0 ------------------------------------------------------------------- */
static const unsigned int usb0_pins[] = {
/* PWEN, OVC */
@@ -3881,6 +3927,236 @@ static const unsigned int usb30_mux[] = {
USB30_PWEN_MARK, USB30_OVC_MARK,
};
+/* - VIN4 ------------------------------------------------------------------- */
+static const unsigned int vin4_data18_a_pins[] = {
+ RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+ RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+};
+static const unsigned int vin4_data18_a_mux[] = {
+ VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+ VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+ VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+ VI4_DATA10_MARK, VI4_DATA11_MARK,
+ VI4_DATA12_MARK, VI4_DATA13_MARK,
+ VI4_DATA14_MARK, VI4_DATA15_MARK,
+ VI4_DATA18_MARK, VI4_DATA19_MARK,
+ VI4_DATA20_MARK, VI4_DATA21_MARK,
+ VI4_DATA22_MARK, VI4_DATA23_MARK,
+};
+static const unsigned int vin4_data18_b_pins[] = {
+ RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+};
+static const unsigned int vin4_data18_b_mux[] = {
+ VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+ VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+ VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+ VI4_DATA10_MARK, VI4_DATA11_MARK,
+ VI4_DATA12_MARK, VI4_DATA13_MARK,
+ VI4_DATA14_MARK, VI4_DATA15_MARK,
+ VI4_DATA18_MARK, VI4_DATA19_MARK,
+ VI4_DATA20_MARK, VI4_DATA21_MARK,
+ VI4_DATA22_MARK, VI4_DATA23_MARK,
+};
+static const union vin_data vin4_data_a_pins = {
+ .data24 = {
+ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+ RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+ RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+ RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+ },
+};
+static const union vin_data vin4_data_a_mux = {
+ .data24 = {
+ VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+ VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+ VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+ VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+ VI4_DATA8_MARK, VI4_DATA9_MARK,
+ VI4_DATA10_MARK, VI4_DATA11_MARK,
+ VI4_DATA12_MARK, VI4_DATA13_MARK,
+ VI4_DATA14_MARK, VI4_DATA15_MARK,
+ VI4_DATA16_MARK, VI4_DATA17_MARK,
+ VI4_DATA18_MARK, VI4_DATA19_MARK,
+ VI4_DATA20_MARK, VI4_DATA21_MARK,
+ VI4_DATA22_MARK, VI4_DATA23_MARK,
+ },
+};
+static const union vin_data vin4_data_b_pins = {
+ .data24 = {
+ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+ RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+ RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+ },
+};
+static const union vin_data vin4_data_b_mux = {
+ .data24 = {
+ VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+ VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+ VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+ VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+ VI4_DATA8_MARK, VI4_DATA9_MARK,
+ VI4_DATA10_MARK, VI4_DATA11_MARK,
+ VI4_DATA12_MARK, VI4_DATA13_MARK,
+ VI4_DATA14_MARK, VI4_DATA15_MARK,
+ VI4_DATA16_MARK, VI4_DATA17_MARK,
+ VI4_DATA18_MARK, VI4_DATA19_MARK,
+ VI4_DATA20_MARK, VI4_DATA21_MARK,
+ VI4_DATA22_MARK, VI4_DATA23_MARK,
+ },
+};
+static const unsigned int vin4_sync_pins[] = {
+ /* HSYNC#, VSYNC# */
+ RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
+};
+static const unsigned int vin4_sync_mux[] = {
+ VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
+};
+static const unsigned int vin4_field_pins[] = {
+ /* FIELD */
+ RCAR_GP_PIN(1, 16),
+};
+static const unsigned int vin4_field_mux[] = {
+ VI4_FIELD_MARK,
+};
+static const unsigned int vin4_clkenb_pins[] = {
+ /* CLKENB */
+ RCAR_GP_PIN(1, 19),
+};
+static const unsigned int vin4_clkenb_mux[] = {
+ VI4_CLKENB_MARK,
+};
+static const unsigned int vin4_clk_pins[] = {
+ /* CLK */
+ RCAR_GP_PIN(1, 27),
+};
+static const unsigned int vin4_clk_mux[] = {
+ VI4_CLK_MARK,
+};
+
+/* - VIN5 ------------------------------------------------------------------- */
+static const unsigned int vin5_data8_pins[] = {
+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+};
+static const unsigned int vin5_data8_mux[] = {
+ VI5_DATA0_MARK, VI5_DATA1_MARK,
+ VI5_DATA2_MARK, VI5_DATA3_MARK,
+ VI5_DATA4_MARK, VI5_DATA5_MARK,
+ VI5_DATA6_MARK, VI5_DATA7_MARK,
+};
+static const unsigned int vin5_data10_pins[] = {
+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+ RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
+};
+static const unsigned int vin5_data10_mux[] = {
+ VI5_DATA0_MARK, VI5_DATA1_MARK,
+ VI5_DATA2_MARK, VI5_DATA3_MARK,
+ VI5_DATA4_MARK, VI5_DATA5_MARK,
+ VI5_DATA6_MARK, VI5_DATA7_MARK,
+ VI5_DATA8_MARK, VI5_DATA9_MARK,
+};
+static const unsigned int vin5_data12_pins[] = {
+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+ RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
+ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
+};
+static const unsigned int vin5_data12_mux[] = {
+ VI5_DATA0_MARK, VI5_DATA1_MARK,
+ VI5_DATA2_MARK, VI5_DATA3_MARK,
+ VI5_DATA4_MARK, VI5_DATA5_MARK,
+ VI5_DATA6_MARK, VI5_DATA7_MARK,
+ VI5_DATA8_MARK, VI5_DATA9_MARK,
+ VI5_DATA10_MARK, VI5_DATA11_MARK,
+};
+static const unsigned int vin5_data16_pins[] = {
+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+ RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
+ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+};
+static const unsigned int vin5_data16_mux[] = {
+ VI5_DATA0_MARK, VI5_DATA1_MARK,
+ VI5_DATA2_MARK, VI5_DATA3_MARK,
+ VI5_DATA4_MARK, VI5_DATA5_MARK,
+ VI5_DATA6_MARK, VI5_DATA7_MARK,
+ VI5_DATA8_MARK, VI5_DATA9_MARK,
+ VI5_DATA10_MARK, VI5_DATA11_MARK,
+ VI5_DATA12_MARK, VI5_DATA13_MARK,
+ VI5_DATA14_MARK, VI5_DATA15_MARK,
+};
+static const unsigned int vin5_sync_pins[] = {
+ /* HSYNC#, VSYNC# */
+ RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
+};
+static const unsigned int vin5_sync_mux[] = {
+ VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
+};
+static const unsigned int vin5_field_pins[] = {
+ RCAR_GP_PIN(1, 11),
+};
+static const unsigned int vin5_field_mux[] = {
+ /* FIELD */
+ VI5_FIELD_MARK,
+};
+static const unsigned int vin5_clkenb_pins[] = {
+ RCAR_GP_PIN(1, 20),
+};
+static const unsigned int vin5_clkenb_mux[] = {
+ /* CLKENB */
+ VI5_CLKENB_MARK,
+};
+static const unsigned int vin5_clk_pins[] = {
+ RCAR_GP_PIN(1, 21),
+};
+static const unsigned int vin5_clk_mux[] = {
+ /* CLK */
+ VI5_CLK_MARK,
+};
+
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(audio_clk_a_a),
SH_PFC_PIN_GROUP(audio_clk_a_b),
@@ -3902,7 +4178,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(avb_link),
SH_PFC_PIN_GROUP(avb_magic),
SH_PFC_PIN_GROUP(avb_phy_int),
- SH_PFC_PIN_GROUP(avb_mdc),
+ SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
+ SH_PFC_PIN_GROUP(avb_mdio),
SH_PFC_PIN_GROUP(avb_mii),
SH_PFC_PIN_GROUP(avb_avtp_pps),
SH_PFC_PIN_GROUP(avb_avtp_match_a),
@@ -3954,6 +4231,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(du_oddf),
SH_PFC_PIN_GROUP(du_cde),
SH_PFC_PIN_GROUP(du_disp),
+ SH_PFC_PIN_GROUP(hdmi0_cec),
+ SH_PFC_PIN_GROUP(hdmi1_cec),
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_ctrl),
@@ -4189,11 +4468,41 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(ssi9_data_b),
SH_PFC_PIN_GROUP(ssi9_ctrl_a),
SH_PFC_PIN_GROUP(ssi9_ctrl_b),
+ SH_PFC_PIN_GROUP(tmu_tclk1_a),
+ SH_PFC_PIN_GROUP(tmu_tclk1_b),
+ SH_PFC_PIN_GROUP(tmu_tclk2_a),
+ SH_PFC_PIN_GROUP(tmu_tclk2_b),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb2),
SH_PFC_PIN_GROUP(usb2_ch3),
SH_PFC_PIN_GROUP(usb30),
+ VIN_DATA_PIN_GROUP(vin4_data_a, 8),
+ VIN_DATA_PIN_GROUP(vin4_data_a, 10),
+ VIN_DATA_PIN_GROUP(vin4_data_a, 12),
+ VIN_DATA_PIN_GROUP(vin4_data_a, 16),
+ SH_PFC_PIN_GROUP(vin4_data18_a),
+ VIN_DATA_PIN_GROUP(vin4_data_a, 20),
+ VIN_DATA_PIN_GROUP(vin4_data_a, 24),
+ VIN_DATA_PIN_GROUP(vin4_data_b, 8),
+ VIN_DATA_PIN_GROUP(vin4_data_b, 10),
+ VIN_DATA_PIN_GROUP(vin4_data_b, 12),
+ VIN_DATA_PIN_GROUP(vin4_data_b, 16),
+ SH_PFC_PIN_GROUP(vin4_data18_b),
+ VIN_DATA_PIN_GROUP(vin4_data_b, 20),
+ VIN_DATA_PIN_GROUP(vin4_data_b, 24),
+ SH_PFC_PIN_GROUP(vin4_sync),
+ SH_PFC_PIN_GROUP(vin4_field),
+ SH_PFC_PIN_GROUP(vin4_clkenb),
+ SH_PFC_PIN_GROUP(vin4_clk),
+ SH_PFC_PIN_GROUP(vin5_data8),
+ SH_PFC_PIN_GROUP(vin5_data10),
+ SH_PFC_PIN_GROUP(vin5_data12),
+ SH_PFC_PIN_GROUP(vin5_data16),
+ SH_PFC_PIN_GROUP(vin5_sync),
+ SH_PFC_PIN_GROUP(vin5_field),
+ SH_PFC_PIN_GROUP(vin5_clkenb),
+ SH_PFC_PIN_GROUP(vin5_clk),
};
static const char * const audio_clk_groups[] = {
@@ -4220,7 +4529,8 @@ static const char * const avb_groups[] = {
"avb_link",
"avb_magic",
"avb_phy_int",
- "avb_mdc",
+ "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
+ "avb_mdio",
"avb_mii",
"avb_avtp_pps",
"avb_avtp_match_a",
@@ -4304,6 +4614,14 @@ static const char * const du_groups[] = {
"du_disp",
};
+static const char * const hdmi0_groups[] = {
+ "hdmi0_cec",
+};
+
+static const char * const hdmi1_groups[] = {
+ "hdmi1_cec",
+};
+
static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
@@ -4638,6 +4956,13 @@ static const char * const ssi_groups[] = {
"ssi9_ctrl_b",
};
+static const char * const tmu_groups[] = {
+ "tmu_tclk1_a",
+ "tmu_tclk1_b",
+ "tmu_tclk2_a",
+ "tmu_tclk2_b",
+};
+
static const char * const usb0_groups[] = {
"usb0",
};
@@ -4658,6 +4983,38 @@ static const char * const usb30_groups[] = {
"usb30",
};
+static const char * const vin4_groups[] = {
+ "vin4_data8_a",
+ "vin4_data10_a",
+ "vin4_data12_a",
+ "vin4_data16_a",
+ "vin4_data18_a",
+ "vin4_data20_a",
+ "vin4_data24_a",
+ "vin4_data8_b",
+ "vin4_data10_b",
+ "vin4_data12_b",
+ "vin4_data16_b",
+ "vin4_data18_b",
+ "vin4_data20_b",
+ "vin4_data24_b",
+ "vin4_sync",
+ "vin4_field",
+ "vin4_clkenb",
+ "vin4_clk",
+};
+
+static const char * const vin5_groups[] = {
+ "vin5_data8",
+ "vin5_data10",
+ "vin5_data12",
+ "vin5_data16",
+ "vin5_sync",
+ "vin5_field",
+ "vin5_clkenb",
+ "vin5_clk",
+};
+
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(audio_clk),
SH_PFC_FUNCTION(avb),
@@ -4671,6 +5028,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
SH_PFC_FUNCTION(du),
+ SH_PFC_FUNCTION(hdmi0),
+ SH_PFC_FUNCTION(hdmi1),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2),
@@ -4704,11 +5063,14 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(sdhi2),
SH_PFC_FUNCTION(sdhi3),
SH_PFC_FUNCTION(ssi),
+ SH_PFC_FUNCTION(tmu),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(usb2),
SH_PFC_FUNCTION(usb2_ch3),
SH_PFC_FUNCTION(usb30),
+ SH_PFC_FUNCTION(vin4),
+ SH_PFC_FUNCTION(vin5),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index e5807d1ce0dc..4bc5b1f820c1 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -1,7 +1,7 @@
/*
* R8A7796 processor support - PFC hardware block.
*
- * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2016-2017 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
*
@@ -477,7 +477,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
-#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
+#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
@@ -502,7 +502,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
+#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
@@ -1016,35 +1016,35 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
+ PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
+ PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
+ PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
+ PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
+ PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
@@ -1110,16 +1110,20 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
+ PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
+ PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
+ PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
+ PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
@@ -1218,7 +1222,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
- PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1),
+ PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
@@ -1226,14 +1230,14 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
- PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1),
+ PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
- PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1),
+ PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
@@ -1241,7 +1245,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
- PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0),
+ PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
@@ -1250,7 +1254,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
- PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0),
+ PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
@@ -1263,9 +1267,9 @@ static const u16 pinmux_data[] = {
/* IPSR14 */
PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
- PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
+ PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
- PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0),
+ PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
@@ -1274,7 +1278,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
- PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0),
+ PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
@@ -1302,10 +1306,10 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
/* IPSR15 */
- PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0),
+ PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
- PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0),
- PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1),
+ PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
+ PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
@@ -1391,11 +1395,11 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
- PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0),
+ PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
- PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1),
+ PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
@@ -1427,7 +1431,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
- PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0),
+ PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
@@ -1437,7 +1441,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
- PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0),
+ PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
@@ -1447,7 +1451,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
- PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
+ PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
@@ -1459,7 +1463,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
- PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1),
+ PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
@@ -1470,7 +1474,7 @@ static const u16 pinmux_data[] = {
/* IPSR18 */
PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
- PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1),
+ PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
@@ -1480,7 +1484,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
- PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1),
+ PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
@@ -1713,11 +1717,11 @@ static const unsigned int avb_phy_int_pins[] = {
static const unsigned int avb_phy_int_mux[] = {
AVB_PHY_INT_MARK,
};
-static const unsigned int avb_mdc_pins[] = {
+static const unsigned int avb_mdio_pins[] = {
/* AVB_MDC, AVB_MDIO */
RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
};
-static const unsigned int avb_mdc_mux[] = {
+static const unsigned int avb_mdio_mux[] = {
AVB_MDC_MARK, AVB_MDIO_MARK,
};
static const unsigned int avb_mii_pins[] = {
@@ -2129,6 +2133,15 @@ static const unsigned int du_disp_mux[] = {
DU_DISP_MARK,
};
+/* - HDMI ------------------------------------------------------------------- */
+static const unsigned int hdmi0_cec_pins[] = {
+ /* HDMI0_CEC */
+ RCAR_GP_PIN(7, 2),
+};
+static const unsigned int hdmi0_cec_mux[] = {
+ HDMI0_CEC_MARK,
+};
+
/* - HSCIF0 ----------------------------------------------------------------- */
static const unsigned int hscif0_data_pins[] = {
/* RX, TX */
@@ -3827,6 +3840,36 @@ static const unsigned int ssi9_ctrl_b_mux[] = {
SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
};
+/* - TMU -------------------------------------------------------------------- */
+static const unsigned int tmu_tclk1_a_pins[] = {
+ /* TCLK */
+ RCAR_GP_PIN(6, 23),
+};
+static const unsigned int tmu_tclk1_a_mux[] = {
+ TCLK1_A_MARK,
+};
+static const unsigned int tmu_tclk1_b_pins[] = {
+ /* TCLK */
+ RCAR_GP_PIN(5, 19),
+};
+static const unsigned int tmu_tclk1_b_mux[] = {
+ TCLK1_B_MARK,
+};
+static const unsigned int tmu_tclk2_a_pins[] = {
+ /* TCLK */
+ RCAR_GP_PIN(6, 19),
+};
+static const unsigned int tmu_tclk2_a_mux[] = {
+ TCLK2_A_MARK,
+};
+static const unsigned int tmu_tclk2_b_pins[] = {
+ /* TCLK */
+ RCAR_GP_PIN(6, 28),
+};
+static const unsigned int tmu_tclk2_b_mux[] = {
+ TCLK2_B_MARK,
+};
+
/* - USB0 ------------------------------------------------------------------- */
static const unsigned int usb0_pins[] = {
/* PWEN, OVC */
@@ -3853,6 +3896,236 @@ static const unsigned int usb30_mux[] = {
USB30_PWEN_MARK, USB30_OVC_MARK,
};
+/* - VIN4 ------------------------------------------------------------------- */
+static const unsigned int vin4_data18_a_pins[] = {
+ RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+ RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+};
+static const unsigned int vin4_data18_a_mux[] = {
+ VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+ VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+ VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+ VI4_DATA10_MARK, VI4_DATA11_MARK,
+ VI4_DATA12_MARK, VI4_DATA13_MARK,
+ VI4_DATA14_MARK, VI4_DATA15_MARK,
+ VI4_DATA18_MARK, VI4_DATA19_MARK,
+ VI4_DATA20_MARK, VI4_DATA21_MARK,
+ VI4_DATA22_MARK, VI4_DATA23_MARK,
+};
+static const unsigned int vin4_data18_b_pins[] = {
+ RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+};
+static const unsigned int vin4_data18_b_mux[] = {
+ VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+ VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+ VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+ VI4_DATA10_MARK, VI4_DATA11_MARK,
+ VI4_DATA12_MARK, VI4_DATA13_MARK,
+ VI4_DATA14_MARK, VI4_DATA15_MARK,
+ VI4_DATA18_MARK, VI4_DATA19_MARK,
+ VI4_DATA20_MARK, VI4_DATA21_MARK,
+ VI4_DATA22_MARK, VI4_DATA23_MARK,
+};
+static const union vin_data vin4_data_a_pins = {
+ .data24 = {
+ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+ RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+ RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+ RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+ },
+};
+static const union vin_data vin4_data_a_mux = {
+ .data24 = {
+ VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+ VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+ VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+ VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+ VI4_DATA8_MARK, VI4_DATA9_MARK,
+ VI4_DATA10_MARK, VI4_DATA11_MARK,
+ VI4_DATA12_MARK, VI4_DATA13_MARK,
+ VI4_DATA14_MARK, VI4_DATA15_MARK,
+ VI4_DATA16_MARK, VI4_DATA17_MARK,
+ VI4_DATA18_MARK, VI4_DATA19_MARK,
+ VI4_DATA20_MARK, VI4_DATA21_MARK,
+ VI4_DATA22_MARK, VI4_DATA23_MARK,
+ },
+};
+static const union vin_data vin4_data_b_pins = {
+ .data24 = {
+ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+ RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+ RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+ },
+};
+static const union vin_data vin4_data_b_mux = {
+ .data24 = {
+ VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+ VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+ VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+ VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+ VI4_DATA8_MARK, VI4_DATA9_MARK,
+ VI4_DATA10_MARK, VI4_DATA11_MARK,
+ VI4_DATA12_MARK, VI4_DATA13_MARK,
+ VI4_DATA14_MARK, VI4_DATA15_MARK,
+ VI4_DATA16_MARK, VI4_DATA17_MARK,
+ VI4_DATA18_MARK, VI4_DATA19_MARK,
+ VI4_DATA20_MARK, VI4_DATA21_MARK,
+ VI4_DATA22_MARK, VI4_DATA23_MARK,
+ },
+};
+static const unsigned int vin4_sync_pins[] = {
+ /* HSYNC#, VSYNC# */
+ RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
+};
+static const unsigned int vin4_sync_mux[] = {
+ VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
+};
+static const unsigned int vin4_field_pins[] = {
+ /* FIELD */
+ RCAR_GP_PIN(1, 16),
+};
+static const unsigned int vin4_field_mux[] = {
+ VI4_FIELD_MARK,
+};
+static const unsigned int vin4_clkenb_pins[] = {
+ /* CLKENB */
+ RCAR_GP_PIN(1, 19),
+};
+static const unsigned int vin4_clkenb_mux[] = {
+ VI4_CLKENB_MARK,
+};
+static const unsigned int vin4_clk_pins[] = {
+ /* CLK */
+ RCAR_GP_PIN(1, 27),
+};
+static const unsigned int vin4_clk_mux[] = {
+ VI4_CLK_MARK,
+};
+
+/* - VIN5 ------------------------------------------------------------------- */
+static const unsigned int vin5_data8_pins[] = {
+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+};
+static const unsigned int vin5_data8_mux[] = {
+ VI5_DATA0_MARK, VI5_DATA1_MARK,
+ VI5_DATA2_MARK, VI5_DATA3_MARK,
+ VI5_DATA4_MARK, VI5_DATA5_MARK,
+ VI5_DATA6_MARK, VI5_DATA7_MARK,
+};
+static const unsigned int vin5_data10_pins[] = {
+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+ RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
+};
+static const unsigned int vin5_data10_mux[] = {
+ VI5_DATA0_MARK, VI5_DATA1_MARK,
+ VI5_DATA2_MARK, VI5_DATA3_MARK,
+ VI5_DATA4_MARK, VI5_DATA5_MARK,
+ VI5_DATA6_MARK, VI5_DATA7_MARK,
+ VI5_DATA8_MARK, VI5_DATA9_MARK,
+};
+static const unsigned int vin5_data12_pins[] = {
+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+ RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
+ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
+};
+static const unsigned int vin5_data12_mux[] = {
+ VI5_DATA0_MARK, VI5_DATA1_MARK,
+ VI5_DATA2_MARK, VI5_DATA3_MARK,
+ VI5_DATA4_MARK, VI5_DATA5_MARK,
+ VI5_DATA6_MARK, VI5_DATA7_MARK,
+ VI5_DATA8_MARK, VI5_DATA9_MARK,
+ VI5_DATA10_MARK, VI5_DATA11_MARK,
+};
+static const unsigned int vin5_data16_pins[] = {
+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+ RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
+ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+};
+static const unsigned int vin5_data16_mux[] = {
+ VI5_DATA0_MARK, VI5_DATA1_MARK,
+ VI5_DATA2_MARK, VI5_DATA3_MARK,
+ VI5_DATA4_MARK, VI5_DATA5_MARK,
+ VI5_DATA6_MARK, VI5_DATA7_MARK,
+ VI5_DATA8_MARK, VI5_DATA9_MARK,
+ VI5_DATA10_MARK, VI5_DATA11_MARK,
+ VI5_DATA12_MARK, VI5_DATA13_MARK,
+ VI5_DATA14_MARK, VI5_DATA15_MARK,
+};
+static const unsigned int vin5_sync_pins[] = {
+ /* HSYNC#, VSYNC# */
+ RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
+};
+static const unsigned int vin5_sync_mux[] = {
+ VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
+};
+static const unsigned int vin5_field_pins[] = {
+ RCAR_GP_PIN(1, 11),
+};
+static const unsigned int vin5_field_mux[] = {
+ /* FIELD */
+ VI5_FIELD_MARK,
+};
+static const unsigned int vin5_clkenb_pins[] = {
+ RCAR_GP_PIN(1, 20),
+};
+static const unsigned int vin5_clkenb_mux[] = {
+ /* CLKENB */
+ VI5_CLKENB_MARK,
+};
+static const unsigned int vin5_clk_pins[] = {
+ RCAR_GP_PIN(1, 21),
+};
+static const unsigned int vin5_clk_mux[] = {
+ /* CLK */
+ VI5_CLK_MARK,
+};
+
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(audio_clk_a_a),
SH_PFC_PIN_GROUP(audio_clk_a_b),
@@ -3874,7 +4147,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(avb_link),
SH_PFC_PIN_GROUP(avb_magic),
SH_PFC_PIN_GROUP(avb_phy_int),
- SH_PFC_PIN_GROUP(avb_mdc),
+ SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
+ SH_PFC_PIN_GROUP(avb_mdio),
SH_PFC_PIN_GROUP(avb_mii),
SH_PFC_PIN_GROUP(avb_avtp_pps),
SH_PFC_PIN_GROUP(avb_avtp_match_a),
@@ -3926,6 +4200,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(du_oddf),
SH_PFC_PIN_GROUP(du_cde),
SH_PFC_PIN_GROUP(du_disp),
+ SH_PFC_PIN_GROUP(hdmi0_cec),
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_ctrl),
@@ -4159,9 +4434,39 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(ssi9_data_b),
SH_PFC_PIN_GROUP(ssi9_ctrl_a),
SH_PFC_PIN_GROUP(ssi9_ctrl_b),
+ SH_PFC_PIN_GROUP(tmu_tclk1_a),
+ SH_PFC_PIN_GROUP(tmu_tclk1_b),
+ SH_PFC_PIN_GROUP(tmu_tclk2_a),
+ SH_PFC_PIN_GROUP(tmu_tclk2_b),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb30),
+ VIN_DATA_PIN_GROUP(vin4_data_a, 8),
+ VIN_DATA_PIN_GROUP(vin4_data_a, 10),
+ VIN_DATA_PIN_GROUP(vin4_data_a, 12),
+ VIN_DATA_PIN_GROUP(vin4_data_a, 16),
+ SH_PFC_PIN_GROUP(vin4_data18_a),
+ VIN_DATA_PIN_GROUP(vin4_data_a, 20),
+ VIN_DATA_PIN_GROUP(vin4_data_a, 24),
+ VIN_DATA_PIN_GROUP(vin4_data_b, 8),
+ VIN_DATA_PIN_GROUP(vin4_data_b, 10),
+ VIN_DATA_PIN_GROUP(vin4_data_b, 12),
+ VIN_DATA_PIN_GROUP(vin4_data_b, 16),
+ SH_PFC_PIN_GROUP(vin4_data18_b),
+ VIN_DATA_PIN_GROUP(vin4_data_b, 20),
+ VIN_DATA_PIN_GROUP(vin4_data_b, 24),
+ SH_PFC_PIN_GROUP(vin4_sync),
+ SH_PFC_PIN_GROUP(vin4_field),
+ SH_PFC_PIN_GROUP(vin4_clkenb),
+ SH_PFC_PIN_GROUP(vin4_clk),
+ SH_PFC_PIN_GROUP(vin5_data8),
+ SH_PFC_PIN_GROUP(vin5_data10),
+ SH_PFC_PIN_GROUP(vin5_data12),
+ SH_PFC_PIN_GROUP(vin5_data16),
+ SH_PFC_PIN_GROUP(vin5_sync),
+ SH_PFC_PIN_GROUP(vin5_field),
+ SH_PFC_PIN_GROUP(vin5_clkenb),
+ SH_PFC_PIN_GROUP(vin5_clk),
};
static const char * const audio_clk_groups[] = {
@@ -4188,7 +4493,8 @@ static const char * const avb_groups[] = {
"avb_link",
"avb_magic",
"avb_phy_int",
- "avb_mdc",
+ "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
+ "avb_mdio",
"avb_mii",
"avb_avtp_pps",
"avb_avtp_match_a",
@@ -4272,6 +4578,10 @@ static const char * const du_groups[] = {
"du_disp",
};
+static const char * const hdmi0_groups[] = {
+ "hdmi0_cec",
+};
+
static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
@@ -4601,6 +4911,13 @@ static const char * const ssi_groups[] = {
"ssi9_ctrl_b",
};
+static const char * const tmu_groups[] = {
+ "tmu_tclk1_a",
+ "tmu_tclk1_b",
+ "tmu_tclk2_a",
+ "tmu_tclk2_b",
+};
+
static const char * const usb0_groups[] = {
"usb0",
};
@@ -4613,6 +4930,38 @@ static const char * const usb30_groups[] = {
"usb30",
};
+static const char * const vin4_groups[] = {
+ "vin4_data8_a",
+ "vin4_data10_a",
+ "vin4_data12_a",
+ "vin4_data16_a",
+ "vin4_data18_a",
+ "vin4_data20_a",
+ "vin4_data24_a",
+ "vin4_data8_b",
+ "vin4_data10_b",
+ "vin4_data12_b",
+ "vin4_data16_b",
+ "vin4_data18_b",
+ "vin4_data20_b",
+ "vin4_data24_b",
+ "vin4_sync",
+ "vin4_field",
+ "vin4_clkenb",
+ "vin4_clk",
+};
+
+static const char * const vin5_groups[] = {
+ "vin5_data8",
+ "vin5_data10",
+ "vin5_data12",
+ "vin5_data16",
+ "vin5_sync",
+ "vin5_field",
+ "vin5_clkenb",
+ "vin5_clk",
+};
+
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(audio_clk),
SH_PFC_FUNCTION(avb),
@@ -4626,6 +4975,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
SH_PFC_FUNCTION(du),
+ SH_PFC_FUNCTION(hdmi0),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2),
@@ -4658,9 +5008,12 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(sdhi2),
SH_PFC_FUNCTION(sdhi3),
SH_PFC_FUNCTION(ssi),
+ SH_PFC_FUNCTION(tmu),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(usb30),
+ SH_PFC_FUNCTION(vin4),
+ SH_PFC_FUNCTION(vin5),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
new file mode 100644
index 000000000000..cea9d0599c12
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
@@ -0,0 +1,3243 @@
+// SPDX-License-Identifier: GPL-2.
+/*
+ * R8A77965 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ *
+ * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+ *
+ * R-Car Gen3 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ */
+
+#include <linux/kernel.h>
+
+#include "core.h"
+#include "sh_pfc.h"
+
+#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
+ SH_PFC_PIN_CFG_PULL_UP | \
+ SH_PFC_PIN_CFG_PULL_DOWN)
+
+#define CPU_ALL_PORT(fn, sfx) \
+ PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
+/*
+ * F_() : just information
+ * FM() : macro for FN_xxx / xxx_MARK
+ */
+
+/* GPSR0 */
+#define GPSR0_15 F_(D15, IP7_11_8)
+#define GPSR0_14 F_(D14, IP7_7_4)
+#define GPSR0_13 F_(D13, IP7_3_0)
+#define GPSR0_12 F_(D12, IP6_31_28)
+#define GPSR0_11 F_(D11, IP6_27_24)
+#define GPSR0_10 F_(D10, IP6_23_20)
+#define GPSR0_9 F_(D9, IP6_19_16)
+#define GPSR0_8 F_(D8, IP6_15_12)
+#define GPSR0_7 F_(D7, IP6_11_8)
+#define GPSR0_6 F_(D6, IP6_7_4)
+#define GPSR0_5 F_(D5, IP6_3_0)
+#define GPSR0_4 F_(D4, IP5_31_28)
+#define GPSR0_3 F_(D3, IP5_27_24)
+#define GPSR0_2 F_(D2, IP5_23_20)
+#define GPSR0_1 F_(D1, IP5_19_16)
+#define GPSR0_0 F_(D0, IP5_15_12)
+
+/* GPSR1 */
+#define GPSR1_28 FM(CLKOUT)
+#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
+#define GPSR1_26 F_(WE1_N, IP5_7_4)
+#define GPSR1_25 F_(WE0_N, IP5_3_0)
+#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
+#define GPSR1_23 F_(RD_N, IP4_27_24)
+#define GPSR1_22 F_(BS_N, IP4_23_20)
+#define GPSR1_21 F_(CS1_N, IP4_19_16)
+#define GPSR1_20 F_(CS0_N, IP4_15_12)
+#define GPSR1_19 F_(A19, IP4_11_8)
+#define GPSR1_18 F_(A18, IP4_7_4)
+#define GPSR1_17 F_(A17, IP4_3_0)
+#define GPSR1_16 F_(A16, IP3_31_28)
+#define GPSR1_15 F_(A15, IP3_27_24)
+#define GPSR1_14 F_(A14, IP3_23_20)
+#define GPSR1_13 F_(A13, IP3_19_16)
+#define GPSR1_12 F_(A12, IP3_15_12)
+#define GPSR1_11 F_(A11, IP3_11_8)
+#define GPSR1_10 F_(A10, IP3_7_4)
+#define GPSR1_9 F_(A9, IP3_3_0)
+#define GPSR1_8 F_(A8, IP2_31_28)
+#define GPSR1_7 F_(A7, IP2_27_24)
+#define GPSR1_6 F_(A6, IP2_23_20)
+#define GPSR1_5 F_(A5, IP2_19_16)
+#define GPSR1_4 F_(A4, IP2_15_12)
+#define GPSR1_3 F_(A3, IP2_11_8)
+#define GPSR1_2 F_(A2, IP2_7_4)
+#define GPSR1_1 F_(A1, IP2_3_0)
+#define GPSR1_0 F_(A0, IP1_31_28)
+
+/* GPSR2 */
+#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
+#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
+#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
+#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
+#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
+#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
+#define GPSR2_8 F_(PWM2_A, IP1_27_24)
+#define GPSR2_7 F_(PWM1_A, IP1_23_20)
+#define GPSR2_6 F_(PWM0, IP1_19_16)
+#define GPSR2_5 F_(IRQ5, IP1_15_12)
+#define GPSR2_4 F_(IRQ4, IP1_11_8)
+#define GPSR2_3 F_(IRQ3, IP1_7_4)
+#define GPSR2_2 F_(IRQ2, IP1_3_0)
+#define GPSR2_1 F_(IRQ1, IP0_31_28)
+#define GPSR2_0 F_(IRQ0, IP0_27_24)
+
+/* GPSR3 */
+#define GPSR3_15 F_(SD1_WP, IP11_23_20)
+#define GPSR3_14 F_(SD1_CD, IP11_19_16)
+#define GPSR3_13 F_(SD0_WP, IP11_15_12)
+#define GPSR3_12 F_(SD0_CD, IP11_11_8)
+#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
+#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
+#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
+#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
+#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
+#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
+#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
+#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
+#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
+#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
+#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
+#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
+
+/* GPSR4 */
+#define GPSR4_17 F_(SD3_DS, IP11_7_4)
+#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
+#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
+#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
+#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
+#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
+#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
+#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
+#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
+#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
+#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
+#define GPSR4_6 F_(SD2_DS, IP9_27_24)
+#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
+#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
+#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
+#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
+#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
+#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
+
+/* GPSR5 */
+#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
+#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
+#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
+#define GPSR5_22 FM(MSIOF0_RXD)
+#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
+#define GPSR5_20 FM(MSIOF0_TXD)
+#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
+#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
+#define GPSR5_17 FM(MSIOF0_SCK)
+#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
+#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
+#define GPSR5_14 F_(HTX0, IP13_19_16)
+#define GPSR5_13 F_(HRX0, IP13_15_12)
+#define GPSR5_12 F_(HSCK0, IP13_11_8)
+#define GPSR5_11 F_(RX2_A, IP13_7_4)
+#define GPSR5_10 F_(TX2_A, IP13_3_0)
+#define GPSR5_9 F_(SCK2, IP12_31_28)
+#define GPSR5_8 F_(RTS1_N, IP12_27_24)
+#define GPSR5_7 F_(CTS1_N, IP12_23_20)
+#define GPSR5_6 F_(TX1_A, IP12_19_16)
+#define GPSR5_5 F_(RX1_A, IP12_15_12)
+#define GPSR5_4 F_(RTS0_N, IP12_11_8)
+#define GPSR5_3 F_(CTS0_N, IP12_7_4)
+#define GPSR5_2 F_(TX0, IP12_3_0)
+#define GPSR5_1 F_(RX0, IP11_31_28)
+#define GPSR5_0 F_(SCK0, IP11_27_24)
+
+/* GPSR6 */
+#define GPSR6_31 F_(GP6_31, IP18_7_4)
+#define GPSR6_30 F_(GP6_30, IP18_3_0)
+#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
+#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
+#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
+#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
+#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
+#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
+#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
+#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
+#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
+#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
+#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
+#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
+#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
+#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
+#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
+#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
+#define GPSR6_13 FM(SSI_SDATA5)
+#define GPSR6_12 FM(SSI_WS5)
+#define GPSR6_11 FM(SSI_SCK5)
+#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
+#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
+#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
+#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
+#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
+#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
+#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
+#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
+#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
+#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
+#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
+
+/* GPSR7 */
+#define GPSR7_3 FM(GP7_03)
+#define GPSR7_2 FM(HDMI0_CEC)
+#define GPSR7_1 FM(AVS2)
+#define GPSR7_0 FM(AVS1)
+
+
+/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
+#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
+#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
+#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
+#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
+#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
+#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
+#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
+#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
+#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
+#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
+#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
+#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
+
+#define PINMUX_GPSR \
+\
+ GPSR6_31 \
+ GPSR6_30 \
+ GPSR6_29 \
+ GPSR1_28 GPSR6_28 \
+ GPSR1_27 GPSR6_27 \
+ GPSR1_26 GPSR6_26 \
+ GPSR1_25 GPSR5_25 GPSR6_25 \
+ GPSR1_24 GPSR5_24 GPSR6_24 \
+ GPSR1_23 GPSR5_23 GPSR6_23 \
+ GPSR1_22 GPSR5_22 GPSR6_22 \
+ GPSR1_21 GPSR5_21 GPSR6_21 \
+ GPSR1_20 GPSR5_20 GPSR6_20 \
+ GPSR1_19 GPSR5_19 GPSR6_19 \
+ GPSR1_18 GPSR5_18 GPSR6_18 \
+ GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
+ GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
+GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
+GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
+GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
+GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
+GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
+GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
+GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
+GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
+GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
+GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
+GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
+GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
+GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
+GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
+GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
+GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
+
+#define PINMUX_IPSR \
+\
+FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
+FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
+FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
+FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
+FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
+FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
+FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
+FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
+\
+FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
+FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
+FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
+FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
+FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
+FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
+FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
+FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
+\
+FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
+FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
+FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
+FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
+FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
+FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
+FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
+FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
+\
+FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
+FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
+FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
+FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
+FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
+FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
+FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
+FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
+\
+FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
+FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
+FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
+FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
+FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
+FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
+FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
+FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
+
+/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
+#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
+#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
+#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
+#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
+#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
+#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
+#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
+#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
+#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
+#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
+#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
+#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
+#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
+#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
+#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
+#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
+#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
+#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
+
+/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
+#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
+#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
+#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
+#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
+#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
+#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
+#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
+#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
+#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
+#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
+#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
+#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
+#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
+#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
+#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
+#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
+#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
+#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
+#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
+#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
+#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
+#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
+
+/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
+#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
+#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
+#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
+#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
+#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
+#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
+#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
+#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
+#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
+#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
+#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
+#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
+
+#define PINMUX_MOD_SELS \
+\
+MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
+ MOD_SEL2_30 \
+ MOD_SEL1_29_28_27 MOD_SEL2_29 \
+MOD_SEL0_28_27 MOD_SEL2_28_27 \
+MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
+ MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
+MOD_SEL0_23 MOD_SEL1_23_22_21 \
+MOD_SEL0_22 MOD_SEL2_22 \
+MOD_SEL0_21 MOD_SEL2_21 \
+MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
+MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
+MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
+ MOD_SEL2_17 \
+MOD_SEL0_16 MOD_SEL1_16 \
+ MOD_SEL1_15_14 \
+MOD_SEL0_14_13 \
+ MOD_SEL1_13 \
+MOD_SEL0_12 MOD_SEL1_12 \
+MOD_SEL0_11 MOD_SEL1_11 \
+MOD_SEL0_10 MOD_SEL1_10 \
+MOD_SEL0_9_8 MOD_SEL1_9 \
+MOD_SEL0_7_6 \
+ MOD_SEL1_6 \
+MOD_SEL0_5 MOD_SEL1_5 \
+MOD_SEL0_4_3 MOD_SEL1_4 \
+ MOD_SEL1_3 \
+ MOD_SEL1_2 \
+ MOD_SEL1_1 \
+ MOD_SEL1_0 MOD_SEL2_0
+
+/*
+ * These pins are not able to be muxed but have other properties
+ * that can be set, such as drive-strength or pull-up/pull-down enable.
+ */
+#define PINMUX_STATIC \
+ FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
+ FM(QSPI0_IO2) FM(QSPI0_IO3) \
+ FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
+ FM(QSPI1_IO2) FM(QSPI1_IO3) \
+ FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
+ FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
+ FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
+ FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
+ FM(PRESETOUT) \
+ FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
+ FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
+
+enum {
+ PINMUX_RESERVED = 0,
+
+ PINMUX_DATA_BEGIN,
+ GP_ALL(DATA),
+ PINMUX_DATA_END,
+
+#define F_(x, y)
+#define FM(x) FN_##x,
+ PINMUX_FUNCTION_BEGIN,
+ GP_ALL(FN),
+ PINMUX_GPSR
+ PINMUX_IPSR
+ PINMUX_MOD_SELS
+ PINMUX_FUNCTION_END,
+#undef F_
+#undef FM
+
+#define F_(x, y)
+#define FM(x) x##_MARK,
+ PINMUX_MARK_BEGIN,
+ PINMUX_GPSR
+ PINMUX_IPSR
+ PINMUX_MOD_SELS
+ PINMUX_STATIC
+ PINMUX_MARK_END,
+#undef F_
+#undef FM
+};
+
+static const u16 pinmux_data[] = {
+ PINMUX_DATA_GP_ALL(),
+
+ PINMUX_SINGLE(AVS1),
+ PINMUX_SINGLE(AVS2),
+ PINMUX_SINGLE(CLKOUT),
+ PINMUX_SINGLE(GP7_03),
+ PINMUX_SINGLE(HDMI0_CEC),
+ PINMUX_SINGLE(MSIOF0_RXD),
+ PINMUX_SINGLE(MSIOF0_SCK),
+ PINMUX_SINGLE(MSIOF0_TXD),
+ PINMUX_SINGLE(SSI_SCK5),
+ PINMUX_SINGLE(SSI_SDATA5),
+ PINMUX_SINGLE(SSI_WS5),
+
+ /* IPSR0 */
+ PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
+ PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
+
+ PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
+ PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
+ PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
+
+ PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
+ PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
+ PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
+
+ PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
+ PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
+ PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
+ PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
+
+ PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
+ PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
+ PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
+
+ PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
+ PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
+ PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
+
+ PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
+ PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
+ PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
+ PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
+ PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
+ PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
+ PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
+
+ PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
+ PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
+ PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
+ PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
+ PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
+ PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
+ PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
+
+ /* IPSR1 */
+ PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
+ PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
+ PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
+ PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
+ PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
+ PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
+
+ PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
+ PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
+ PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
+ PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
+ PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
+ PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
+
+ PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
+ PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
+ PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
+ PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
+ PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
+ PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
+
+ PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
+ PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
+ PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
+ PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
+ PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
+ PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
+ PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
+
+ PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
+ PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
+ PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
+ PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
+
+ PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
+ PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
+ PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
+ PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
+
+ PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
+ PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
+ PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
+
+ PINMUX_IPSR_GPSR(IP1_31_28, A0),
+ PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
+ PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
+ PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
+ PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
+ PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
+
+ /* IPSR2 */
+ PINMUX_IPSR_GPSR(IP2_3_0, A1),
+ PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
+ PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
+ PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
+ PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
+ PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
+
+ PINMUX_IPSR_GPSR(IP2_7_4, A2),
+ PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
+ PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
+ PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
+ PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
+ PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
+
+ PINMUX_IPSR_GPSR(IP2_11_8, A3),
+ PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
+ PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
+ PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
+ PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
+ PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
+
+ PINMUX_IPSR_GPSR(IP2_15_12, A4),
+ PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
+ PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
+ PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
+ PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
+ PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
+
+ PINMUX_IPSR_GPSR(IP2_19_16, A5),
+ PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
+ PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
+ PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
+ PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
+ PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
+ PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
+
+ PINMUX_IPSR_GPSR(IP2_23_20, A6),
+ PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
+ PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
+ PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
+ PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
+ PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
+ PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
+
+ PINMUX_IPSR_GPSR(IP2_27_24, A7),
+ PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
+ PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
+ PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
+ PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
+ PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
+ PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
+
+ PINMUX_IPSR_GPSR(IP2_31_28, A8),
+ PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
+ PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
+ PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
+ PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
+ PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
+ PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
+
+ /* IPSR3 */
+ PINMUX_IPSR_GPSR(IP3_3_0, A9),
+ PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
+ PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
+ PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
+
+ PINMUX_IPSR_GPSR(IP3_7_4, A10),
+ PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
+ PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
+ PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
+
+ PINMUX_IPSR_GPSR(IP3_11_8, A11),
+ PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
+ PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
+ PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
+ PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
+ PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
+ PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
+ PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
+ PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
+
+ PINMUX_IPSR_GPSR(IP3_15_12, A12),
+ PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
+ PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
+ PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
+ PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
+ PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
+
+ PINMUX_IPSR_GPSR(IP3_19_16, A13),
+ PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
+ PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
+ PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
+ PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
+ PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
+
+ PINMUX_IPSR_GPSR(IP3_23_20, A14),
+ PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
+ PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
+ PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
+ PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
+ PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
+
+ PINMUX_IPSR_GPSR(IP3_27_24, A15),
+ PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
+ PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
+ PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
+ PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
+ PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
+
+ PINMUX_IPSR_GPSR(IP3_31_28, A16),
+ PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
+ PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
+ PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
+
+ /* IPSR4 */
+ PINMUX_IPSR_GPSR(IP4_3_0, A17),
+ PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
+ PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
+ PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
+
+ PINMUX_IPSR_GPSR(IP4_7_4, A18),
+ PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
+ PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
+ PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
+
+ PINMUX_IPSR_GPSR(IP4_11_8, A19),
+ PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
+ PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
+ PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
+
+ PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
+ PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
+
+ PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
+ PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
+ PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
+
+ PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
+ PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
+ PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
+ PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
+ PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
+ PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
+ PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
+ PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
+
+ PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
+ PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
+ PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
+ PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
+ PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
+ PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
+
+ PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
+ PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
+ PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
+ PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
+ PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
+ PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
+
+ /* IPSR5 */
+ PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
+ PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
+ PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
+ PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
+ PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
+ PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
+ PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
+
+ PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
+ PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
+ PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
+ PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
+ PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
+ PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
+ PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
+ PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
+
+ PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
+ PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
+ PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
+ PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
+
+ PINMUX_IPSR_GPSR(IP5_15_12, D0),
+ PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
+ PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
+ PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
+ PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
+
+ PINMUX_IPSR_GPSR(IP5_19_16, D1),
+ PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
+ PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
+ PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
+ PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
+
+ PINMUX_IPSR_GPSR(IP5_23_20, D2),
+ PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
+ PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
+ PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
+
+ PINMUX_IPSR_GPSR(IP5_27_24, D3),
+ PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
+ PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
+ PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
+
+ PINMUX_IPSR_GPSR(IP5_31_28, D4),
+ PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
+ PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
+ PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
+
+ /* IPSR6 */
+ PINMUX_IPSR_GPSR(IP6_3_0, D5),
+ PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
+ PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
+ PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
+
+ PINMUX_IPSR_GPSR(IP6_7_4, D6),
+ PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
+ PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
+ PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
+
+ PINMUX_IPSR_GPSR(IP6_11_8, D7),
+ PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
+ PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
+ PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
+
+ PINMUX_IPSR_GPSR(IP6_15_12, D8),
+ PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
+ PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
+ PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
+ PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
+ PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
+
+ PINMUX_IPSR_GPSR(IP6_19_16, D9),
+ PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
+ PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
+ PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
+ PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
+
+ PINMUX_IPSR_GPSR(IP6_23_20, D10),
+ PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
+ PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
+ PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
+ PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
+ PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
+ PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
+
+ PINMUX_IPSR_GPSR(IP6_27_24, D11),
+ PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
+ PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
+ PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
+ PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
+ PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
+ PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
+
+ PINMUX_IPSR_GPSR(IP6_31_28, D12),
+ PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
+ PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
+ PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
+ PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
+ PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
+
+ /* IPSR7 */
+ PINMUX_IPSR_GPSR(IP7_3_0, D13),
+ PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
+ PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
+ PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
+ PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
+ PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
+
+ PINMUX_IPSR_GPSR(IP7_7_4, D14),
+ PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
+ PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
+ PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
+ PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
+ PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
+ PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
+
+ PINMUX_IPSR_GPSR(IP7_11_8, D15),
+ PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
+ PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
+ PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
+ PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
+ PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
+ PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
+
+ PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
+ PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
+ PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
+
+ PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
+ PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
+ PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
+
+ PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
+ PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
+ PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
+ PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
+
+ PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
+ PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
+ PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
+ PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
+
+ /* IPSR8 */
+ PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
+ PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
+ PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
+ PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
+
+ PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
+ PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
+ PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
+ PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
+
+ PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
+ PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
+ PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
+
+ PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
+ PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
+ PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
+ PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
+
+ PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
+ PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
+ PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
+ PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
+ PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
+
+ PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
+ PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
+ PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
+ PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
+ PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
+
+ PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
+ PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
+ PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
+ PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
+ PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
+
+ PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
+ PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
+ PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
+ PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
+ PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
+
+ /* IPSR9 */
+ PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
+ PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
+
+ PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
+ PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
+
+ PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
+ PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
+
+ PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
+ PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
+
+ PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
+ PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
+
+ PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
+ PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
+
+ PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
+ PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
+ PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
+
+ PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
+ PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
+
+ /* IPSR10 */
+ PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
+ PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
+
+ PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
+ PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
+
+ PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
+ PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
+
+ PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
+ PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
+
+ PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
+ PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
+
+ PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
+ PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
+ PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
+
+ PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
+ PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
+ PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
+
+ PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
+ PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
+ PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
+
+ /* IPSR11 */
+ PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
+ PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
+ PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
+
+ PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
+ PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
+
+ PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
+ PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
+ PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
+
+ PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
+ PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
+
+ PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
+ PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
+
+ PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
+ PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
+
+ PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
+ PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
+ PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
+ PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
+ PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
+ PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
+ PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
+ PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
+ PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
+ PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
+
+ PINMUX_IPSR_GPSR(IP11_31_28, RX0),
+ PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
+ PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
+ PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
+ PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
+
+ /* IPSR12 */
+ PINMUX_IPSR_GPSR(IP12_3_0, TX0),
+ PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
+ PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
+ PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
+ PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
+
+ PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
+ PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
+ PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
+ PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
+ PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
+ PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
+ PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
+ PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
+
+ PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
+ PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
+ PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
+ PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
+ PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
+ PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
+ PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
+ PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
+
+ PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
+ PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
+ PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
+ PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
+ PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
+
+ PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
+ PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
+ PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
+ PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
+ PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
+
+ PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
+ PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
+ PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
+ PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
+ PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
+ PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
+ PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
+
+ PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
+ PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
+ PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
+ PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
+ PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
+ PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
+ PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
+
+ PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
+ PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
+ PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
+ PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
+ PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
+ PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
+ PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
+
+ /* IPSR13 */
+ PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
+ PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
+ PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
+ PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
+ PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
+ PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
+
+ PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
+ PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
+ PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
+ PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
+ PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
+ PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
+
+ PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
+ PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
+ PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
+ PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
+ PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
+ PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
+ PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
+ PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
+
+ PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
+ PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
+ PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
+ PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
+ PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
+ PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
+
+ PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
+ PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
+ PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
+ PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
+ PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
+ PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
+
+ PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
+ PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
+ PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
+ PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
+ PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
+ PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
+ PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
+ PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
+
+ PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
+ PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
+ PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
+ PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
+ PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
+ PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
+ PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
+
+ PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
+ PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
+ PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
+ PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
+
+ /* IPSR14 */
+ PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
+ PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
+ PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
+ PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
+ PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
+ PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
+ PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
+
+ PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
+ PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
+ PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
+ PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
+ PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
+ PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
+ PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
+ PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
+
+ PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
+ PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
+ PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
+
+ PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
+ PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
+ PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
+ PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
+
+ PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
+ PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
+ PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
+
+ PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
+ PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
+
+ PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
+ PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
+
+ PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
+ PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
+
+ /* IPSR15 */
+ PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
+
+ PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
+ PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
+
+ PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
+ PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
+ PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
+
+ PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
+ PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
+ PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
+ PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
+
+ PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
+ PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
+ PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
+ PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
+ PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
+ PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
+ PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
+
+ PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
+ PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
+ PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
+ PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
+ PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
+ PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
+ PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
+
+ PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
+ PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
+ PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
+ PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
+ PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
+ PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
+ PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
+
+ PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
+ PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
+ PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
+ PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
+ PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
+ PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
+ PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
+
+ /* IPSR16 */
+ PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
+ PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
+
+ PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
+ PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
+
+ PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
+ PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
+ PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
+
+ PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
+ PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
+ PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
+ PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
+ PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
+ PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
+ PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
+
+ PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
+ PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
+ PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
+ PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
+ PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
+ PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
+ PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
+
+ PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
+ PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
+ PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
+ PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
+ PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
+ PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
+ PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
+ PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
+
+ PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
+ PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
+ PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
+ PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
+ PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
+ PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
+ PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
+
+ PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
+ PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
+ PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
+ PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
+ PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
+ PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
+ PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
+ PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
+
+ /* IPSR17 */
+ PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
+ PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
+
+ PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
+ PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
+ PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
+ PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
+ PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
+
+ PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
+ PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
+ PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
+ PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
+ PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
+ PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
+ PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
+
+ PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
+ PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
+ PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
+ PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
+ PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
+ PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
+
+ PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
+ PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
+ PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
+ PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
+ PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
+ PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
+ PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
+ PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
+ PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
+
+ PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
+ PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
+ PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
+ PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
+ PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
+ PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
+ PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
+ PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
+ PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
+
+ PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
+ PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
+ PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
+ PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
+ PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
+ PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
+ PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
+ PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
+ PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
+ PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
+ PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
+
+ PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
+ PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
+ PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
+ PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
+ PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
+ PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
+ PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
+ PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
+ PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
+
+ /* IPSR18 */
+ PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
+ PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
+ PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
+ PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
+ PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
+ PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
+ PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
+ PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
+ PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
+
+ PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
+ PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
+ PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
+ PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
+ PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
+ PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
+ PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
+ PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
+ PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
+
+ /* I2C */
+ PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
+ PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
+ PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
+
+/*
+ * Static pins can not be muxed between different functions but
+ * still needs a mark entry in the pinmux list. Add each static
+ * pin to the list without an associated function. The sh-pfc
+ * core will do the right thing and skip trying to mux then pin
+ * while still applying configuration to it
+ */
+#define FM(x) PINMUX_DATA(x##_MARK, 0),
+ PINMUX_STATIC
+#undef FM
+};
+
+/*
+ * R8A77965 has 8 banks with 32 GPIOs in each => 256 GPIOs.
+ * Physical layout rows: A - AW, cols: 1 - 39.
+ */
+#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
+#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
+#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
+#define PIN_NONE U16_MAX
+
+static const struct sh_pfc_pin pinmux_pins[] = {
+ PINMUX_GPIO_GP_ALL(),
+
+ /*
+ * Pins not associated with a GPIO port.
+ *
+ * The pin positions are different between different r8a77965
+ * packages, all that is needed for the pfc driver is a unique
+ * number for each pin. To this end use the pin layout from
+ * R-Car M3SiP to calculate a unique number for each pin.
+ */
+ SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
+ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
+ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
+ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
+ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
+ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
+ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
+};
+
+/* - EtherAVB --------------------------------------------------------------- */
+static const unsigned int avb_link_pins[] = {
+ /* AVB_LINK */
+ RCAR_GP_PIN(2, 12),
+};
+static const unsigned int avb_link_mux[] = {
+ AVB_LINK_MARK,
+};
+static const unsigned int avb_magic_pins[] = {
+ /* AVB_MAGIC_ */
+ RCAR_GP_PIN(2, 10),
+};
+static const unsigned int avb_magic_mux[] = {
+ AVB_MAGIC_MARK,
+};
+static const unsigned int avb_phy_int_pins[] = {
+ /* AVB_PHY_INT */
+ RCAR_GP_PIN(2, 11),
+};
+static const unsigned int avb_phy_int_mux[] = {
+ AVB_PHY_INT_MARK,
+};
+static const unsigned int avb_mdio_pins[] = {
+ /* AVB_MDC, AVB_MDIO */
+ RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
+};
+static const unsigned int avb_mdio_mux[] = {
+ AVB_MDC_MARK, AVB_MDIO_MARK,
+};
+static const unsigned int avb_mii_pins[] = {
+ /*
+ * AVB_TX_CTL, AVB_TXC, AVB_TD0,
+ * AVB_TD1, AVB_TD2, AVB_TD3,
+ * AVB_RX_CTL, AVB_RXC, AVB_RD0,
+ * AVB_RD1, AVB_RD2, AVB_RD3,
+ * AVB_TXCREFCLK
+ */
+ PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
+ PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
+ PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
+ PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
+ PIN_NUMBER('A', 12),
+
+};
+static const unsigned int avb_mii_mux[] = {
+ AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
+ AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
+ AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
+ AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
+ AVB_TXCREFCLK_MARK,
+};
+static const unsigned int avb_avtp_pps_pins[] = {
+ /* AVB_AVTP_PPS */
+ RCAR_GP_PIN(2, 6),
+};
+static const unsigned int avb_avtp_pps_mux[] = {
+ AVB_AVTP_PPS_MARK,
+};
+static const unsigned int avb_avtp_match_a_pins[] = {
+ /* AVB_AVTP_MATCH_A */
+ RCAR_GP_PIN(2, 13),
+};
+static const unsigned int avb_avtp_match_a_mux[] = {
+ AVB_AVTP_MATCH_A_MARK,
+};
+static const unsigned int avb_avtp_capture_a_pins[] = {
+ /* AVB_AVTP_CAPTURE_A */
+ RCAR_GP_PIN(2, 14),
+};
+static const unsigned int avb_avtp_capture_a_mux[] = {
+ AVB_AVTP_CAPTURE_A_MARK,
+};
+static const unsigned int avb_avtp_match_b_pins[] = {
+ /* AVB_AVTP_MATCH_B */
+ RCAR_GP_PIN(1, 8),
+};
+static const unsigned int avb_avtp_match_b_mux[] = {
+ AVB_AVTP_MATCH_B_MARK,
+};
+static const unsigned int avb_avtp_capture_b_pins[] = {
+ /* AVB_AVTP_CAPTURE_B */
+ RCAR_GP_PIN(1, 11),
+};
+static const unsigned int avb_avtp_capture_b_mux[] = {
+ AVB_AVTP_CAPTURE_B_MARK,
+};
+
+/* - INTC-EX ---------------------------------------------------------------- */
+static const unsigned int intc_ex_irq0_pins[] = {
+ /* IRQ0 */
+ RCAR_GP_PIN(2, 0),
+};
+static const unsigned int intc_ex_irq0_mux[] = {
+ IRQ0_MARK,
+};
+static const unsigned int intc_ex_irq1_pins[] = {
+ /* IRQ1 */
+ RCAR_GP_PIN(2, 1),
+};
+static const unsigned int intc_ex_irq1_mux[] = {
+ IRQ1_MARK,
+};
+static const unsigned int intc_ex_irq2_pins[] = {
+ /* IRQ2 */
+ RCAR_GP_PIN(2, 2),
+};
+static const unsigned int intc_ex_irq2_mux[] = {
+ IRQ2_MARK,
+};
+static const unsigned int intc_ex_irq3_pins[] = {
+ /* IRQ3 */
+ RCAR_GP_PIN(2, 3),
+};
+static const unsigned int intc_ex_irq3_mux[] = {
+ IRQ3_MARK,
+};
+static const unsigned int intc_ex_irq4_pins[] = {
+ /* IRQ4 */
+ RCAR_GP_PIN(2, 4),
+};
+static const unsigned int intc_ex_irq4_mux[] = {
+ IRQ4_MARK,
+};
+static const unsigned int intc_ex_irq5_pins[] = {
+ /* IRQ5 */
+ RCAR_GP_PIN(2, 5),
+};
+static const unsigned int intc_ex_irq5_mux[] = {
+ IRQ5_MARK,
+};
+
+/* - SCIF0 ------------------------------------------------------------------ */
+static const unsigned int scif0_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
+};
+static const unsigned int scif0_data_mux[] = {
+ RX0_MARK, TX0_MARK,
+};
+static const unsigned int scif0_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 0),
+};
+static const unsigned int scif0_clk_mux[] = {
+ SCK0_MARK,
+};
+static const unsigned int scif0_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
+};
+static const unsigned int scif0_ctrl_mux[] = {
+ RTS0_N_MARK, CTS0_N_MARK,
+};
+/* - SCIF1 ------------------------------------------------------------------ */
+static const unsigned int scif1_data_a_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
+};
+static const unsigned int scif1_data_a_mux[] = {
+ RX1_A_MARK, TX1_A_MARK,
+};
+static const unsigned int scif1_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(6, 21),
+};
+static const unsigned int scif1_clk_mux[] = {
+ SCK1_MARK,
+};
+static const unsigned int scif1_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
+};
+static const unsigned int scif1_ctrl_mux[] = {
+ RTS1_N_MARK, CTS1_N_MARK,
+};
+static const unsigned int scif1_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
+};
+static const unsigned int scif1_data_b_mux[] = {
+ RX1_B_MARK, TX1_B_MARK,
+};
+/* - SCIF2 ------------------------------------------------------------------ */
+static const unsigned int scif2_data_a_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
+};
+static const unsigned int scif2_data_a_mux[] = {
+ RX2_A_MARK, TX2_A_MARK,
+};
+static const unsigned int scif2_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 9),
+};
+static const unsigned int scif2_clk_mux[] = {
+ SCK2_MARK,
+};
+static const unsigned int scif2_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
+};
+static const unsigned int scif2_data_b_mux[] = {
+ RX2_B_MARK, TX2_B_MARK,
+};
+/* - SCIF3 ------------------------------------------------------------------ */
+static const unsigned int scif3_data_a_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
+};
+static const unsigned int scif3_data_a_mux[] = {
+ RX3_A_MARK, TX3_A_MARK,
+};
+static const unsigned int scif3_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(1, 22),
+};
+static const unsigned int scif3_clk_mux[] = {
+ SCK3_MARK,
+};
+static const unsigned int scif3_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
+};
+static const unsigned int scif3_ctrl_mux[] = {
+ RTS3_N_MARK, CTS3_N_MARK,
+};
+static const unsigned int scif3_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
+};
+static const unsigned int scif3_data_b_mux[] = {
+ RX3_B_MARK, TX3_B_MARK,
+};
+/* - SCIF4 ------------------------------------------------------------------ */
+static const unsigned int scif4_data_a_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
+};
+static const unsigned int scif4_data_a_mux[] = {
+ RX4_A_MARK, TX4_A_MARK,
+};
+static const unsigned int scif4_clk_a_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(2, 10),
+};
+static const unsigned int scif4_clk_a_mux[] = {
+ SCK4_A_MARK,
+};
+static const unsigned int scif4_ctrl_a_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
+};
+static const unsigned int scif4_ctrl_a_mux[] = {
+ RTS4_N_A_MARK, CTS4_N_A_MARK,
+};
+static const unsigned int scif4_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+};
+static const unsigned int scif4_data_b_mux[] = {
+ RX4_B_MARK, TX4_B_MARK,
+};
+static const unsigned int scif4_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(1, 5),
+};
+static const unsigned int scif4_clk_b_mux[] = {
+ SCK4_B_MARK,
+};
+static const unsigned int scif4_ctrl_b_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
+};
+static const unsigned int scif4_ctrl_b_mux[] = {
+ RTS4_N_B_MARK, CTS4_N_B_MARK,
+};
+static const unsigned int scif4_data_c_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+};
+static const unsigned int scif4_data_c_mux[] = {
+ RX4_C_MARK, TX4_C_MARK,
+};
+static const unsigned int scif4_clk_c_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(0, 8),
+};
+static const unsigned int scif4_clk_c_mux[] = {
+ SCK4_C_MARK,
+};
+static const unsigned int scif4_ctrl_c_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
+};
+static const unsigned int scif4_ctrl_c_mux[] = {
+ RTS4_N_C_MARK, CTS4_N_C_MARK,
+};
+/* - SCIF5 ------------------------------------------------------------------ */
+static const unsigned int scif5_data_a_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
+};
+static const unsigned int scif5_data_a_mux[] = {
+ RX5_A_MARK, TX5_A_MARK,
+};
+static const unsigned int scif5_clk_a_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(6, 21),
+};
+static const unsigned int scif5_clk_a_mux[] = {
+ SCK5_A_MARK,
+};
+static const unsigned int scif5_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
+};
+static const unsigned int scif5_data_b_mux[] = {
+ RX5_B_MARK, TX5_B_MARK,
+};
+static const unsigned int scif5_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 0),
+};
+static const unsigned int scif5_clk_b_mux[] = {
+ SCK5_B_MARK,
+};
+/* - SCIF Clock ------------------------------------------------------------- */
+static const unsigned int scif_clk_a_pins[] = {
+ /* SCIF_CLK */
+ RCAR_GP_PIN(6, 23),
+};
+static const unsigned int scif_clk_a_mux[] = {
+ SCIF_CLK_A_MARK,
+};
+static const unsigned int scif_clk_b_pins[] = {
+ /* SCIF_CLK */
+ RCAR_GP_PIN(5, 9),
+};
+static const unsigned int scif_clk_b_mux[] = {
+ SCIF_CLK_B_MARK,
+};
+
+/* - USB0 ------------------------------------------------------------------- */
+static const unsigned int usb0_pins[] = {
+ /* PWEN, OVC */
+ RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
+};
+
+static const unsigned int usb0_mux[] = {
+ USB0_PWEN_MARK, USB0_OVC_MARK,
+};
+
+/* - USB1 ------------------------------------------------------------------- */
+static const unsigned int usb1_pins[] = {
+ /* PWEN, OVC */
+ RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
+};
+
+static const unsigned int usb1_mux[] = {
+ USB1_PWEN_MARK, USB1_OVC_MARK,
+};
+
+/* - USB30 ------------------------------------------------------------------ */
+static const unsigned int usb30_pins[] = {
+ /* PWEN, OVC */
+ RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
+};
+
+static const unsigned int usb30_mux[] = {
+ USB30_PWEN_MARK, USB30_OVC_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(avb_link),
+ SH_PFC_PIN_GROUP(avb_magic),
+ SH_PFC_PIN_GROUP(avb_phy_int),
+ SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
+ SH_PFC_PIN_GROUP(avb_mdio),
+ SH_PFC_PIN_GROUP(avb_mii),
+ SH_PFC_PIN_GROUP(avb_avtp_pps),
+ SH_PFC_PIN_GROUP(avb_avtp_match_a),
+ SH_PFC_PIN_GROUP(avb_avtp_capture_a),
+ SH_PFC_PIN_GROUP(avb_avtp_match_b),
+ SH_PFC_PIN_GROUP(avb_avtp_capture_b),
+ SH_PFC_PIN_GROUP(intc_ex_irq0),
+ SH_PFC_PIN_GROUP(intc_ex_irq1),
+ SH_PFC_PIN_GROUP(intc_ex_irq2),
+ SH_PFC_PIN_GROUP(intc_ex_irq3),
+ SH_PFC_PIN_GROUP(intc_ex_irq4),
+ SH_PFC_PIN_GROUP(intc_ex_irq5),
+ SH_PFC_PIN_GROUP(scif0_data),
+ SH_PFC_PIN_GROUP(scif0_clk),
+ SH_PFC_PIN_GROUP(scif0_ctrl),
+ SH_PFC_PIN_GROUP(scif1_data_a),
+ SH_PFC_PIN_GROUP(scif1_clk),
+ SH_PFC_PIN_GROUP(scif1_ctrl),
+ SH_PFC_PIN_GROUP(scif1_data_b),
+ SH_PFC_PIN_GROUP(scif2_data_a),
+ SH_PFC_PIN_GROUP(scif2_clk),
+ SH_PFC_PIN_GROUP(scif2_data_b),
+ SH_PFC_PIN_GROUP(scif3_data_a),
+ SH_PFC_PIN_GROUP(scif3_clk),
+ SH_PFC_PIN_GROUP(scif3_ctrl),
+ SH_PFC_PIN_GROUP(scif3_data_b),
+ SH_PFC_PIN_GROUP(scif4_data_a),
+ SH_PFC_PIN_GROUP(scif4_clk_a),
+ SH_PFC_PIN_GROUP(scif4_ctrl_a),
+ SH_PFC_PIN_GROUP(scif4_data_b),
+ SH_PFC_PIN_GROUP(scif4_clk_b),
+ SH_PFC_PIN_GROUP(scif4_ctrl_b),
+ SH_PFC_PIN_GROUP(scif4_data_c),
+ SH_PFC_PIN_GROUP(scif4_clk_c),
+ SH_PFC_PIN_GROUP(scif4_ctrl_c),
+ SH_PFC_PIN_GROUP(scif5_data_a),
+ SH_PFC_PIN_GROUP(scif5_clk_a),
+ SH_PFC_PIN_GROUP(scif5_data_b),
+ SH_PFC_PIN_GROUP(scif5_clk_b),
+ SH_PFC_PIN_GROUP(scif_clk_a),
+ SH_PFC_PIN_GROUP(scif_clk_b),
+ SH_PFC_PIN_GROUP(usb0),
+ SH_PFC_PIN_GROUP(usb1),
+ SH_PFC_PIN_GROUP(usb30),
+};
+
+static const char * const avb_groups[] = {
+ "avb_link",
+ "avb_magic",
+ "avb_phy_int",
+ "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
+ "avb_mdio",
+ "avb_mii",
+ "avb_avtp_pps",
+ "avb_avtp_match_a",
+ "avb_avtp_capture_a",
+ "avb_avtp_match_b",
+ "avb_avtp_capture_b",
+};
+
+static const char * const intc_ex_groups[] = {
+ "intc_ex_irq0",
+ "intc_ex_irq1",
+ "intc_ex_irq2",
+ "intc_ex_irq3",
+ "intc_ex_irq4",
+ "intc_ex_irq5",
+};
+
+static const char * const scif0_groups[] = {
+ "scif0_data",
+ "scif0_clk",
+ "scif0_ctrl",
+};
+
+static const char * const scif1_groups[] = {
+ "scif1_data_a",
+ "scif1_clk",
+ "scif1_ctrl",
+ "scif1_data_b",
+};
+static const char * const scif2_groups[] = {
+ "scif2_data_a",
+ "scif2_clk",
+ "scif2_data_b",
+};
+
+static const char * const scif3_groups[] = {
+ "scif3_data_a",
+ "scif3_clk",
+ "scif3_ctrl",
+ "scif3_data_b",
+};
+
+static const char * const scif4_groups[] = {
+ "scif4_data_a",
+ "scif4_clk_a",
+ "scif4_ctrl_a",
+ "scif4_data_b",
+ "scif4_clk_b",
+ "scif4_ctrl_b",
+ "scif4_data_c",
+ "scif4_clk_c",
+ "scif4_ctrl_c",
+};
+
+static const char * const scif5_groups[] = {
+ "scif5_data_a",
+ "scif5_clk_a",
+ "scif5_data_b",
+ "scif5_clk_b",
+};
+
+static const char * const scif_clk_groups[] = {
+ "scif_clk_a",
+ "scif_clk_b",
+};
+
+static const char * const usb0_groups[] = {
+ "usb0",
+};
+
+static const char * const usb1_groups[] = {
+ "usb1",
+};
+
+static const char * const usb30_groups[] = {
+ "usb30",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(avb),
+ SH_PFC_FUNCTION(intc_ex),
+ SH_PFC_FUNCTION(scif0),
+ SH_PFC_FUNCTION(scif1),
+ SH_PFC_FUNCTION(scif2),
+ SH_PFC_FUNCTION(scif3),
+ SH_PFC_FUNCTION(scif4),
+ SH_PFC_FUNCTION(scif5),
+ SH_PFC_FUNCTION(scif_clk),
+ SH_PFC_FUNCTION(usb0),
+ SH_PFC_FUNCTION(usb1),
+ SH_PFC_FUNCTION(usb30),
+};
+
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+#define F_(x, y) FN_##y
+#define FM(x) FN_##x
+ { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_0_15_FN, GPSR0_15,
+ GP_0_14_FN, GPSR0_14,
+ GP_0_13_FN, GPSR0_13,
+ GP_0_12_FN, GPSR0_12,
+ GP_0_11_FN, GPSR0_11,
+ GP_0_10_FN, GPSR0_10,
+ GP_0_9_FN, GPSR0_9,
+ GP_0_8_FN, GPSR0_8,
+ GP_0_7_FN, GPSR0_7,
+ GP_0_6_FN, GPSR0_6,
+ GP_0_5_FN, GPSR0_5,
+ GP_0_4_FN, GPSR0_4,
+ GP_0_3_FN, GPSR0_3,
+ GP_0_2_FN, GPSR0_2,
+ GP_0_1_FN, GPSR0_1,
+ GP_0_0_FN, GPSR0_0, }
+ },
+ { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_1_28_FN, GPSR1_28,
+ GP_1_27_FN, GPSR1_27,
+ GP_1_26_FN, GPSR1_26,
+ GP_1_25_FN, GPSR1_25,
+ GP_1_24_FN, GPSR1_24,
+ GP_1_23_FN, GPSR1_23,
+ GP_1_22_FN, GPSR1_22,
+ GP_1_21_FN, GPSR1_21,
+ GP_1_20_FN, GPSR1_20,
+ GP_1_19_FN, GPSR1_19,
+ GP_1_18_FN, GPSR1_18,
+ GP_1_17_FN, GPSR1_17,
+ GP_1_16_FN, GPSR1_16,
+ GP_1_15_FN, GPSR1_15,
+ GP_1_14_FN, GPSR1_14,
+ GP_1_13_FN, GPSR1_13,
+ GP_1_12_FN, GPSR1_12,
+ GP_1_11_FN, GPSR1_11,
+ GP_1_10_FN, GPSR1_10,
+ GP_1_9_FN, GPSR1_9,
+ GP_1_8_FN, GPSR1_8,
+ GP_1_7_FN, GPSR1_7,
+ GP_1_6_FN, GPSR1_6,
+ GP_1_5_FN, GPSR1_5,
+ GP_1_4_FN, GPSR1_4,
+ GP_1_3_FN, GPSR1_3,
+ GP_1_2_FN, GPSR1_2,
+ GP_1_1_FN, GPSR1_1,
+ GP_1_0_FN, GPSR1_0, }
+ },
+ { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_2_14_FN, GPSR2_14,
+ GP_2_13_FN, GPSR2_13,
+ GP_2_12_FN, GPSR2_12,
+ GP_2_11_FN, GPSR2_11,
+ GP_2_10_FN, GPSR2_10,
+ GP_2_9_FN, GPSR2_9,
+ GP_2_8_FN, GPSR2_8,
+ GP_2_7_FN, GPSR2_7,
+ GP_2_6_FN, GPSR2_6,
+ GP_2_5_FN, GPSR2_5,
+ GP_2_4_FN, GPSR2_4,
+ GP_2_3_FN, GPSR2_3,
+ GP_2_2_FN, GPSR2_2,
+ GP_2_1_FN, GPSR2_1,
+ GP_2_0_FN, GPSR2_0, }
+ },
+ { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_3_15_FN, GPSR3_15,
+ GP_3_14_FN, GPSR3_14,
+ GP_3_13_FN, GPSR3_13,
+ GP_3_12_FN, GPSR3_12,
+ GP_3_11_FN, GPSR3_11,
+ GP_3_10_FN, GPSR3_10,
+ GP_3_9_FN, GPSR3_9,
+ GP_3_8_FN, GPSR3_8,
+ GP_3_7_FN, GPSR3_7,
+ GP_3_6_FN, GPSR3_6,
+ GP_3_5_FN, GPSR3_5,
+ GP_3_4_FN, GPSR3_4,
+ GP_3_3_FN, GPSR3_3,
+ GP_3_2_FN, GPSR3_2,
+ GP_3_1_FN, GPSR3_1,
+ GP_3_0_FN, GPSR3_0, }
+ },
+ { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_4_17_FN, GPSR4_17,
+ GP_4_16_FN, GPSR4_16,
+ GP_4_15_FN, GPSR4_15,
+ GP_4_14_FN, GPSR4_14,
+ GP_4_13_FN, GPSR4_13,
+ GP_4_12_FN, GPSR4_12,
+ GP_4_11_FN, GPSR4_11,
+ GP_4_10_FN, GPSR4_10,
+ GP_4_9_FN, GPSR4_9,
+ GP_4_8_FN, GPSR4_8,
+ GP_4_7_FN, GPSR4_7,
+ GP_4_6_FN, GPSR4_6,
+ GP_4_5_FN, GPSR4_5,
+ GP_4_4_FN, GPSR4_4,
+ GP_4_3_FN, GPSR4_3,
+ GP_4_2_FN, GPSR4_2,
+ GP_4_1_FN, GPSR4_1,
+ GP_4_0_FN, GPSR4_0, }
+ },
+ { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_5_25_FN, GPSR5_25,
+ GP_5_24_FN, GPSR5_24,
+ GP_5_23_FN, GPSR5_23,
+ GP_5_22_FN, GPSR5_22,
+ GP_5_21_FN, GPSR5_21,
+ GP_5_20_FN, GPSR5_20,
+ GP_5_19_FN, GPSR5_19,
+ GP_5_18_FN, GPSR5_18,
+ GP_5_17_FN, GPSR5_17,
+ GP_5_16_FN, GPSR5_16,
+ GP_5_15_FN, GPSR5_15,
+ GP_5_14_FN, GPSR5_14,
+ GP_5_13_FN, GPSR5_13,
+ GP_5_12_FN, GPSR5_12,
+ GP_5_11_FN, GPSR5_11,
+ GP_5_10_FN, GPSR5_10,
+ GP_5_9_FN, GPSR5_9,
+ GP_5_8_FN, GPSR5_8,
+ GP_5_7_FN, GPSR5_7,
+ GP_5_6_FN, GPSR5_6,
+ GP_5_5_FN, GPSR5_5,
+ GP_5_4_FN, GPSR5_4,
+ GP_5_3_FN, GPSR5_3,
+ GP_5_2_FN, GPSR5_2,
+ GP_5_1_FN, GPSR5_1,
+ GP_5_0_FN, GPSR5_0, }
+ },
+ { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
+ GP_6_31_FN, GPSR6_31,
+ GP_6_30_FN, GPSR6_30,
+ GP_6_29_FN, GPSR6_29,
+ GP_6_28_FN, GPSR6_28,
+ GP_6_27_FN, GPSR6_27,
+ GP_6_26_FN, GPSR6_26,
+ GP_6_25_FN, GPSR6_25,
+ GP_6_24_FN, GPSR6_24,
+ GP_6_23_FN, GPSR6_23,
+ GP_6_22_FN, GPSR6_22,
+ GP_6_21_FN, GPSR6_21,
+ GP_6_20_FN, GPSR6_20,
+ GP_6_19_FN, GPSR6_19,
+ GP_6_18_FN, GPSR6_18,
+ GP_6_17_FN, GPSR6_17,
+ GP_6_16_FN, GPSR6_16,
+ GP_6_15_FN, GPSR6_15,
+ GP_6_14_FN, GPSR6_14,
+ GP_6_13_FN, GPSR6_13,
+ GP_6_12_FN, GPSR6_12,
+ GP_6_11_FN, GPSR6_11,
+ GP_6_10_FN, GPSR6_10,
+ GP_6_9_FN, GPSR6_9,
+ GP_6_8_FN, GPSR6_8,
+ GP_6_7_FN, GPSR6_7,
+ GP_6_6_FN, GPSR6_6,
+ GP_6_5_FN, GPSR6_5,
+ GP_6_4_FN, GPSR6_4,
+ GP_6_3_FN, GPSR6_3,
+ GP_6_2_FN, GPSR6_2,
+ GP_6_1_FN, GPSR6_1,
+ GP_6_0_FN, GPSR6_0, }
+ },
+ { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_7_3_FN, GPSR7_3,
+ GP_7_2_FN, GPSR7_2,
+ GP_7_1_FN, GPSR7_1,
+ GP_7_0_FN, GPSR7_0, }
+ },
+#undef F_
+#undef FM
+
+#define F_(x, y) x,
+#define FM(x) FN_##x,
+ { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
+ IP0_31_28
+ IP0_27_24
+ IP0_23_20
+ IP0_19_16
+ IP0_15_12
+ IP0_11_8
+ IP0_7_4
+ IP0_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
+ IP1_31_28
+ IP1_27_24
+ IP1_23_20
+ IP1_19_16
+ IP1_15_12
+ IP1_11_8
+ IP1_7_4
+ IP1_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
+ IP2_31_28
+ IP2_27_24
+ IP2_23_20
+ IP2_19_16
+ IP2_15_12
+ IP2_11_8
+ IP2_7_4
+ IP2_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
+ IP3_31_28
+ IP3_27_24
+ IP3_23_20
+ IP3_19_16
+ IP3_15_12
+ IP3_11_8
+ IP3_7_4
+ IP3_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
+ IP4_31_28
+ IP4_27_24
+ IP4_23_20
+ IP4_19_16
+ IP4_15_12
+ IP4_11_8
+ IP4_7_4
+ IP4_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
+ IP5_31_28
+ IP5_27_24
+ IP5_23_20
+ IP5_19_16
+ IP5_15_12
+ IP5_11_8
+ IP5_7_4
+ IP5_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
+ IP6_31_28
+ IP6_27_24
+ IP6_23_20
+ IP6_19_16
+ IP6_15_12
+ IP6_11_8
+ IP6_7_4
+ IP6_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
+ IP7_31_28
+ IP7_27_24
+ IP7_23_20
+ IP7_19_16
+ /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ IP7_11_8
+ IP7_7_4
+ IP7_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
+ IP8_31_28
+ IP8_27_24
+ IP8_23_20
+ IP8_19_16
+ IP8_15_12
+ IP8_11_8
+ IP8_7_4
+ IP8_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
+ IP9_31_28
+ IP9_27_24
+ IP9_23_20
+ IP9_19_16
+ IP9_15_12
+ IP9_11_8
+ IP9_7_4
+ IP9_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
+ IP10_31_28
+ IP10_27_24
+ IP10_23_20
+ IP10_19_16
+ IP10_15_12
+ IP10_11_8
+ IP10_7_4
+ IP10_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
+ IP11_31_28
+ IP11_27_24
+ IP11_23_20
+ IP11_19_16
+ IP11_15_12
+ IP11_11_8
+ IP11_7_4
+ IP11_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
+ IP12_31_28
+ IP12_27_24
+ IP12_23_20
+ IP12_19_16
+ IP12_15_12
+ IP12_11_8
+ IP12_7_4
+ IP12_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
+ IP13_31_28
+ IP13_27_24
+ IP13_23_20
+ IP13_19_16
+ IP13_15_12
+ IP13_11_8
+ IP13_7_4
+ IP13_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
+ IP14_31_28
+ IP14_27_24
+ IP14_23_20
+ IP14_19_16
+ IP14_15_12
+ IP14_11_8
+ IP14_7_4
+ IP14_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
+ IP15_31_28
+ IP15_27_24
+ IP15_23_20
+ IP15_19_16
+ IP15_15_12
+ IP15_11_8
+ IP15_7_4
+ IP15_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
+ IP16_31_28
+ IP16_27_24
+ IP16_23_20
+ IP16_19_16
+ IP16_15_12
+ IP16_11_8
+ IP16_7_4
+ IP16_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
+ IP17_31_28
+ IP17_27_24
+ IP17_23_20
+ IP17_19_16
+ IP17_15_12
+ IP17_11_8
+ IP17_7_4
+ IP17_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
+ /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ IP18_7_4
+ IP18_3_0 }
+ },
+#undef F_
+#undef FM
+
+#define F_(x, y) x,
+#define FM(x) FN_##x,
+ { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
+ 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
+ 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
+ MOD_SEL0_31_30_29
+ MOD_SEL0_28_27
+ MOD_SEL0_26_25_24
+ MOD_SEL0_23
+ MOD_SEL0_22
+ MOD_SEL0_21
+ MOD_SEL0_20
+ MOD_SEL0_19
+ MOD_SEL0_18_17
+ MOD_SEL0_16
+ 0, 0, /* RESERVED 15 */
+ MOD_SEL0_14_13
+ MOD_SEL0_12
+ MOD_SEL0_11
+ MOD_SEL0_10
+ MOD_SEL0_9_8
+ MOD_SEL0_7_6
+ MOD_SEL0_5
+ MOD_SEL0_4_3
+ /* RESERVED 2, 1, 0 */
+ 0, 0, 0, 0, 0, 0, 0, 0 }
+ },
+ { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
+ 2, 3, 1, 2, 3, 1, 1, 2, 1,
+ 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
+ MOD_SEL1_31_30
+ MOD_SEL1_29_28_27
+ MOD_SEL1_26
+ MOD_SEL1_25_24
+ MOD_SEL1_23_22_21
+ MOD_SEL1_20
+ MOD_SEL1_19
+ MOD_SEL1_18_17
+ MOD_SEL1_16
+ MOD_SEL1_15_14
+ MOD_SEL1_13
+ MOD_SEL1_12
+ MOD_SEL1_11
+ MOD_SEL1_10
+ MOD_SEL1_9
+ 0, 0, 0, 0, /* RESERVED 8, 7 */
+ MOD_SEL1_6
+ MOD_SEL1_5
+ MOD_SEL1_4
+ MOD_SEL1_3
+ MOD_SEL1_2
+ MOD_SEL1_1
+ MOD_SEL1_0 }
+ },
+ { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
+ 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
+ 4, 4, 4, 3, 1) {
+ MOD_SEL2_31
+ MOD_SEL2_30
+ MOD_SEL2_29
+ MOD_SEL2_28_27
+ MOD_SEL2_26
+ MOD_SEL2_25_24_23
+ MOD_SEL2_22
+ MOD_SEL2_21
+ MOD_SEL2_20
+ MOD_SEL2_19
+ MOD_SEL2_18
+ MOD_SEL2_17
+ /* RESERVED 16 */
+ 0, 0,
+ /* RESERVED 15, 14, 13, 12 */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 11, 10, 9, 8 */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 7, 6, 5, 4 */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 3, 2, 1 */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ MOD_SEL2_0 }
+ },
+ { },
+};
+
+static const struct pinmux_drive_reg pinmux_drive_regs[] = {
+ { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
+ { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
+ { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
+ { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
+ { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
+ { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
+ { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
+ { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
+ { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
+ } },
+ { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
+ { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
+ { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
+ { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
+ { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
+ { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
+ { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
+ { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
+ { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
+ } },
+ { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
+ { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
+ { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
+ { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
+ { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
+ { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
+ { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
+ { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
+ { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
+ } },
+ { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
+ { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
+ { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
+ { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
+ { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
+ { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
+ { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
+ { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
+ { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
+ } },
+ { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
+ { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
+ { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
+ { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
+ { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
+ { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
+ { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
+ { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
+ { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
+ } },
+ { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
+ { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
+ { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
+ { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
+ { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
+ { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
+ { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
+ { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
+ { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
+ } },
+ { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
+ { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
+ { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
+ { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
+ { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
+ { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
+ { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
+ { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
+ { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
+ } },
+ { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
+ { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
+ { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
+ { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
+ { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
+ { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
+ { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
+ { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
+ { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
+ } },
+ { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
+ { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
+ { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
+ { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
+ { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
+ { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
+ { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
+ { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
+ { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
+ } },
+ { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
+ { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
+ { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
+ { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
+ { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
+ { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
+ { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
+ { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
+ { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
+ } },
+ { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
+ { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
+ { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
+ { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
+ { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
+ { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
+ { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
+ { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
+ { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
+ } },
+ { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
+ { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
+ { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
+ { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
+ { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
+ { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
+ { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
+ { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
+ { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
+ } },
+ { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
+ { PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN3 */
+ { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */
+ { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
+ } },
+ { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
+ { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
+ { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
+ { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
+ { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
+ { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
+ { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
+ { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
+ { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
+ } },
+ { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
+ { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
+ { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
+ { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
+ { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
+ { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
+ { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
+ { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
+ { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
+ } },
+ { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
+ { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
+ { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
+ { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
+ { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
+ { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
+ { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
+ { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
+ { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
+ } },
+ { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
+ { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
+ { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
+ { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
+ { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
+ { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
+ { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
+ { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
+ { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
+ } },
+ { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
+ { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
+ { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
+ { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
+ { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
+ { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
+ { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
+ { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
+ { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
+ } },
+ { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
+ { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
+ { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
+ { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
+ { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
+ { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
+ { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
+ { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
+ { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
+ } },
+ { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
+ { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
+ { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
+ { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
+ { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
+ { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
+ { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
+ { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
+ { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
+ } },
+ { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
+ { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
+ { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
+ { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
+ { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
+ { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
+ { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
+ { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
+ { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
+ } },
+ { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
+ { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
+ { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
+ { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
+ { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
+ { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
+ { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
+ { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
+ { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
+ } },
+ { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
+ { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
+ { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
+ { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
+ { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
+ { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
+ { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
+ { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
+ { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
+ } },
+ { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
+ { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
+ { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
+ { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
+ { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
+ { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
+ { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
+ { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
+ { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
+ } },
+ { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
+ { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
+ { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
+ { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
+ { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
+ { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
+ { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
+ { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
+ } },
+ { },
+};
+
+enum ioctrl_regs {
+ POCCTRL,
+};
+
+static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
+ [POCCTRL] = { 0xe6060380, },
+ { /* sentinel */ },
+};
+
+static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
+{
+ int bit = -EINVAL;
+
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
+
+ if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
+ bit = pin & 0x1f;
+
+ if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
+ bit = (pin & 0x1f) + 12;
+
+ return bit;
+}
+
+static const struct pinmux_bias_reg pinmux_bias_regs[] = {
+ { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
+ [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
+ [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
+ [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
+ [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
+ [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
+ [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
+ [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
+ [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
+ [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
+ [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
+ [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
+ [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
+ [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
+ [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
+ [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
+ [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
+ [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
+ [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
+ [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
+ [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
+ [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
+ [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
+ [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
+ [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
+ [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
+ [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
+ [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
+ [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
+ [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
+ [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
+ [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
+ [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
+ } },
+ { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
+ [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
+ [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
+ [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
+ [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
+ [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
+ [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
+ [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
+ [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
+ [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
+ [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
+ [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
+ [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
+ [12] = RCAR_GP_PIN(1, 0), /* A0 */
+ [13] = RCAR_GP_PIN(1, 1), /* A1 */
+ [14] = RCAR_GP_PIN(1, 2), /* A2 */
+ [15] = RCAR_GP_PIN(1, 3), /* A3 */
+ [16] = RCAR_GP_PIN(1, 4), /* A4 */
+ [17] = RCAR_GP_PIN(1, 5), /* A5 */
+ [18] = RCAR_GP_PIN(1, 6), /* A6 */
+ [19] = RCAR_GP_PIN(1, 7), /* A7 */
+ [20] = RCAR_GP_PIN(1, 8), /* A8 */
+ [21] = RCAR_GP_PIN(1, 9), /* A9 */
+ [22] = RCAR_GP_PIN(1, 10), /* A10 */
+ [23] = RCAR_GP_PIN(1, 11), /* A11 */
+ [24] = RCAR_GP_PIN(1, 12), /* A12 */
+ [25] = RCAR_GP_PIN(1, 13), /* A13 */
+ [26] = RCAR_GP_PIN(1, 14), /* A14 */
+ [27] = RCAR_GP_PIN(1, 15), /* A15 */
+ [28] = RCAR_GP_PIN(1, 16), /* A16 */
+ [29] = RCAR_GP_PIN(1, 17), /* A17 */
+ [30] = RCAR_GP_PIN(1, 18), /* A18 */
+ [31] = RCAR_GP_PIN(1, 19), /* A19 */
+ } },
+ { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
+ [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
+ [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
+ [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
+ [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
+ [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
+ [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
+ [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
+ [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
+ [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
+ [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
+ [10] = RCAR_GP_PIN(0, 0), /* D0 */
+ [11] = RCAR_GP_PIN(0, 1), /* D1 */
+ [12] = RCAR_GP_PIN(0, 2), /* D2 */
+ [13] = RCAR_GP_PIN(0, 3), /* D3 */
+ [14] = RCAR_GP_PIN(0, 4), /* D4 */
+ [15] = RCAR_GP_PIN(0, 5), /* D5 */
+ [16] = RCAR_GP_PIN(0, 6), /* D6 */
+ [17] = RCAR_GP_PIN(0, 7), /* D7 */
+ [18] = RCAR_GP_PIN(0, 8), /* D8 */
+ [19] = RCAR_GP_PIN(0, 9), /* D9 */
+ [20] = RCAR_GP_PIN(0, 10), /* D10 */
+ [21] = RCAR_GP_PIN(0, 11), /* D11 */
+ [22] = RCAR_GP_PIN(0, 12), /* D12 */
+ [23] = RCAR_GP_PIN(0, 13), /* D13 */
+ [24] = RCAR_GP_PIN(0, 14), /* D14 */
+ [25] = RCAR_GP_PIN(0, 15), /* D15 */
+ [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
+ [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
+ [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
+ [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
+ [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
+ [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
+ } },
+ { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
+ [ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN2 */
+ [ 1] = PIN_NONE,
+ [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */
+ [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
+ [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
+ [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
+ [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
+ [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
+ [ 8] = PIN_NONE,
+ [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
+ [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
+ [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
+ [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
+ [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
+ [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
+ [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
+ [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
+ [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
+ [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
+ [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
+ [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
+ [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
+ [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
+ [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
+ [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
+ [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
+ [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
+ [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
+ [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
+ [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
+ [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
+ [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
+ } },
+ { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
+ [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
+ [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
+ [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
+ [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
+ [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
+ [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
+ [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
+ [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
+ [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
+ [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
+ [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
+ [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
+ [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
+ [13] = RCAR_GP_PIN(5, 1), /* RX0 */
+ [14] = RCAR_GP_PIN(5, 2), /* TX0 */
+ [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
+ [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
+ [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
+ [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
+ [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
+ [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
+ [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
+ [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
+ [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
+ [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
+ [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
+ [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
+ [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
+ [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
+ [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
+ [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
+ [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
+ } },
+ { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
+ [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
+ [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
+ [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
+ [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
+ [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
+ [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
+ [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
+ [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
+ [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
+ [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
+ [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
+ [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
+ [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
+ [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
+ [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
+ [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
+ [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
+ [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
+ [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
+ [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
+ [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
+ [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
+ [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
+ [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
+ [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
+ [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
+ [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
+ [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
+ [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
+ [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
+ [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
+ [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
+ } },
+ { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
+ [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
+ [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
+ [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
+ [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
+ [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
+ [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
+ [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
+ [ 7] = PIN_NONE,
+ [ 8] = PIN_NONE,
+ [ 9] = PIN_NONE,
+ [10] = PIN_NONE,
+ [11] = PIN_NONE,
+ [12] = PIN_NONE,
+ [13] = PIN_NONE,
+ [14] = PIN_NONE,
+ [15] = PIN_NONE,
+ [16] = PIN_NONE,
+ [17] = PIN_NONE,
+ [18] = PIN_NONE,
+ [19] = PIN_NONE,
+ [20] = PIN_NONE,
+ [21] = PIN_NONE,
+ [22] = PIN_NONE,
+ [23] = PIN_NONE,
+ [24] = PIN_NONE,
+ [25] = PIN_NONE,
+ [26] = PIN_NONE,
+ [27] = PIN_NONE,
+ [28] = PIN_NONE,
+ [29] = PIN_NONE,
+ [30] = PIN_NONE,
+ [31] = PIN_NONE,
+ } },
+ { /* sentinel */ },
+};
+
+static unsigned int r8a77965_pinmux_get_bias(struct sh_pfc *pfc,
+ unsigned int pin)
+{
+ const struct pinmux_bias_reg *reg;
+ unsigned int bit;
+
+ reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
+ if (!reg)
+ return PIN_CONFIG_BIAS_DISABLE;
+
+ if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
+ return PIN_CONFIG_BIAS_DISABLE;
+ else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
+ return PIN_CONFIG_BIAS_PULL_UP;
+ else
+ return PIN_CONFIG_BIAS_PULL_DOWN;
+}
+
+static void r8a77965_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
+ unsigned int bias)
+{
+ const struct pinmux_bias_reg *reg;
+ u32 enable, updown;
+ unsigned int bit;
+
+ reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
+ if (!reg)
+ return;
+
+ enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
+ if (bias != PIN_CONFIG_BIAS_DISABLE)
+ enable |= BIT(bit);
+
+ updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
+ if (bias == PIN_CONFIG_BIAS_PULL_UP)
+ updown |= BIT(bit);
+
+ sh_pfc_write(pfc, reg->pud, updown);
+ sh_pfc_write(pfc, reg->puen, enable);
+}
+
+static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = {
+ .pin_to_pocctrl = r8a77965_pin_to_pocctrl,
+ .get_bias = r8a77965_pinmux_get_bias,
+ .set_bias = r8a77965_pinmux_set_bias,
+};
+
+const struct sh_pfc_soc_info r8a77965_pinmux_info = {
+ .name = "r8a77965_pfc",
+ .ops = &r8a77965_pinmux_ops,
+ .unlock_reg = 0xe6060000, /* PMMR */
+
+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups,
+ .nr_groups = ARRAY_SIZE(pinmux_groups),
+ .functions = pinmux_functions,
+ .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+ .cfg_regs = pinmux_config_regs,
+ .drive_regs = pinmux_drive_regs,
+ .bias_regs = pinmux_bias_regs,
+ .ioctrl_regs = pinmux_ioctrl_regs,
+
+ .pinmux_data = pinmux_data,
+ .pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
index 794f12d74449..b1bb7263532b 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
@@ -728,6 +728,82 @@ static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
};
+/* - AVB0 ------------------------------------------------------------------- */
+static const unsigned int avb0_link_pins[] = {
+ /* AVB0_LINK */
+ RCAR_GP_PIN(1, 18),
+};
+static const unsigned int avb0_link_mux[] = {
+ AVB0_LINK_MARK,
+};
+static const unsigned int avb0_magic_pins[] = {
+ /* AVB0_MAGIC */
+ RCAR_GP_PIN(1, 16),
+};
+static const unsigned int avb0_magic_mux[] = {
+ AVB0_MAGIC_MARK,
+};
+static const unsigned int avb0_phy_int_pins[] = {
+ /* AVB0_PHY_INT */
+ RCAR_GP_PIN(1, 17),
+};
+static const unsigned int avb0_phy_int_mux[] = {
+ AVB0_PHY_INT_MARK,
+};
+static const unsigned int avb0_mdio_pins[] = {
+ /* AVB0_MDC, AVB0_MDIO */
+ RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
+};
+static const unsigned int avb0_mdio_mux[] = {
+ AVB0_MDC_MARK, AVB0_MDIO_MARK,
+};
+static const unsigned int avb0_rgmii_pins[] = {
+ /*
+ * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
+ * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3
+ */
+ RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
+ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
+ RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
+ RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
+ RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
+ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
+};
+static const unsigned int avb0_rgmii_mux[] = {
+ AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
+ AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
+ AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
+ AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
+};
+static const unsigned int avb0_txcrefclk_pins[] = {
+ /* AVB0_TXCREFCLK */
+ RCAR_GP_PIN(1, 13),
+};
+static const unsigned int avb0_txcrefclk_mux[] = {
+ AVB0_TXCREFCLK_MARK,
+};
+static const unsigned int avb0_avtp_pps_pins[] = {
+ /* AVB0_AVTP_PPS */
+ RCAR_GP_PIN(2, 6),
+};
+static const unsigned int avb0_avtp_pps_mux[] = {
+ AVB0_AVTP_PPS_MARK,
+};
+static const unsigned int avb0_avtp_capture_pins[] = {
+ /* AVB0_AVTP_CAPTURE */
+ RCAR_GP_PIN(1, 20),
+};
+static const unsigned int avb0_avtp_capture_mux[] = {
+ AVB0_AVTP_CAPTURE_MARK,
+};
+static const unsigned int avb0_avtp_match_pins[] = {
+ /* AVB0_AVTP_MATCH */
+ RCAR_GP_PIN(1, 19),
+};
+static const unsigned int avb0_avtp_match_mux[] = {
+ AVB0_AVTP_MATCH_MARK,
+};
+
/* - CANFD Clock ------------------------------------------------------------ */
static const unsigned int canfd_clk_a_pins[] = {
/* CANFD_CLK */
@@ -1599,6 +1675,15 @@ static const unsigned int vin1_clk_mux[] = {
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(avb0_link),
+ SH_PFC_PIN_GROUP(avb0_magic),
+ SH_PFC_PIN_GROUP(avb0_phy_int),
+ SH_PFC_PIN_GROUP(avb0_mdio),
+ SH_PFC_PIN_GROUP(avb0_rgmii),
+ SH_PFC_PIN_GROUP(avb0_txcrefclk),
+ SH_PFC_PIN_GROUP(avb0_avtp_pps),
+ SH_PFC_PIN_GROUP(avb0_avtp_capture),
+ SH_PFC_PIN_GROUP(avb0_avtp_match),
SH_PFC_PIN_GROUP(canfd_clk_a),
SH_PFC_PIN_GROUP(canfd_clk_b),
SH_PFC_PIN_GROUP(canfd0_data_a),
@@ -1709,6 +1794,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(vin1_clk),
};
+static const char * const avb0_groups[] = {
+ "avb0_link",
+ "avb0_magic",
+ "avb0_phy_int",
+ "avb0_mdio",
+ "avb0_rgmii",
+ "avb0_txcrefclk",
+ "avb0_avtp_pps",
+ "avb0_avtp_capture",
+ "avb0_avtp_match",
+};
+
static const char * const canfd_clk_groups[] = {
"canfd_clk_a",
"canfd_clk_b",
@@ -1914,6 +2011,7 @@ static const char * const vin1_groups[] = {
};
static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(avb0),
SH_PFC_FUNCTION(canfd_clk),
SH_PFC_FUNCTION(canfd0),
SH_PFC_FUNCTION(canfd1),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77980.c b/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
new file mode 100644
index 000000000000..84c8f1c2f1d1
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
@@ -0,0 +1,2799 @@
+// SPDX-Lincense-Identifier: GPL 2.0
+/*
+ * R8A77980 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ *
+ * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+ *
+ * R-Car Gen3 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+
+#include "core.h"
+#include "sh_pfc.h"
+
+#define CPU_ALL_PORT(fn, sfx) \
+ PORT_GP_22(0, fn, sfx), \
+ PORT_GP_28(1, fn, sfx), \
+ PORT_GP_30(2, fn, sfx), \
+ PORT_GP_17(3, fn, sfx), \
+ PORT_GP_25(4, fn, sfx), \
+ PORT_GP_15(5, fn, sfx)
+
+/*
+ * F_() : just information
+ * FM() : macro for FN_xxx / xxx_MARK
+ */
+
+/* GPSR0 */
+#define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20)
+#define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16)
+#define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12)
+#define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8)
+#define GPSR0_17 F_(DU_DB7, IP2_7_4)
+#define GPSR0_16 F_(DU_DB6, IP2_3_0)
+#define GPSR0_15 F_(DU_DB5, IP1_31_28)
+#define GPSR0_14 F_(DU_DB4, IP1_27_24)
+#define GPSR0_13 F_(DU_DB3, IP1_23_20)
+#define GPSR0_12 F_(DU_DB2, IP1_19_16)
+#define GPSR0_11 F_(DU_DG7, IP1_15_12)
+#define GPSR0_10 F_(DU_DG6, IP1_11_8)
+#define GPSR0_9 F_(DU_DG5, IP1_7_4)
+#define GPSR0_8 F_(DU_DG4, IP1_3_0)
+#define GPSR0_7 F_(DU_DG3, IP0_31_28)
+#define GPSR0_6 F_(DU_DG2, IP0_27_24)
+#define GPSR0_5 F_(DU_DR7, IP0_23_20)
+#define GPSR0_4 F_(DU_DR6, IP0_19_16)
+#define GPSR0_3 F_(DU_DR5, IP0_15_12)
+#define GPSR0_2 F_(DU_DR4, IP0_11_8)
+#define GPSR0_1 F_(DU_DR3, IP0_7_4)
+#define GPSR0_0 F_(DU_DR2, IP0_3_0)
+
+/* GPSR1 */
+#define GPSR1_27 F_(DIGRF_CLKOUT, IP8_31_28)
+#define GPSR1_26 F_(DIGRF_CLKIN, IP8_27_24)
+#define GPSR1_25 F_(CANFD_CLK_A, IP8_23_20)
+#define GPSR1_24 F_(CANFD1_RX, IP8_19_16)
+#define GPSR1_23 F_(CANFD1_TX, IP8_15_12)
+#define GPSR1_22 F_(CANFD0_RX_A, IP8_11_8)
+#define GPSR1_21 F_(CANFD0_TX_A, IP8_7_4)
+#define GPSR1_20 F_(AVB_AVTP_CAPTURE, IP8_3_0)
+#define GPSR1_19 F_(AVB_AVTP_MATCH, IP7_31_28)
+#define GPSR1_18 FM(AVB_LINK)
+#define GPSR1_17 FM(AVB_PHY_INT)
+#define GPSR1_16 FM(AVB_MAGIC)
+#define GPSR1_15 FM(AVB_MDC)
+#define GPSR1_14 FM(AVB_MDIO)
+#define GPSR1_13 FM(AVB_TXCREFCLK)
+#define GPSR1_12 FM(AVB_TD3)
+#define GPSR1_11 FM(AVB_TD2)
+#define GPSR1_10 FM(AVB_TD1)
+#define GPSR1_9 FM(AVB_TD0)
+#define GPSR1_8 FM(AVB_TXC)
+#define GPSR1_7 FM(AVB_TX_CTL)
+#define GPSR1_6 FM(AVB_RD3)
+#define GPSR1_5 FM(AVB_RD2)
+#define GPSR1_4 FM(AVB_RD1)
+#define GPSR1_3 FM(AVB_RD0)
+#define GPSR1_2 FM(AVB_RXC)
+#define GPSR1_1 FM(AVB_RX_CTL)
+#define GPSR1_0 F_(IRQ0, IP2_27_24)
+
+/* GPSR2 */
+#define GPSR2_29 F_(FSO_TOE_N, IP10_19_16)
+#define GPSR2_28 F_(FSO_CFE_1_N, IP10_15_12)
+#define GPSR2_27 F_(FSO_CFE_0_N, IP10_11_8)
+#define GPSR2_26 F_(SDA3, IP10_7_4)
+#define GPSR2_25 F_(SCL3, IP10_3_0)
+#define GPSR2_24 F_(MSIOF0_SS2, IP9_31_28)
+#define GPSR2_23 F_(MSIOF0_SS1, IP9_27_24)
+#define GPSR2_22 F_(MSIOF0_SYNC, IP9_23_20)
+#define GPSR2_21 F_(MSIOF0_SCK, IP9_19_16)
+#define GPSR2_20 F_(MSIOF0_TXD, IP9_15_12)
+#define GPSR2_19 F_(MSIOF0_RXD, IP9_11_8)
+#define GPSR2_18 F_(IRQ5, IP9_7_4)
+#define GPSR2_17 F_(IRQ4, IP9_3_0)
+#define GPSR2_16 F_(VI0_FIELD, IP4_31_28)
+#define GPSR2_15 F_(VI0_DATA11, IP4_27_24)
+#define GPSR2_14 F_(VI0_DATA10, IP4_23_20)
+#define GPSR2_13 F_(VI0_DATA9, IP4_19_16)
+#define GPSR2_12 F_(VI0_DATA8, IP4_15_12)
+#define GPSR2_11 F_(VI0_DATA7, IP4_11_8)
+#define GPSR2_10 F_(VI0_DATA6, IP4_7_4)
+#define GPSR2_9 F_(VI0_DATA5, IP4_3_0)
+#define GPSR2_8 F_(VI0_DATA4, IP3_31_28)
+#define GPSR2_7 F_(VI0_DATA3, IP3_27_24)
+#define GPSR2_6 F_(VI0_DATA2, IP3_23_20)
+#define GPSR2_5 F_(VI0_DATA1, IP3_19_16)
+#define GPSR2_4 F_(VI0_DATA0, IP3_15_12)
+#define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8)
+#define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4)
+#define GPSR2_1 F_(VI0_CLKENB, IP3_3_0)
+#define GPSR2_0 F_(VI0_CLK, IP2_31_28)
+
+/* GPSR3 */
+#define GPSR3_16 F_(VI1_FIELD, IP7_3_0)
+#define GPSR3_15 F_(VI1_DATA11, IP6_31_28)
+#define GPSR3_14 F_(VI1_DATA10, IP6_27_24)
+#define GPSR3_13 F_(VI1_DATA9, IP6_23_20)
+#define GPSR3_12 F_(VI1_DATA8, IP6_19_16)
+#define GPSR3_11 F_(VI1_DATA7, IP6_15_12)
+#define GPSR3_10 F_(VI1_DATA6, IP6_11_8)
+#define GPSR3_9 F_(VI1_DATA5, IP6_7_4)
+#define GPSR3_8 F_(VI1_DATA4, IP6_3_0)
+#define GPSR3_7 F_(VI1_DATA3, IP5_31_28)
+#define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
+#define GPSR3_5 F_(VI1_DATA1, IP5_23_20)
+#define GPSR3_4 F_(VI1_DATA0, IP5_19_16)
+#define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12)
+#define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8)
+#define GPSR3_1 F_(VI1_CLKENB, IP5_7_4)
+#define GPSR3_0 F_(VI1_CLK, IP5_3_0)
+
+/* GPSR4 */
+#define GPSR4_24 FM(GETHER_LINK_A)
+#define GPSR4_23 FM(GETHER_PHY_INT_A)
+#define GPSR4_22 FM(GETHER_MAGIC)
+#define GPSR4_21 FM(GETHER_MDC_A)
+#define GPSR4_20 FM(GETHER_MDIO_A)
+#define GPSR4_19 FM(GETHER_TXCREFCLK_MEGA)
+#define GPSR4_18 FM(GETHER_TXCREFCLK)
+#define GPSR4_17 FM(GETHER_TD3)
+#define GPSR4_16 FM(GETHER_TD2)
+#define GPSR4_15 FM(GETHER_TD1)
+#define GPSR4_14 FM(GETHER_TD0)
+#define GPSR4_13 FM(GETHER_TXC)
+#define GPSR4_12 FM(GETHER_TX_CTL)
+#define GPSR4_11 FM(GETHER_RD3)
+#define GPSR4_10 FM(GETHER_RD2)
+#define GPSR4_9 FM(GETHER_RD1)
+#define GPSR4_8 FM(GETHER_RD0)
+#define GPSR4_7 FM(GETHER_RXC)
+#define GPSR4_6 FM(GETHER_RX_CTL)
+#define GPSR4_5 F_(SDA2, IP7_27_24)
+#define GPSR4_4 F_(SCL2, IP7_23_20)
+#define GPSR4_3 F_(SDA1, IP7_19_16)
+#define GPSR4_2 F_(SCL1, IP7_15_12)
+#define GPSR4_1 F_(SDA0, IP7_11_8)
+#define GPSR4_0 F_(SCL0, IP7_7_4)
+
+/* GPSR5 */
+#define GPSR5_14 FM(RPC_INT_N)
+#define GPSR5_13 FM(RPC_WP_N)
+#define GPSR5_12 FM(RPC_RESET_N)
+#define GPSR5_11 FM(QSPI1_SSL)
+#define GPSR5_10 FM(QSPI1_IO3)
+#define GPSR5_9 FM(QSPI1_IO2)
+#define GPSR5_8 FM(QSPI1_MISO_IO1)
+#define GPSR5_7 FM(QSPI1_MOSI_IO0)
+#define GPSR5_6 FM(QSPI1_SPCLK)
+#define GPSR5_5 FM(QSPI0_SSL)
+#define GPSR5_4 FM(QSPI0_IO3)
+#define GPSR5_3 FM(QSPI0_IO2)
+#define GPSR5_2 FM(QSPI0_MISO_IO1)
+#define GPSR5_1 FM(QSPI0_MOSI_IO0)
+#define GPSR5_0 FM(QSPI0_SPCLK)
+
+
+/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
+#define IP0_3_0 FM(DU_DR2) FM(SCK4) FM(GETHER_RMII_CRS_DV) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_7_4 FM(DU_DR3) FM(RX4) FM(GETHER_RMII_RX_ER) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_11_8 FM(DU_DR4) FM(TX4) FM(GETHER_RMII_RXD0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_15_12 FM(DU_DR5) FM(CTS4_N) FM(GETHER_RMII_RXD1) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_19_16 FM(DU_DR6) FM(RTS4_N_TANS) FM(GETHER_RMII_TXD_EN) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_23_20 FM(DU_DR7) F_(0, 0) FM(GETHER_RMII_TXD0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_27_24 FM(DU_DG2) F_(0, 0) FM(GETHER_RMII_TXD1) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_31_28 FM(DU_DG3) FM(CPG_CPCKOUT) FM(GETHER_RMII_REFCLK) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_3_0 FM(DU_DG4) FM(SCL5) F_(0, 0) FM(A8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_7_4 FM(DU_DG5) FM(SDA5) FM(GETHER_MDC_B) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_11_8 FM(DU_DG6) FM(SCIF_CLK_A) FM(GETHER_MDIO_B) FM(A10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_15_12 FM(DU_DG7) FM(HRX0_A) F_(0, 0) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_19_16 FM(DU_DB2) FM(HSCK0_A) F_(0, 0) FM(A12) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_23_20 FM(DU_DB3) FM(HRTS0_N_A) F_(0, 0) FM(A13) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_27_24 FM(DU_DB4) FM(HCTS0_N_A) F_(0, 0) FM(A14) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_31_28 FM(DU_DB5) FM(HTX0_A) FM(PWM0_A) FM(A15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_3_0 FM(DU_DB6) FM(MSIOF3_RXD) F_(0, 0) FM(A16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_7_4 FM(DU_DB7) FM(MSIOF3_TXD) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_11_8 FM(DU_DOTCLKOUT) FM(MSIOF3_SS1) FM(GETHER_LINK_B) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(MSIOF3_SS2) FM(GETHER_PHY_INT_B) FM(A19) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_27_24 FM(IRQ0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N_TANS) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_23_20 FM(VI0_DATA2) FM(AVB_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_7_4 FM(VI1_DATA5) F_(0, 0) F_(0, 0) FM(D8) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_11_8 FM(VI1_DATA6) F_(0, 0) F_(0, 0) FM(D9) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_15_12 FM(VI1_DATA7) F_(0, 0) F_(0, 0) FM(D10) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_19_16 FM(VI1_DATA8) F_(0, 0) F_(0, 0) FM(D11) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_23_20 FM(VI1_DATA9) FM(TCLK1_A) F_(0, 0) FM(D12) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_27_24 FM(VI1_DATA10) FM(TCLK2_A) F_(0, 0) FM(D13) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) F_(0, 0) FM(D14) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) F_(0, 0) FM(D15) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_7_4 FM(SCL0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_11_8 FM(SDA0) F_(0, 0) F_(0, 0) FM(BS_N) FM(SCK0) FM(HSCK0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_15_12 FM(SCL1) F_(0, 0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(HCTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_19_16 FM(SDA1) F_(0, 0) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N_TANS) FM(HRTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_23_20 FM(SCL2) F_(0, 0) F_(0, 0) FM(WE1_N) FM(RX0) FM(HRX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_27_24 FM(SDA2) F_(0, 0) F_(0, 0) FM(EX_WAIT0) FM(TX0) FM(HTX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_31_28 FM(AVB_AVTP_MATCH) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_3_0 FM(AVB_AVTP_CAPTURE) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_7_4 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_11_8 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_15_12 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_19_16 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_27_24 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_31_28 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_3_0 FM(IRQ4) F_(0, 0) F_(0, 0) FM(VI0_DATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_11_8 FM(MSIOF0_RXD) FM(DU_DR0) F_(0, 0) FM(VI0_DATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_15_12 FM(MSIOF0_TXD) FM(DU_DR1) F_(0, 0) FM(VI0_DATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_19_16 FM(MSIOF0_SCK) FM(DU_DG0) F_(0, 0) FM(VI0_DATA16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_23_20 FM(MSIOF0_SYNC) FM(DU_DG1) F_(0, 0) FM(VI0_DATA17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_27_24 FM(MSIOF0_SS1) FM(DU_DB0) FM(TCLK3) FM(VI0_DATA18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_31_28 FM(MSIOF0_SS2) FM(DU_DB1) FM(TCLK4) FM(VI0_DATA19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_3_0 FM(SCL3) F_(0, 0) F_(0, 0) FM(VI0_DATA20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_7_4 FM(SDA3) F_(0, 0) F_(0, 0) FM(VI0_DATA21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_11_8 FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) FM(VI0_DATA22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_15_12 FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) FM(VI0_DATA23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_19_16 FM(FSO_TOE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+#define PINMUX_GPSR \
+\
+ GPSR2_29 \
+ GPSR2_28 \
+ GPSR1_27 GPSR2_27 \
+ GPSR1_26 GPSR2_26 \
+ GPSR1_25 GPSR2_25 \
+ GPSR1_24 GPSR2_24 GPSR4_24 \
+ GPSR1_23 GPSR2_23 GPSR4_23 \
+ GPSR1_22 GPSR2_22 GPSR4_22 \
+GPSR0_21 GPSR1_21 GPSR2_21 GPSR4_21 \
+GPSR0_20 GPSR1_20 GPSR2_20 GPSR4_20 \
+GPSR0_19 GPSR1_19 GPSR2_19 GPSR4_19 \
+GPSR0_18 GPSR1_18 GPSR2_18 GPSR4_18 \
+GPSR0_17 GPSR1_17 GPSR2_17 GPSR4_17 \
+GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 \
+GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 \
+GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 \
+GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 \
+GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 \
+GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 \
+GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 \
+GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 \
+GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 \
+GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 \
+GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 \
+GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 \
+GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 \
+GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 \
+GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 \
+GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 \
+GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0
+
+#define PINMUX_IPSR \
+\
+FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
+FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
+FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
+FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
+FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
+FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
+FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
+FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
+\
+FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
+FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
+FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
+FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
+FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
+FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
+FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
+FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
+\
+FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 \
+FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 \
+FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 \
+FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 \
+FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 \
+FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 \
+FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 \
+FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28
+
+/* MOD_SEL0 */ /* 0 */ /* 1 */
+#define MOD_SEL0_11 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
+#define MOD_SEL0_10 FM(SEL_GETHER_0) FM(SEL_GETHER_1)
+#define MOD_SEL0_9 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
+#define MOD_SEL0_8 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
+#define MOD_SEL0_7 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
+#define MOD_SEL0_6 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
+#define MOD_SEL0_5 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
+#define MOD_SEL0_4 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
+#define MOD_SEL0_2 FM(SEL_RSP_0) FM(SEL_RSP_1)
+#define MOD_SEL0_1 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
+#define MOD_SEL0_0 FM(SEL_TMU_0) FM(SEL_TMU_1)
+
+#define PINMUX_MOD_SELS \
+\
+MOD_SEL0_11 \
+MOD_SEL0_10 \
+MOD_SEL0_9 \
+MOD_SEL0_8 \
+MOD_SEL0_7 \
+MOD_SEL0_6 \
+MOD_SEL0_5 \
+MOD_SEL0_4 \
+MOD_SEL0_2 \
+MOD_SEL0_1 \
+MOD_SEL0_0
+
+enum {
+ PINMUX_RESERVED = 0,
+
+ PINMUX_DATA_BEGIN,
+ GP_ALL(DATA),
+ PINMUX_DATA_END,
+
+#define F_(x, y)
+#define FM(x) FN_##x,
+ PINMUX_FUNCTION_BEGIN,
+ GP_ALL(FN),
+ PINMUX_GPSR
+ PINMUX_IPSR
+ PINMUX_MOD_SELS
+ PINMUX_FUNCTION_END,
+#undef F_
+#undef FM
+
+#define F_(x, y)
+#define FM(x) x##_MARK,
+ PINMUX_MARK_BEGIN,
+ PINMUX_GPSR
+ PINMUX_IPSR
+ PINMUX_MOD_SELS
+ PINMUX_MARK_END,
+#undef F_
+#undef FM
+};
+
+static const u16 pinmux_data[] = {
+ PINMUX_DATA_GP_ALL(),
+
+ PINMUX_SINGLE(AVB_RX_CTL),
+ PINMUX_SINGLE(AVB_RXC),
+ PINMUX_SINGLE(AVB_RD0),
+ PINMUX_SINGLE(AVB_RD1),
+ PINMUX_SINGLE(AVB_RD2),
+ PINMUX_SINGLE(AVB_RD3),
+ PINMUX_SINGLE(AVB_TX_CTL),
+ PINMUX_SINGLE(AVB_TXC),
+ PINMUX_SINGLE(AVB_TD0),
+ PINMUX_SINGLE(AVB_TD1),
+ PINMUX_SINGLE(AVB_TD2),
+ PINMUX_SINGLE(AVB_TD3),
+ PINMUX_SINGLE(AVB_TXCREFCLK),
+ PINMUX_SINGLE(AVB_MDIO),
+ PINMUX_SINGLE(AVB_MDC),
+ PINMUX_SINGLE(AVB_MAGIC),
+ PINMUX_SINGLE(AVB_PHY_INT),
+ PINMUX_SINGLE(AVB_LINK),
+
+ PINMUX_SINGLE(GETHER_RX_CTL),
+ PINMUX_SINGLE(GETHER_RXC),
+ PINMUX_SINGLE(GETHER_RD0),
+ PINMUX_SINGLE(GETHER_RD1),
+ PINMUX_SINGLE(GETHER_RD2),
+ PINMUX_SINGLE(GETHER_RD3),
+ PINMUX_SINGLE(GETHER_TX_CTL),
+ PINMUX_SINGLE(GETHER_TXC),
+ PINMUX_SINGLE(GETHER_TD0),
+ PINMUX_SINGLE(GETHER_TD1),
+ PINMUX_SINGLE(GETHER_TD2),
+ PINMUX_SINGLE(GETHER_TD3),
+ PINMUX_SINGLE(GETHER_TXCREFCLK),
+ PINMUX_SINGLE(GETHER_TXCREFCLK_MEGA),
+ PINMUX_SINGLE(GETHER_MDIO_A),
+ PINMUX_SINGLE(GETHER_MDC_A),
+ PINMUX_SINGLE(GETHER_MAGIC),
+ PINMUX_SINGLE(GETHER_PHY_INT_A),
+ PINMUX_SINGLE(GETHER_LINK_A),
+
+ PINMUX_SINGLE(QSPI0_SPCLK),
+ PINMUX_SINGLE(QSPI0_MOSI_IO0),
+ PINMUX_SINGLE(QSPI0_MISO_IO1),
+ PINMUX_SINGLE(QSPI0_IO2),
+ PINMUX_SINGLE(QSPI0_IO3),
+ PINMUX_SINGLE(QSPI0_SSL),
+ PINMUX_SINGLE(QSPI1_SPCLK),
+ PINMUX_SINGLE(QSPI1_MOSI_IO0),
+ PINMUX_SINGLE(QSPI1_MISO_IO1),
+ PINMUX_SINGLE(QSPI1_IO2),
+ PINMUX_SINGLE(QSPI1_IO3),
+ PINMUX_SINGLE(QSPI1_SSL),
+ PINMUX_SINGLE(RPC_RESET_N),
+ PINMUX_SINGLE(RPC_WP_N),
+ PINMUX_SINGLE(RPC_INT_N),
+
+ /* IPSR0 */
+ PINMUX_IPSR_GPSR(IP0_3_0, DU_DR2),
+ PINMUX_IPSR_GPSR(IP0_3_0, SCK4),
+ PINMUX_IPSR_GPSR(IP0_3_0, GETHER_RMII_CRS_DV),
+ PINMUX_IPSR_GPSR(IP0_3_0, A0),
+
+ PINMUX_IPSR_GPSR(IP0_7_4, DU_DR3),
+ PINMUX_IPSR_GPSR(IP0_7_4, RX4),
+ PINMUX_IPSR_GPSR(IP0_7_4, GETHER_RMII_RX_ER),
+ PINMUX_IPSR_GPSR(IP0_7_4, A1),
+
+ PINMUX_IPSR_GPSR(IP0_11_8, DU_DR4),
+ PINMUX_IPSR_GPSR(IP0_11_8, TX4),
+ PINMUX_IPSR_GPSR(IP0_11_8, GETHER_RMII_RXD0),
+ PINMUX_IPSR_GPSR(IP0_11_8, A2),
+
+ PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5),
+ PINMUX_IPSR_GPSR(IP0_15_12, CTS4_N),
+ PINMUX_IPSR_GPSR(IP0_15_12, GETHER_RMII_RXD1),
+ PINMUX_IPSR_GPSR(IP0_15_12, A3),
+
+ PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6),
+ PINMUX_IPSR_GPSR(IP0_19_16, RTS4_N_TANS),
+ PINMUX_IPSR_GPSR(IP0_19_16, GETHER_RMII_TXD_EN),
+ PINMUX_IPSR_GPSR(IP0_19_16, A4),
+
+ PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7),
+ PINMUX_IPSR_GPSR(IP0_23_20, GETHER_RMII_TXD0),
+ PINMUX_IPSR_GPSR(IP0_23_20, A5),
+
+ PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2),
+ PINMUX_IPSR_GPSR(IP0_27_24, GETHER_RMII_TXD1),
+ PINMUX_IPSR_GPSR(IP0_27_24, A6),
+
+ PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
+ PINMUX_IPSR_GPSR(IP0_31_28, CPG_CPCKOUT),
+ PINMUX_IPSR_GPSR(IP0_31_28, GETHER_RMII_REFCLK),
+ PINMUX_IPSR_GPSR(IP0_31_28, A7),
+ PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
+
+ /* IPSR1 */
+ PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4),
+ PINMUX_IPSR_GPSR(IP1_3_0, SCL5),
+ PINMUX_IPSR_GPSR(IP1_3_0, A8),
+
+ PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5),
+ PINMUX_IPSR_GPSR(IP1_7_4, SDA5),
+ PINMUX_IPSR_MSEL(IP1_7_4, GETHER_MDC_B, SEL_GETHER_1),
+ PINMUX_IPSR_GPSR(IP1_7_4, A9),
+
+ PINMUX_IPSR_GPSR(IP1_11_8, DU_DG6),
+ PINMUX_IPSR_MSEL(IP1_11_8, SCIF_CLK_A, SEL_HSCIF0_0),
+ PINMUX_IPSR_MSEL(IP1_11_8, GETHER_MDIO_B, SEL_GETHER_1),
+ PINMUX_IPSR_GPSR(IP1_11_8, A10),
+
+ PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
+ PINMUX_IPSR_MSEL(IP1_15_12, HRX0_A, SEL_HSCIF0_0),
+ PINMUX_IPSR_GPSR(IP1_15_12, A11),
+
+ PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2),
+ PINMUX_IPSR_MSEL(IP1_19_16, HSCK0_A, SEL_HSCIF0_0),
+ PINMUX_IPSR_GPSR(IP1_19_16, A12),
+ PINMUX_IPSR_GPSR(IP1_19_16, IRQ1),
+
+ PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3),
+ PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_A, SEL_HSCIF0_0),
+ PINMUX_IPSR_GPSR(IP1_23_20, A13),
+ PINMUX_IPSR_GPSR(IP1_23_20, IRQ2),
+
+ PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4),
+ PINMUX_IPSR_MSEL(IP1_27_24, HCTS0_N_A, SEL_HSCIF0_0),
+ PINMUX_IPSR_GPSR(IP1_27_24, A14),
+ PINMUX_IPSR_GPSR(IP1_27_24, IRQ3),
+
+ PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5),
+ PINMUX_IPSR_MSEL(IP1_31_28, HTX0_A, SEL_HSCIF0_0),
+ PINMUX_IPSR_MSEL(IP1_31_28, PWM0_A, SEL_PWM0_0),
+ PINMUX_IPSR_GPSR(IP1_31_28, A15),
+
+ /* IPSR2 */
+ PINMUX_IPSR_GPSR(IP2_3_0, DU_DB6),
+ PINMUX_IPSR_GPSR(IP2_3_0, MSIOF3_RXD),
+ PINMUX_IPSR_GPSR(IP2_3_0, A16),
+
+ PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7),
+ PINMUX_IPSR_GPSR(IP2_7_4, MSIOF3_TXD),
+ PINMUX_IPSR_GPSR(IP2_7_4, A17),
+
+ PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT),
+ PINMUX_IPSR_GPSR(IP2_11_8, MSIOF3_SS1),
+ PINMUX_IPSR_MSEL(IP2_11_8, GETHER_LINK_B, SEL_GETHER_1),
+ PINMUX_IPSR_GPSR(IP2_11_8, A18),
+
+ PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC),
+ PINMUX_IPSR_GPSR(IP2_15_12, MSIOF3_SS2),
+ PINMUX_IPSR_MSEL(IP2_15_12, GETHER_PHY_INT_B, SEL_GETHER_1),
+ PINMUX_IPSR_GPSR(IP2_15_12, A19),
+ PINMUX_IPSR_GPSR(IP2_15_12, FXR_TXENA_N),
+
+ PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC),
+ PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK),
+ PINMUX_IPSR_GPSR(IP2_19_16, FXR_TXENB_N),
+
+ PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE),
+ PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
+
+ PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
+ PINMUX_IPSR_GPSR(IP2_27_24, CC5_OSCOUT),
+
+ PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
+ PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
+ PINMUX_IPSR_GPSR(IP2_31_28, SCK3),
+ PINMUX_IPSR_GPSR(IP2_31_28, HSCK3),
+
+ /* IPSR3 */
+ PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB),
+ PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD),
+ PINMUX_IPSR_GPSR(IP3_3_0, RX3),
+ PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N),
+ PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N),
+
+ PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N),
+ PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
+ PINMUX_IPSR_GPSR(IP3_7_4, TX3),
+ PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N),
+
+ PINMUX_IPSR_GPSR(IP3_11_8, VI0_VSYNC_N),
+ PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_SYNC),
+ PINMUX_IPSR_GPSR(IP3_11_8, CTS3_N),
+ PINMUX_IPSR_GPSR(IP3_11_8, HTX3),
+
+ PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
+ PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
+ PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N_TANS),
+ PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
+
+ PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
+ PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2),
+ PINMUX_IPSR_GPSR(IP3_19_16, SCK1),
+ PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0),
+
+ PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2),
+ PINMUX_IPSR_GPSR(IP3_23_20, AVB_AVTP_PPS),
+
+ PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3),
+ PINMUX_IPSR_GPSR(IP3_27_24, HSCK1),
+
+ PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4),
+ PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N),
+ PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0),
+
+ /* IPSR4 */
+ PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5),
+ PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N),
+ PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0),
+
+ PINMUX_IPSR_GPSR(IP4_7_4, VI0_DATA6),
+ PINMUX_IPSR_GPSR(IP4_7_4, HTX1),
+ PINMUX_IPSR_GPSR(IP4_7_4, CTS1_N),
+
+ PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7),
+ PINMUX_IPSR_GPSR(IP4_11_8, HRX1),
+ PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N_TANS),
+
+ PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
+ PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
+
+ PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9),
+ PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N),
+ PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0),
+
+ PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10),
+ PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N),
+ PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0),
+
+ PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11),
+ PINMUX_IPSR_GPSR(IP4_27_24, HTX2),
+ PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0),
+
+ PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD),
+ PINMUX_IPSR_GPSR(IP4_31_28, HRX2),
+ PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0),
+ PINMUX_IPSR_GPSR(IP4_31_28, CS1_N),
+
+ /* IPSR5 */
+ PINMUX_IPSR_GPSR(IP5_3_0, VI1_CLK),
+ PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
+ PINMUX_IPSR_GPSR(IP5_3_0, CS0_N),
+
+ PINMUX_IPSR_GPSR(IP5_7_4, VI1_CLKENB),
+ PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
+ PINMUX_IPSR_GPSR(IP5_7_4, D0),
+
+ PINMUX_IPSR_GPSR(IP5_11_8, VI1_HSYNC_N),
+ PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
+ PINMUX_IPSR_GPSR(IP5_11_8, D1),
+
+ PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N),
+ PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC),
+ PINMUX_IPSR_GPSR(IP5_15_12, D2),
+
+ PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0),
+ PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1),
+ PINMUX_IPSR_GPSR(IP5_19_16, D3),
+ PINMUX_IPSR_GPSR(IP5_19_16, MMC_WP),
+
+ PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1),
+ PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2),
+ PINMUX_IPSR_GPSR(IP5_23_20, D4),
+ PINMUX_IPSR_GPSR(IP5_23_20, MMC_CD),
+
+ PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
+ PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
+ PINMUX_IPSR_GPSR(IP5_27_24, D5),
+ PINMUX_IPSR_GPSR(IP5_27_24, MMC_DS),
+
+ PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3),
+ PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1),
+ PINMUX_IPSR_GPSR(IP5_31_28, D6),
+ PINMUX_IPSR_GPSR(IP5_31_28, MMC_CMD),
+
+ /* IPSR6 */
+ PINMUX_IPSR_GPSR(IP6_3_0, VI1_DATA4),
+ PINMUX_IPSR_MSEL(IP6_3_0, CANFD_CLK_B, SEL_CANFD0_1),
+ PINMUX_IPSR_GPSR(IP6_3_0, D7),
+ PINMUX_IPSR_GPSR(IP6_3_0, MMC_D0),
+
+ PINMUX_IPSR_GPSR(IP6_7_4, VI1_DATA5),
+ PINMUX_IPSR_GPSR(IP6_7_4, D8),
+ PINMUX_IPSR_GPSR(IP6_7_4, MMC_D1),
+
+ PINMUX_IPSR_GPSR(IP6_11_8, VI1_DATA6),
+ PINMUX_IPSR_GPSR(IP6_11_8, D9),
+ PINMUX_IPSR_GPSR(IP6_11_8, MMC_D2),
+
+ PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7),
+ PINMUX_IPSR_GPSR(IP6_15_12, D10),
+ PINMUX_IPSR_GPSR(IP6_15_12, MMC_D3),
+
+ PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8),
+ PINMUX_IPSR_GPSR(IP6_19_16, D11),
+ PINMUX_IPSR_GPSR(IP6_19_16, MMC_CLK),
+
+ PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9),
+ PINMUX_IPSR_MSEL(IP6_23_20, TCLK1_A, SEL_TMU_0),
+ PINMUX_IPSR_GPSR(IP6_23_20, D12),
+ PINMUX_IPSR_GPSR(IP6_23_20, MMC_D4),
+
+ PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10),
+ PINMUX_IPSR_MSEL(IP6_27_24, TCLK2_A, SEL_TMU_0),
+ PINMUX_IPSR_GPSR(IP6_27_24, D13),
+ PINMUX_IPSR_GPSR(IP6_27_24, MMC_D5),
+
+ PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11),
+ PINMUX_IPSR_GPSR(IP6_31_28, SCL4),
+ PINMUX_IPSR_GPSR(IP6_31_28, D14),
+ PINMUX_IPSR_GPSR(IP6_31_28, MMC_D6),
+
+ /* IPSR7 */
+ PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD),
+ PINMUX_IPSR_GPSR(IP7_3_0, SDA4),
+ PINMUX_IPSR_GPSR(IP7_3_0, D15),
+ PINMUX_IPSR_GPSR(IP7_3_0, MMC_D7),
+
+ PINMUX_IPSR_GPSR(IP7_7_4, SCL0),
+ PINMUX_IPSR_GPSR(IP7_7_4, CLKOUT),
+
+ PINMUX_IPSR_GPSR(IP7_11_8, SDA0),
+ PINMUX_IPSR_GPSR(IP7_11_8, BS_N),
+ PINMUX_IPSR_GPSR(IP7_11_8, SCK0),
+ PINMUX_IPSR_MSEL(IP7_11_8, HSCK0_B, SEL_HSCIF0_1),
+
+ PINMUX_IPSR_GPSR(IP7_15_12, SCL1),
+ PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2),
+ PINMUX_IPSR_GPSR(IP7_15_12, RD_N),
+ PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N),
+ PINMUX_IPSR_GPSR(IP7_15_12, HCTS0_N_B),
+
+ PINMUX_IPSR_GPSR(IP7_19_16, SDA1),
+ PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
+ PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
+ PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N_TANS),
+ PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_B, SEL_HSCIF0_1),
+
+ PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
+ PINMUX_IPSR_GPSR(IP7_23_20, WE1_N),
+ PINMUX_IPSR_GPSR(IP7_23_20, RX0),
+ PINMUX_IPSR_MSEL(IP7_23_20, HRX0_B, SEL_HSCIF0_1),
+
+ PINMUX_IPSR_GPSR(IP7_27_24, SDA2),
+ PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0),
+ PINMUX_IPSR_GPSR(IP7_27_24, TX0),
+ PINMUX_IPSR_MSEL(IP7_27_24, HTX0_B, SEL_HSCIF0_1),
+
+ PINMUX_IPSR_GPSR(IP7_31_28, AVB_AVTP_MATCH),
+ PINMUX_IPSR_GPSR(IP7_31_28, TPU0TO0),
+
+ /* IPSR8 */
+ PINMUX_IPSR_GPSR(IP8_3_0, AVB_AVTP_CAPTURE),
+ PINMUX_IPSR_GPSR(IP8_3_0, TPU0TO1),
+
+ PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_TX_A, SEL_CANFD0_0),
+ PINMUX_IPSR_GPSR(IP8_7_4, FXR_TXDA),
+ PINMUX_IPSR_MSEL(IP8_7_4, PWM0_B, SEL_PWM0_1),
+ PINMUX_IPSR_GPSR(IP8_7_4, DU_DISP),
+
+ PINMUX_IPSR_MSEL(IP8_11_8, CANFD0_RX_A, SEL_CANFD0_0),
+ PINMUX_IPSR_GPSR(IP8_11_8, RXDA_EXTFXR),
+ PINMUX_IPSR_MSEL(IP8_11_8, PWM1_B, SEL_PWM1_1),
+ PINMUX_IPSR_GPSR(IP8_11_8, DU_CDE),
+
+ PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_TX),
+ PINMUX_IPSR_GPSR(IP8_15_12, FXR_TXDB),
+ PINMUX_IPSR_MSEL(IP8_15_12, PWM2_B, SEL_PWM2_1),
+ PINMUX_IPSR_MSEL(IP8_15_12, TCLK1_B, SEL_TMU_1),
+ PINMUX_IPSR_MSEL(IP8_15_12, TX1_B, SEL_SCIF1_1),
+
+ PINMUX_IPSR_GPSR(IP8_19_16, CANFD1_RX),
+ PINMUX_IPSR_GPSR(IP8_19_16, RXDB_EXTFXR),
+ PINMUX_IPSR_MSEL(IP8_19_16, PWM3_B, SEL_PWM3_1),
+ PINMUX_IPSR_MSEL(IP8_19_16, TCLK2_B, SEL_TMU_1),
+ PINMUX_IPSR_MSEL(IP8_19_16, RX1_B, SEL_SCIF1_1),
+
+ PINMUX_IPSR_MSEL(IP8_23_20, CANFD_CLK_A, SEL_CANFD0_0),
+ PINMUX_IPSR_GPSR(IP8_23_20, CLK_EXTFXR),
+ PINMUX_IPSR_MSEL(IP8_23_20, PWM4_B, SEL_PWM4_1),
+ PINMUX_IPSR_MSEL(IP8_23_20, SPEEDIN_B, SEL_RSP_1),
+ PINMUX_IPSR_MSEL(IP8_23_20, SCIF_CLK_B, SEL_HSCIF0_1),
+
+ PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKIN),
+ PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_IN),
+
+ PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKOUT),
+ PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKEN_OUT),
+
+ /* IPSR9 */
+ PINMUX_IPSR_GPSR(IP9_3_0, IRQ4),
+ PINMUX_IPSR_GPSR(IP9_3_0, VI0_DATA12),
+
+ PINMUX_IPSR_GPSR(IP9_7_4, IRQ5),
+ PINMUX_IPSR_GPSR(IP9_7_4, VI0_DATA13),
+
+ PINMUX_IPSR_GPSR(IP9_11_8, MSIOF0_RXD),
+ PINMUX_IPSR_GPSR(IP9_11_8, DU_DR0),
+ PINMUX_IPSR_GPSR(IP9_11_8, VI0_DATA14),
+
+ PINMUX_IPSR_GPSR(IP9_15_12, MSIOF0_TXD),
+ PINMUX_IPSR_GPSR(IP9_15_12, DU_DR1),
+ PINMUX_IPSR_GPSR(IP9_15_12, VI0_DATA15),
+
+ PINMUX_IPSR_GPSR(IP9_19_16, MSIOF0_SCK),
+ PINMUX_IPSR_GPSR(IP9_19_16, DU_DG0),
+ PINMUX_IPSR_GPSR(IP9_19_16, VI0_DATA16),
+
+ PINMUX_IPSR_GPSR(IP9_23_20, MSIOF0_SYNC),
+ PINMUX_IPSR_GPSR(IP9_23_20, DU_DG1),
+ PINMUX_IPSR_GPSR(IP9_23_20, VI0_DATA17),
+
+ PINMUX_IPSR_GPSR(IP9_27_24, MSIOF0_SS1),
+ PINMUX_IPSR_GPSR(IP9_27_24, DU_DB0),
+ PINMUX_IPSR_GPSR(IP9_27_24, TCLK3),
+ PINMUX_IPSR_GPSR(IP9_27_24, VI0_DATA18),
+
+ PINMUX_IPSR_GPSR(IP9_31_28, MSIOF0_SS2),
+ PINMUX_IPSR_GPSR(IP9_31_28, DU_DB1),
+ PINMUX_IPSR_GPSR(IP9_31_28, TCLK4),
+ PINMUX_IPSR_GPSR(IP9_31_28, VI0_DATA19),
+
+ /* IPSR10 */
+ PINMUX_IPSR_GPSR(IP10_3_0, SCL3),
+ PINMUX_IPSR_GPSR(IP10_3_0, VI0_DATA20),
+
+ PINMUX_IPSR_GPSR(IP10_7_4, SDA3),
+ PINMUX_IPSR_GPSR(IP10_7_4, VI0_DATA21),
+
+ PINMUX_IPSR_GPSR(IP10_11_8, FSO_CFE_0_N),
+ PINMUX_IPSR_GPSR(IP10_11_8, VI0_DATA22),
+
+ PINMUX_IPSR_GPSR(IP10_15_12, FSO_CFE_1_N),
+ PINMUX_IPSR_GPSR(IP10_15_12, VI0_DATA23),
+
+ PINMUX_IPSR_GPSR(IP10_19_16, FSO_TOE_N),
+};
+
+static const struct sh_pfc_pin pinmux_pins[] = {
+ PINMUX_GPIO_GP_ALL(),
+};
+
+/* - AVB -------------------------------------------------------------------- */
+static const unsigned int avb_link_pins[] = {
+ /* AVB_LINK */
+ RCAR_GP_PIN(1, 18),
+};
+static const unsigned int avb_link_mux[] = {
+ AVB_LINK_MARK,
+};
+static const unsigned int avb_magic_pins[] = {
+ /* AVB_MAGIC */
+ RCAR_GP_PIN(1, 16),
+};
+static const unsigned int avb_magic_mux[] = {
+ AVB_MAGIC_MARK,
+};
+static const unsigned int avb_phy_int_pins[] = {
+ /* AVB_PHY_INT */
+ RCAR_GP_PIN(1, 17),
+};
+static const unsigned int avb_phy_int_mux[] = {
+ AVB_PHY_INT_MARK,
+};
+static const unsigned int avb_mdio_pins[] = {
+ /* AVB_MDC, AVB_MDIO */
+ RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
+};
+static const unsigned int avb_mdio_mux[] = {
+ AVB_MDC_MARK, AVB_MDIO_MARK,
+};
+static const unsigned int avb_rgmii_pins[] = {
+ /*
+ * AVB_TX_CTL, AVB_TXC, AVB_TD0, AVB_TD1, AVB_TD2, AVB_TD3,
+ * AVB_RX_CTL, AVB_RXC, AVB_RD0, AVB_RD1, AVB_RD2, AVB_RD3,
+ */
+ RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
+ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
+ RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
+ RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
+ RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
+ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
+};
+static const unsigned int avb_rgmii_mux[] = {
+ AVB_TX_CTL_MARK, AVB_TXC_MARK,
+ AVB_TD0_MARK, AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
+ AVB_RX_CTL_MARK, AVB_RXC_MARK,
+ AVB_RD0_MARK, AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
+};
+static const unsigned int avb_txcrefclk_pins[] = {
+ /* AVB_TXCREFCLK */
+ RCAR_GP_PIN(1, 13),
+};
+static const unsigned int avb_txcrefclk_mux[] = {
+ AVB_TXCREFCLK_MARK,
+};
+static const unsigned int avb_avtp_pps_pins[] = {
+ /* AVB_AVTP_PPS */
+ RCAR_GP_PIN(2, 6),
+};
+static const unsigned int avb_avtp_pps_mux[] = {
+ AVB_AVTP_PPS_MARK,
+};
+static const unsigned int avb_avtp_capture_pins[] = {
+ /* AVB_AVTP_CAPTURE */
+ RCAR_GP_PIN(1, 20),
+};
+static const unsigned int avb_avtp_capture_mux[] = {
+ AVB_AVTP_CAPTURE_MARK,
+};
+static const unsigned int avb_avtp_match_pins[] = {
+ /* AVB_AVTP_MATCH */
+ RCAR_GP_PIN(1, 19),
+};
+static const unsigned int avb_avtp_match_mux[] = {
+ AVB_AVTP_MATCH_MARK,
+};
+
+/* - CANFD0 ----------------------------------------------------------------- */
+static const unsigned int canfd0_data_a_pins[] = {
+ /* CANFD0_TX, CANFD0_RX */
+ RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
+};
+static const unsigned int canfd0_data_a_mux[] = {
+ CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
+};
+static const unsigned int canfd0_data_b_pins[] = {
+ /* CANFD0_TX, CANFD0_RX */
+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+};
+static const unsigned int canfd0_data_b_mux[] = {
+ CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
+};
+
+/* - CANFD1 ----------------------------------------------------------------- */
+static const unsigned int canfd1_data_pins[] = {
+ /* CANFD1_TX, CANFD1_RX */
+ RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
+};
+static const unsigned int canfd1_data_mux[] = {
+ CANFD1_TX_MARK, CANFD1_RX_MARK,
+};
+
+/* - CANFD Clock ------------------------------------------------------------ */
+static const unsigned int canfd_clk_a_pins[] = {
+ /* CANFD_CLK */
+ RCAR_GP_PIN(1, 25),
+};
+static const unsigned int canfd_clk_a_mux[] = {
+ CANFD_CLK_A_MARK,
+};
+static const unsigned int canfd_clk_b_pins[] = {
+ /* CANFD_CLK */
+ RCAR_GP_PIN(3, 8),
+};
+static const unsigned int canfd_clk_b_mux[] = {
+ CANFD_CLK_B_MARK,
+};
+
+/* - DU --------------------------------------------------------------------- */
+static const unsigned int du_rgb666_pins[] = {
+ /* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */
+ RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
+ RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
+ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
+ RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
+ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
+};
+static const unsigned int du_rgb666_mux[] = {
+ DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
+ DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
+ DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
+ DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
+ DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
+ DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
+};
+static const unsigned int du_rgb888_pins[] = {
+ /* DU_DR[7:0], DU_DG[7:0], DU_DB[7:0] */
+ RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
+ RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19),
+ RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
+ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
+ RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
+ RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
+ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
+ RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
+};
+static const unsigned int du_rgb888_mux[] = {
+ DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
+ DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
+ DU_DR1_MARK, DU_DR0_MARK,
+ DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
+ DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
+ DU_DG1_MARK, DU_DG0_MARK,
+ DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
+ DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
+ DU_DB1_MARK, DU_DB0_MARK,
+};
+static const unsigned int du_clk_out_pins[] = {
+ /* DU_DOTCLKOUT */
+ RCAR_GP_PIN(0, 18),
+};
+static const unsigned int du_clk_out_mux[] = {
+ DU_DOTCLKOUT_MARK,
+};
+static const unsigned int du_sync_pins[] = {
+ /* DU_EXVSYNC/DU_VSYNC, DU_EXHSYNC/DU_HSYNC */
+ RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
+};
+static const unsigned int du_sync_mux[] = {
+ DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK,
+};
+static const unsigned int du_oddf_pins[] = {
+ /* DU_EXODDF/DU_ODDF/DISP/CDE */
+ RCAR_GP_PIN(0, 21),
+};
+static const unsigned int du_oddf_mux[] = {
+ DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
+};
+static const unsigned int du_cde_pins[] = {
+ /* DU_CDE */
+ RCAR_GP_PIN(1, 22),
+};
+static const unsigned int du_cde_mux[] = {
+ DU_CDE_MARK,
+};
+static const unsigned int du_disp_pins[] = {
+ /* DU_DISP */
+ RCAR_GP_PIN(1, 21),
+};
+static const unsigned int du_disp_mux[] = {
+ DU_DISP_MARK,
+};
+
+/* - GETHER ----------------------------------------------------------------- */
+static const unsigned int gether_link_a_pins[] = {
+ /* GETHER_LINK */
+ RCAR_GP_PIN(4, 24),
+};
+static const unsigned int gether_link_a_mux[] = {
+ GETHER_LINK_A_MARK,
+};
+static const unsigned int gether_phy_int_a_pins[] = {
+ /* GETHER_PHY_INT */
+ RCAR_GP_PIN(4, 23),
+};
+static const unsigned int gether_phy_int_a_mux[] = {
+ GETHER_PHY_INT_A_MARK,
+};
+static const unsigned int gether_mdio_a_pins[] = {
+ /* GETHER_MDC, GETHER_MDIO */
+ RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
+};
+static const unsigned int gether_mdio_a_mux[] = {
+ GETHER_MDC_A_MARK, GETHER_MDIO_A_MARK,
+};
+static const unsigned int gether_link_b_pins[] = {
+ /* GETHER_LINK */
+ RCAR_GP_PIN(0, 18),
+};
+static const unsigned int gether_link_b_mux[] = {
+ GETHER_LINK_B_MARK,
+};
+static const unsigned int gether_phy_int_b_pins[] = {
+ /* GETHER_PHY_INT */
+ RCAR_GP_PIN(0, 19),
+};
+static const unsigned int gether_phy_int_b_mux[] = {
+ GETHER_PHY_INT_B_MARK,
+};
+static const unsigned int gether_mdio_b_mux[] = {
+ GETHER_MDC_B_MARK, GETHER_MDIO_B_MARK,
+};
+static const unsigned int gether_mdio_b_pins[] = {
+ /* GETHER_MDC, GETHER_MDIO */
+ RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
+};
+static const unsigned int gether_magic_pins[] = {
+ /* GETHER_MAGIC */
+ RCAR_GP_PIN(4, 22),
+};
+static const unsigned int gether_magic_mux[] = {
+ GETHER_MAGIC_MARK,
+};
+static const unsigned int gether_rgmii_pins[] = {
+ /*
+ * GETHER_TX_CTL, GETHER_TXC,
+ * GETHER_TD0, GETHER_TD1, GETHER_TD2, GETHER_TD3,
+ * GETHER_RX_CTL, GETHER_RXC,
+ * GETHER_RD0, GETHER_RD1, GETHER_RD2, GETHER_RD3,
+ */
+ RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
+ RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
+ RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
+ RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
+ RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
+ RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
+};
+static const unsigned int gether_rgmii_mux[] = {
+ GETHER_TX_CTL_MARK, GETHER_TXC_MARK,
+ GETHER_TD0_MARK, GETHER_TD1_MARK,
+ GETHER_TD2_MARK, GETHER_TD3_MARK,
+ GETHER_RX_CTL_MARK, GETHER_RXC_MARK,
+ GETHER_RD0_MARK, AVB_RD1_MARK,
+ GETHER_RD2_MARK, AVB_RD3_MARK,
+};
+static const unsigned int gether_txcrefclk_pins[] = {
+ /* GETHER_TXCREFCLK */
+ RCAR_GP_PIN(4, 18),
+};
+static const unsigned int gether_txcrefclk_mux[] = {
+ GETHER_TXCREFCLK_MARK,
+};
+static const unsigned int gether_txcrefclk_mega_pins[] = {
+ /* GETHER_TXCREFCLK_MEGA */
+ RCAR_GP_PIN(4, 19),
+};
+static const unsigned int gether_txcrefclk_mega_mux[] = {
+ GETHER_TXCREFCLK_MEGA_MARK,
+};
+static const unsigned int gether_rmii_pins[] = {
+ /*
+ * GETHER_RMII_CRS_DV, GETHER_RMII_RX_ER,
+ * GETHER_RMII_RXD0, GETHER_RMII_RXD1,
+ * GETHER_RMII_TXD_EN, GETHER_RMII_TXD0,
+ * GETHER_RMII_TXD1, GETHER_RMII_REFCLK
+ */
+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+};
+static const unsigned int gether_rmii_mux[] = {
+ GETHER_RMII_CRS_DV_MARK, GETHER_RMII_RX_ER_MARK,
+ GETHER_RMII_RXD0_MARK, GETHER_RMII_RXD1_MARK,
+ GETHER_RMII_TXD_EN_MARK, GETHER_RMII_TXD0_MARK,
+ GETHER_RMII_TXD1_MARK, GETHER_RMII_REFCLK_MARK,
+};
+
+/* - HSCIF0 ----------------------------------------------------------------- */
+static const unsigned int hscif0_data_a_pins[] = {
+ /* HRX0, HTX0 */
+ RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 15),
+};
+static const unsigned int hscif0_data_a_mux[] = {
+ HRX0_A_MARK, HTX0_A_MARK,
+};
+static const unsigned int hscif0_clk_a_pins[] = {
+ /* HSCK0 */
+ RCAR_GP_PIN(0, 12),
+};
+static const unsigned int hscif0_clk_a_mux[] = {
+ HSCK0_A_MARK,
+};
+static const unsigned int hscif0_ctrl_a_pins[] = {
+ /* HRTS0#, HCTS0# */
+ RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
+};
+static const unsigned int hscif0_ctrl_a_mux[] = {
+ HRTS0_N_A_MARK, HCTS0_N_A_MARK,
+};
+static const unsigned int hscif0_data_b_pins[] = {
+ /* HRX0, HTX0 */
+ RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
+};
+static const unsigned int hscif0_data_b_mux[] = {
+ HRX0_B_MARK, HTX0_B_MARK,
+};
+static const unsigned int hscif0_clk_b_pins[] = {
+ /* HSCK0 */
+ RCAR_GP_PIN(4, 1),
+};
+static const unsigned int hscif0_clk_b_mux[] = {
+ HSCK0_B_MARK,
+};
+static const unsigned int hscif0_ctrl_b_pins[] = {
+ /* HRTS0#, HCTS0# */
+ RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
+};
+static const unsigned int hscif0_ctrl_b_mux[] = {
+ HRTS0_N_B_MARK, HCTS0_N_B_MARK,
+};
+
+/* - HSCIF1 ----------------------------------------------------------------- */
+static const unsigned int hscif1_data_pins[] = {
+ /* HRX1, HTX1 */
+ RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
+};
+static const unsigned int hscif1_data_mux[] = {
+ HRX1_MARK, HTX1_MARK,
+};
+static const unsigned int hscif1_clk_pins[] = {
+ /* HSCK1 */
+ RCAR_GP_PIN(2, 7),
+};
+static const unsigned int hscif1_clk_mux[] = {
+ HSCK1_MARK,
+};
+static const unsigned int hscif1_ctrl_pins[] = {
+ /* HRTS1#, HCTS1# */
+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+};
+static const unsigned int hscif1_ctrl_mux[] = {
+ HRTS1_N_MARK, HCTS1_N_MARK,
+};
+
+/* - HSCIF2 ----------------------------------------------------------------- */
+static const unsigned int hscif2_data_pins[] = {
+ /* HRX2, HTX2 */
+ RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
+};
+static const unsigned int hscif2_data_mux[] = {
+ HRX2_MARK, HTX2_MARK,
+};
+static const unsigned int hscif2_clk_pins[] = {
+ /* HSCK2 */
+ RCAR_GP_PIN(2, 12),
+};
+static const unsigned int hscif2_clk_mux[] = {
+ HSCK2_MARK,
+};
+static const unsigned int hscif2_ctrl_pins[] = {
+ /* HRTS2#, HCTS2# */
+ RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
+};
+static const unsigned int hscif2_ctrl_mux[] = {
+ HRTS2_N_MARK, HCTS2_N_MARK,
+};
+
+/* - HSCIF3 ----------------------------------------------------------------- */
+static const unsigned int hscif3_data_pins[] = {
+ /* HRX3, HTX3 */
+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
+};
+static const unsigned int hscif3_data_mux[] = {
+ HRX3_MARK, HTX3_MARK,
+};
+static const unsigned int hscif3_clk_pins[] = {
+ /* HSCK3 */
+ RCAR_GP_PIN(2, 0),
+};
+static const unsigned int hscif3_clk_mux[] = {
+ HSCK3_MARK,
+};
+static const unsigned int hscif3_ctrl_pins[] = {
+ /* HRTS3#, HCTS3# */
+ RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
+};
+static const unsigned int hscif3_ctrl_mux[] = {
+ HRTS3_N_MARK, HCTS3_N_MARK,
+};
+
+/* - I2C0 ------------------------------------------------------------------- */
+static const unsigned int i2c0_pins[] = {
+ /* SDA0, SCL0 */
+ RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
+};
+static const unsigned int i2c0_mux[] = {
+ SDA0_MARK, SCL0_MARK,
+};
+
+/* - I2C1 ------------------------------------------------------------------- */
+static const unsigned int i2c1_pins[] = {
+ /* SDA1, SCL1 */
+ RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
+};
+static const unsigned int i2c1_mux[] = {
+ SDA1_MARK, SCL1_MARK,
+};
+
+/* - I2C2 ------------------------------------------------------------------- */
+static const unsigned int i2c2_pins[] = {
+ /* SDA2, SCL2 */
+ RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
+};
+static const unsigned int i2c2_mux[] = {
+ SDA2_MARK, SCL2_MARK,
+};
+
+/* - I2C3 ------------------------------------------------------------------- */
+static const unsigned int i2c3_pins[] = {
+ /* SDA3, SCL3 */
+ RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
+};
+static const unsigned int i2c3_mux[] = {
+ SDA3_MARK, SCL3_MARK,
+};
+
+/* - I2C4 ------------------------------------------------------------------- */
+static const unsigned int i2c4_pins[] = {
+ /* SDA4, SCL4 */
+ RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
+};
+static const unsigned int i2c4_mux[] = {
+ SDA4_MARK, SCL4_MARK,
+};
+
+/* - I2C5 ------------------------------------------------------------------- */
+static const unsigned int i2c5_pins[] = {
+ /* SDA5, SCL5 */
+ RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
+};
+static const unsigned int i2c5_mux[] = {
+ SDA5_MARK, SCL5_MARK,
+};
+
+/* - INTC-EX ---------------------------------------------------------------- */
+static const unsigned int intc_ex_irq0_pins[] = {
+ /* IRQ0 */
+ RCAR_GP_PIN(1, 0),
+};
+static const unsigned int intc_ex_irq0_mux[] = {
+ IRQ0_MARK,
+};
+static const unsigned int intc_ex_irq1_pins[] = {
+ /* IRQ1 */
+ RCAR_GP_PIN(0, 12),
+};
+static const unsigned int intc_ex_irq1_mux[] = {
+ IRQ1_MARK,
+};
+static const unsigned int intc_ex_irq2_pins[] = {
+ /* IRQ2 */
+ RCAR_GP_PIN(0, 13),
+};
+static const unsigned int intc_ex_irq2_mux[] = {
+ IRQ2_MARK,
+};
+static const unsigned int intc_ex_irq3_pins[] = {
+ /* IRQ3 */
+ RCAR_GP_PIN(0, 14),
+};
+static const unsigned int intc_ex_irq3_mux[] = {
+ IRQ3_MARK,
+};
+static const unsigned int intc_ex_irq4_pins[] = {
+ /* IRQ4 */
+ RCAR_GP_PIN(2, 17),
+};
+static const unsigned int intc_ex_irq4_mux[] = {
+ IRQ4_MARK,
+};
+static const unsigned int intc_ex_irq5_pins[] = {
+ /* IRQ5 */
+ RCAR_GP_PIN(2, 18),
+};
+static const unsigned int intc_ex_irq5_mux[] = {
+ IRQ5_MARK,
+};
+
+/* - MMC -------------------------------------------------------------------- */
+static const unsigned int mmc_data1_pins[] = {
+ /* MMC_D0 */
+ RCAR_GP_PIN(3, 8),
+};
+static const unsigned int mmc_data1_mux[] = {
+ MMC_D0_MARK,
+};
+static const unsigned int mmc_data4_pins[] = {
+ /* MMC_D[0:3] */
+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+};
+static const unsigned int mmc_data4_mux[] = {
+ MMC_D0_MARK, MMC_D1_MARK,
+ MMC_D2_MARK, MMC_D3_MARK,
+};
+static const unsigned int mmc_data8_pins[] = {
+ /* MMC_D[0:7] */
+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+ RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
+ RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
+};
+static const unsigned int mmc_data8_mux[] = {
+ MMC_D0_MARK, MMC_D1_MARK,
+ MMC_D2_MARK, MMC_D3_MARK,
+ MMC_D4_MARK, MMC_D5_MARK,
+ MMC_D6_MARK, MMC_D7_MARK,
+};
+static const unsigned int mmc_ctrl_pins[] = {
+ /* MMC_CLK, MMC_CMD */
+ RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 7),
+};
+static const unsigned int mmc_ctrl_mux[] = {
+ MMC_CLK_MARK, MMC_CMD_MARK,
+};
+static const unsigned int mmc_cd_pins[] = {
+ /* MMC_CD */
+ RCAR_GP_PIN(3, 5),
+};
+static const unsigned int mmc_cd_mux[] = {
+ MMC_CD_MARK,
+};
+static const unsigned int mmc_wp_pins[] = {
+ /* MMC_WP */
+ RCAR_GP_PIN(3, 4),
+};
+static const unsigned int mmc_wp_mux[] = {
+ MMC_WP_MARK,
+};
+static const unsigned int mmc_ds_pins[] = {
+ /* MMC_DS */
+ RCAR_GP_PIN(3, 6),
+};
+static const unsigned int mmc_ds_mux[] = {
+ MMC_DS_MARK,
+};
+
+/* - MSIOF0 ----------------------------------------------------------------- */
+static const unsigned int msiof0_clk_pins[] = {
+ /* MSIOF0_SCK */
+ RCAR_GP_PIN(2, 21),
+};
+static const unsigned int msiof0_clk_mux[] = {
+ MSIOF0_SCK_MARK,
+};
+static const unsigned int msiof0_sync_pins[] = {
+ /* MSIOF0_SYNC */
+ RCAR_GP_PIN(2, 22),
+};
+static const unsigned int msiof0_sync_mux[] = {
+ MSIOF0_SYNC_MARK,
+};
+static const unsigned int msiof0_ss1_pins[] = {
+ /* MSIOF0_SS1 */
+ RCAR_GP_PIN(2, 23),
+};
+static const unsigned int msiof0_ss1_mux[] = {
+ MSIOF0_SS1_MARK,
+};
+static const unsigned int msiof0_ss2_pins[] = {
+ /* MSIOF0_SS2 */
+ RCAR_GP_PIN(2, 24),
+};
+static const unsigned int msiof0_ss2_mux[] = {
+ MSIOF0_SS2_MARK,
+};
+static const unsigned int msiof0_txd_pins[] = {
+ /* MSIOF0_TXD */
+ RCAR_GP_PIN(2, 20),
+};
+static const unsigned int msiof0_txd_mux[] = {
+ MSIOF0_TXD_MARK,
+};
+static const unsigned int msiof0_rxd_pins[] = {
+ /* MSIOF0_RXD */
+ RCAR_GP_PIN(2, 19),
+};
+static const unsigned int msiof0_rxd_mux[] = {
+ MSIOF0_RXD_MARK,
+};
+
+/* - MSIOF1 ----------------------------------------------------------------- */
+static const unsigned int msiof1_clk_pins[] = {
+ /* MSIOF1_SCK */
+ RCAR_GP_PIN(3, 2),
+};
+static const unsigned int msiof1_clk_mux[] = {
+ MSIOF1_SCK_MARK,
+};
+static const unsigned int msiof1_sync_pins[] = {
+ /* MSIOF1_SYNC */
+ RCAR_GP_PIN(3, 3),
+};
+static const unsigned int msiof1_sync_mux[] = {
+ MSIOF1_SYNC_MARK,
+};
+static const unsigned int msiof1_ss1_pins[] = {
+ /* MSIOF1_SS1 */
+ RCAR_GP_PIN(3, 4),
+};
+static const unsigned int msiof1_ss1_mux[] = {
+ MSIOF1_SS1_MARK,
+};
+static const unsigned int msiof1_ss2_pins[] = {
+ /* MSIOF1_SS2 */
+ RCAR_GP_PIN(3, 5),
+};
+static const unsigned int msiof1_ss2_mux[] = {
+ MSIOF1_SS2_MARK,
+};
+static const unsigned int msiof1_txd_pins[] = {
+ /* MSIOF1_TXD */
+ RCAR_GP_PIN(3, 1),
+};
+static const unsigned int msiof1_txd_mux[] = {
+ MSIOF1_TXD_MARK,
+};
+static const unsigned int msiof1_rxd_pins[] = {
+ /* MSIOF1_RXD */
+ RCAR_GP_PIN(3, 0),
+};
+static const unsigned int msiof1_rxd_mux[] = {
+ MSIOF1_RXD_MARK,
+};
+
+/* - MSIOF2 ----------------------------------------------------------------- */
+static const unsigned int msiof2_clk_pins[] = {
+ /* MSIOF2_SCK */
+ RCAR_GP_PIN(2, 0),
+};
+static const unsigned int msiof2_clk_mux[] = {
+ MSIOF2_SCK_MARK,
+};
+static const unsigned int msiof2_sync_pins[] = {
+ /* MSIOF2_SYNC */
+ RCAR_GP_PIN(2, 3),
+};
+static const unsigned int msiof2_sync_mux[] = {
+ MSIOF2_SYNC_MARK,
+};
+static const unsigned int msiof2_ss1_pins[] = {
+ /* MSIOF2_SS1 */
+ RCAR_GP_PIN(2, 4),
+};
+static const unsigned int msiof2_ss1_mux[] = {
+ MSIOF2_SS1_MARK,
+};
+static const unsigned int msiof2_ss2_pins[] = {
+ /* MSIOF2_SS2 */
+ RCAR_GP_PIN(2, 5),
+};
+static const unsigned int msiof2_ss2_mux[] = {
+ MSIOF2_SS2_MARK,
+};
+static const unsigned int msiof2_txd_pins[] = {
+ /* MSIOF2_TXD */
+ RCAR_GP_PIN(2, 2),
+};
+static const unsigned int msiof2_txd_mux[] = {
+ MSIOF2_TXD_MARK,
+};
+static const unsigned int msiof2_rxd_pins[] = {
+ /* MSIOF2_RXD */
+ RCAR_GP_PIN(2, 1),
+};
+static const unsigned int msiof2_rxd_mux[] = {
+ MSIOF2_RXD_MARK,
+};
+
+/* - MSIOF3 ----------------------------------------------------------------- */
+static const unsigned int msiof3_clk_pins[] = {
+ /* MSIOF3_SCK */
+ RCAR_GP_PIN(0, 20),
+};
+static const unsigned int msiof3_clk_mux[] = {
+ MSIOF3_SCK_MARK,
+};
+static const unsigned int msiof3_sync_pins[] = {
+ /* MSIOF3_SYNC */
+ RCAR_GP_PIN(0, 21),
+};
+static const unsigned int msiof3_sync_mux[] = {
+ MSIOF3_SYNC_MARK,
+};
+static const unsigned int msiof3_ss1_pins[] = {
+ /* MSIOF3_SS1 */
+ RCAR_GP_PIN(0, 18),
+};
+static const unsigned int msiof3_ss1_mux[] = {
+ MSIOF3_SS1_MARK,
+};
+static const unsigned int msiof3_ss2_pins[] = {
+ /* MSIOF3_SS2 */
+ RCAR_GP_PIN(0, 19),
+};
+static const unsigned int msiof3_ss2_mux[] = {
+ MSIOF3_SS2_MARK,
+};
+static const unsigned int msiof3_txd_pins[] = {
+ /* MSIOF3_TXD */
+ RCAR_GP_PIN(0, 17),
+};
+static const unsigned int msiof3_txd_mux[] = {
+ MSIOF3_TXD_MARK,
+};
+static const unsigned int msiof3_rxd_pins[] = {
+ /* MSIOF3_RXD */
+ RCAR_GP_PIN(0, 16),
+};
+static const unsigned int msiof3_rxd_mux[] = {
+ MSIOF3_RXD_MARK,
+};
+
+/* - PWM0 ------------------------------------------------------------------- */
+static const unsigned int pwm0_a_pins[] = {
+ /* PWM0 */
+ RCAR_GP_PIN(0, 15),
+};
+static const unsigned int pwm0_a_mux[] = {
+ PWM0_A_MARK,
+};
+static const unsigned int pwm0_b_pins[] = {
+ /* PWM0 */
+ RCAR_GP_PIN(1, 21),
+};
+static const unsigned int pwm0_b_mux[] = {
+ PWM0_B_MARK,
+};
+
+/* - PWM1 ------------------------------------------------------------------- */
+static const unsigned int pwm1_a_pins[] = {
+ /* PWM1 */
+ RCAR_GP_PIN(2, 13),
+};
+static const unsigned int pwm1_a_mux[] = {
+ PWM1_A_MARK,
+};
+static const unsigned int pwm1_b_pins[] = {
+ /* PWM1 */
+ RCAR_GP_PIN(1, 22),
+};
+static const unsigned int pwm1_b_mux[] = {
+ PWM1_B_MARK,
+};
+
+/* - PWM2 ------------------------------------------------------------------- */
+static const unsigned int pwm2_a_pins[] = {
+ /* PWM2 */
+ RCAR_GP_PIN(2, 14),
+};
+static const unsigned int pwm2_a_mux[] = {
+ PWM2_A_MARK,
+};
+static const unsigned int pwm2_b_pins[] = {
+ /* PWM2 */
+ RCAR_GP_PIN(1, 23),
+};
+static const unsigned int pwm2_b_mux[] = {
+ PWM2_B_MARK,
+};
+
+/* - PWM3 ------------------------------------------------------------------- */
+static const unsigned int pwm3_a_pins[] = {
+ /* PWM3 */
+ RCAR_GP_PIN(2, 15),
+};
+static const unsigned int pwm3_a_mux[] = {
+ PWM3_A_MARK,
+};
+static const unsigned int pwm3_b_pins[] = {
+ /* PWM3 */
+ RCAR_GP_PIN(1, 24),
+};
+static const unsigned int pwm3_b_mux[] = {
+ PWM3_B_MARK,
+};
+
+/* - PWM4 ------------------------------------------------------------------- */
+static const unsigned int pwm4_a_pins[] = {
+ /* PWM4 */
+ RCAR_GP_PIN(2, 16),
+};
+static const unsigned int pwm4_a_mux[] = {
+ PWM4_A_MARK,
+};
+static const unsigned int pwm4_b_pins[] = {
+ /* PWM4 */
+ RCAR_GP_PIN(1, 25),
+};
+static const unsigned int pwm4_b_mux[] = {
+ PWM4_B_MARK,
+};
+
+/* - SCIF0 ------------------------------------------------------------------ */
+static const unsigned int scif0_data_pins[] = {
+ /* RX0, TX0 */
+ RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
+};
+static const unsigned int scif0_data_mux[] = {
+ RX0_MARK, TX0_MARK,
+};
+static const unsigned int scif0_clk_pins[] = {
+ /* SCK0 */
+ RCAR_GP_PIN(4, 1),
+};
+static const unsigned int scif0_clk_mux[] = {
+ SCK0_MARK,
+};
+static const unsigned int scif0_ctrl_pins[] = {
+ /* RTS0#/TANS, CTS0# */
+ RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
+};
+static const unsigned int scif0_ctrl_mux[] = {
+ RTS0_N_TANS_MARK, CTS0_N_MARK,
+};
+
+/* - SCIF1 ------------------------------------------------------------------ */
+static const unsigned int scif1_data_a_pins[] = {
+ /* RX1, TX1 */
+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+};
+static const unsigned int scif1_data_a_mux[] = {
+ RX1_A_MARK, TX1_A_MARK,
+};
+static const unsigned int scif1_clk_pins[] = {
+ /* SCK1 */
+ RCAR_GP_PIN(2, 5),
+};
+static const unsigned int scif1_clk_mux[] = {
+ SCK1_MARK,
+};
+static const unsigned int scif1_ctrl_pins[] = {
+ /* RTS1#/TANS, CTS1# */
+ RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
+};
+static const unsigned int scif1_ctrl_mux[] = {
+ RTS1_N_TANS_MARK, CTS1_N_MARK,
+};
+static const unsigned int scif1_data_b_pins[] = {
+ /* RX1, TX1 */
+ RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
+};
+static const unsigned int scif1_data_b_mux[] = {
+ RX1_B_MARK, TX1_B_MARK,
+};
+
+/* - SCIF3 ------------------------------------------------------------------ */
+static const unsigned int scif3_data_pins[] = {
+ /* RX3, TX3 */
+ RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+};
+static const unsigned int scif3_data_mux[] = {
+ RX3_MARK, TX3_MARK,
+};
+static const unsigned int scif3_clk_pins[] = {
+ /* SCK3 */
+ RCAR_GP_PIN(2, 0),
+};
+static const unsigned int scif3_clk_mux[] = {
+ SCK3_MARK,
+};
+static const unsigned int scif3_ctrl_pins[] = {
+ /* RTS3#/TANS, CTS3# */
+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
+};
+static const unsigned int scif3_ctrl_mux[] = {
+ RTS3_N_TANS_MARK, CTS3_N_MARK,
+};
+
+/* - SCIF4 ------------------------------------------------------------------ */
+static const unsigned int scif4_data_pins[] = {
+ /* RX4, TX4 */
+ RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
+};
+static const unsigned int scif4_data_mux[] = {
+ RX4_MARK, TX4_MARK,
+};
+static const unsigned int scif4_clk_pins[] = {
+ /* SCK4 */
+ RCAR_GP_PIN(0, 0),
+};
+static const unsigned int scif4_clk_mux[] = {
+ SCK4_MARK,
+};
+static const unsigned int scif4_ctrl_pins[] = {
+ /* RTS4#/TANS, CTS4# */
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
+};
+static const unsigned int scif4_ctrl_mux[] = {
+ RTS4_N_TANS_MARK, CTS4_N_MARK,
+};
+
+/* - SCIF Clock ------------------------------------------------------------- */
+static const unsigned int scif_clk_a_pins[] = {
+ /* SCIF_CLK */
+ RCAR_GP_PIN(0, 10),
+};
+static const unsigned int scif_clk_a_mux[] = {
+ SCIF_CLK_A_MARK,
+};
+static const unsigned int scif_clk_b_pins[] = {
+ /* SCIF_CLK */
+ RCAR_GP_PIN(1, 25),
+};
+static const unsigned int scif_clk_b_mux[] = {
+ SCIF_CLK_B_MARK,
+};
+
+/* - TMU -------------------------------------------------------------------- */
+static const unsigned int tmu_tclk1_a_pins[] = {
+ /* TCLK1 */
+ RCAR_GP_PIN(3, 13),
+};
+static const unsigned int tmu_tclk1_a_mux[] = {
+ TCLK1_A_MARK,
+};
+static const unsigned int tmu_tclk1_b_pins[] = {
+ /* TCLK1 */
+ RCAR_GP_PIN(1, 23),
+};
+static const unsigned int tmu_tclk1_b_mux[] = {
+ TCLK1_B_MARK,
+};
+static const unsigned int tmu_tclk2_a_pins[] = {
+ /* TCLK2 */
+ RCAR_GP_PIN(3, 14),
+};
+static const unsigned int tmu_tclk2_a_mux[] = {
+ TCLK2_A_MARK,
+};
+static const unsigned int tmu_tclk2_b_pins[] = {
+ /* TCLK2 */
+ RCAR_GP_PIN(1, 24),
+};
+static const unsigned int tmu_tclk2_b_mux[] = {
+ TCLK2_B_MARK,
+};
+
+/* - TPU ------------------------------------------------------------------- */
+static const unsigned int tpu_to0_pins[] = {
+ /* TPU0TO0 */
+ RCAR_GP_PIN(1, 19),
+};
+static const unsigned int tpu_to0_mux[] = {
+ TPU0TO0_MARK,
+};
+static const unsigned int tpu_to1_pins[] = {
+ /* TPU0TO1 */
+ RCAR_GP_PIN(1, 20),
+};
+static const unsigned int tpu_to1_mux[] = {
+ TPU0TO1_MARK,
+};
+static const unsigned int tpu_to2_pins[] = {
+ /* TPU0TO2 */
+ RCAR_GP_PIN(4, 2),
+};
+static const unsigned int tpu_to2_mux[] = {
+ TPU0TO2_MARK,
+};
+static const unsigned int tpu_to3_pins[] = {
+ /* TPU0TO3 */
+ RCAR_GP_PIN(4, 3),
+};
+static const unsigned int tpu_to3_mux[] = {
+ TPU0TO3_MARK,
+};
+
+/* - VIN0 ------------------------------------------------------------------- */
+static const union vin_data vin0_data_pins = {
+ .data24 = {
+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+ RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+ RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
+ RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
+ RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
+ RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
+ RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
+ RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
+ RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
+ RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
+ },
+};
+static const union vin_data vin0_data_mux = {
+ .data24 = {
+ VI0_DATA0_MARK, VI0_DATA1_MARK,
+ VI0_DATA2_MARK, VI0_DATA3_MARK,
+ VI0_DATA4_MARK, VI0_DATA5_MARK,
+ VI0_DATA6_MARK, VI0_DATA7_MARK,
+ VI0_DATA8_MARK, VI0_DATA9_MARK,
+ VI0_DATA10_MARK, VI0_DATA11_MARK,
+ VI0_DATA12_MARK, VI0_DATA13_MARK,
+ VI0_DATA14_MARK, VI0_DATA15_MARK,
+ VI0_DATA16_MARK, VI0_DATA17_MARK,
+ VI0_DATA18_MARK, VI0_DATA19_MARK,
+ VI0_DATA20_MARK, VI0_DATA21_MARK,
+ VI0_DATA22_MARK, VI0_DATA23_MARK,
+ },
+};
+static const unsigned int vin0_data18_pins[] = {
+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+ RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+ RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
+ RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
+ RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
+ RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
+ RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
+ RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
+};
+static const unsigned int vin0_data18_mux[] = {
+ VI0_DATA2_MARK, VI0_DATA3_MARK,
+ VI0_DATA4_MARK, VI0_DATA5_MARK,
+ VI0_DATA6_MARK, VI0_DATA7_MARK,
+ VI0_DATA10_MARK, VI0_DATA11_MARK,
+ VI0_DATA12_MARK, VI0_DATA13_MARK,
+ VI0_DATA14_MARK, VI0_DATA15_MARK,
+ VI0_DATA18_MARK, VI0_DATA19_MARK,
+ VI0_DATA20_MARK, VI0_DATA21_MARK,
+ VI0_DATA22_MARK, VI0_DATA23_MARK,
+};
+static const unsigned int vin0_sync_pins[] = {
+ /* VI0_VSYNC#, VI0_HSYNC# */
+ RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
+};
+static const unsigned int vin0_sync_mux[] = {
+ VI0_VSYNC_N_MARK, VI0_HSYNC_N_MARK,
+};
+static const unsigned int vin0_field_pins[] = {
+ /* VI0_FIELD */
+ RCAR_GP_PIN(2, 16),
+};
+static const unsigned int vin0_field_mux[] = {
+ VI0_FIELD_MARK,
+};
+static const unsigned int vin0_clkenb_pins[] = {
+ /* VI0_CLKENB */
+ RCAR_GP_PIN(2, 1),
+};
+static const unsigned int vin0_clkenb_mux[] = {
+ VI0_CLKENB_MARK,
+};
+static const unsigned int vin0_clk_pins[] = {
+ /* VI0_CLK */
+ RCAR_GP_PIN(2, 0),
+};
+static const unsigned int vin0_clk_mux[] = {
+ VI0_CLK_MARK,
+};
+
+/* - VIN1 ------------------------------------------------------------------- */
+static const unsigned int vin1_data8_pins[] = {
+ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+};
+static const unsigned int vin1_data8_mux[] = {
+ VI1_DATA0_MARK, VI1_DATA1_MARK,
+ VI1_DATA2_MARK, VI1_DATA3_MARK,
+ VI1_DATA4_MARK, VI1_DATA5_MARK,
+ VI1_DATA6_MARK, VI1_DATA7_MARK,
+};
+static const unsigned int vin1_data10_pins[] = {
+ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+ RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
+};
+static const unsigned int vin1_data10_mux[] = {
+ VI1_DATA0_MARK, VI1_DATA1_MARK,
+ VI1_DATA2_MARK, VI1_DATA3_MARK,
+ VI1_DATA4_MARK, VI1_DATA5_MARK,
+ VI1_DATA6_MARK, VI1_DATA7_MARK,
+ VI1_DATA8_MARK, VI1_DATA9_MARK,
+};
+static const unsigned int vin1_data12_pins[] = {
+ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+ RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
+ RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
+};
+static const unsigned int vin1_data12_mux[] = {
+ VI1_DATA0_MARK, VI1_DATA1_MARK,
+ VI1_DATA2_MARK, VI1_DATA3_MARK,
+ VI1_DATA4_MARK, VI1_DATA5_MARK,
+ VI1_DATA6_MARK, VI1_DATA7_MARK,
+ VI1_DATA8_MARK, VI1_DATA9_MARK,
+ VI1_DATA10_MARK, VI1_DATA11_MARK,
+};
+static const unsigned int vin1_sync_pins[] = {
+ /* VI1_VSYNC#, VI1_HSYNC# */
+ RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
+};
+static const unsigned int vin1_sync_mux[] = {
+ VI1_VSYNC_N_MARK, VI1_HSYNC_N_MARK,
+};
+static const unsigned int vin1_field_pins[] = {
+ /* VI1_FIELD */
+ RCAR_GP_PIN(3, 16),
+};
+static const unsigned int vin1_field_mux[] = {
+ VI1_FIELD_MARK,
+};
+static const unsigned int vin1_clkenb_pins[] = {
+ /* VI1_CLKENB */
+ RCAR_GP_PIN(3, 1),
+};
+static const unsigned int vin1_clkenb_mux[] = {
+ VI1_CLKENB_MARK,
+};
+static const unsigned int vin1_clk_pins[] = {
+ /* VI1_CLK */
+ RCAR_GP_PIN(3, 0),
+};
+static const unsigned int vin1_clk_mux[] = {
+ VI1_CLK_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(avb_link),
+ SH_PFC_PIN_GROUP(avb_magic),
+ SH_PFC_PIN_GROUP(avb_phy_int),
+ SH_PFC_PIN_GROUP(avb_mdio),
+ SH_PFC_PIN_GROUP(avb_rgmii),
+ SH_PFC_PIN_GROUP(avb_txcrefclk),
+ SH_PFC_PIN_GROUP(avb_avtp_pps),
+ SH_PFC_PIN_GROUP(avb_avtp_capture),
+ SH_PFC_PIN_GROUP(avb_avtp_match),
+ SH_PFC_PIN_GROUP(canfd0_data_a),
+ SH_PFC_PIN_GROUP(canfd0_data_b),
+ SH_PFC_PIN_GROUP(canfd1_data),
+ SH_PFC_PIN_GROUP(canfd_clk_a),
+ SH_PFC_PIN_GROUP(canfd_clk_b),
+ SH_PFC_PIN_GROUP(du_rgb666),
+ SH_PFC_PIN_GROUP(du_rgb888),
+ SH_PFC_PIN_GROUP(du_clk_out),
+ SH_PFC_PIN_GROUP(du_sync),
+ SH_PFC_PIN_GROUP(du_oddf),
+ SH_PFC_PIN_GROUP(du_cde),
+ SH_PFC_PIN_GROUP(du_disp),
+ SH_PFC_PIN_GROUP(gether_link_a),
+ SH_PFC_PIN_GROUP(gether_phy_int_a),
+ SH_PFC_PIN_GROUP(gether_mdio_a),
+ SH_PFC_PIN_GROUP(gether_link_b),
+ SH_PFC_PIN_GROUP(gether_phy_int_b),
+ SH_PFC_PIN_GROUP(gether_mdio_b),
+ SH_PFC_PIN_GROUP(gether_magic),
+ SH_PFC_PIN_GROUP(gether_rgmii),
+ SH_PFC_PIN_GROUP(gether_txcrefclk),
+ SH_PFC_PIN_GROUP(gether_txcrefclk_mega),
+ SH_PFC_PIN_GROUP(gether_rmii),
+ SH_PFC_PIN_GROUP(hscif0_data_a),
+ SH_PFC_PIN_GROUP(hscif0_clk_a),
+ SH_PFC_PIN_GROUP(hscif0_ctrl_a),
+ SH_PFC_PIN_GROUP(hscif0_data_b),
+ SH_PFC_PIN_GROUP(hscif0_clk_b),
+ SH_PFC_PIN_GROUP(hscif0_ctrl_b),
+ SH_PFC_PIN_GROUP(hscif1_data),
+ SH_PFC_PIN_GROUP(hscif1_clk),
+ SH_PFC_PIN_GROUP(hscif1_ctrl),
+ SH_PFC_PIN_GROUP(hscif2_data),
+ SH_PFC_PIN_GROUP(hscif2_clk),
+ SH_PFC_PIN_GROUP(hscif2_ctrl),
+ SH_PFC_PIN_GROUP(hscif3_data),
+ SH_PFC_PIN_GROUP(hscif3_clk),
+ SH_PFC_PIN_GROUP(hscif3_ctrl),
+ SH_PFC_PIN_GROUP(i2c0),
+ SH_PFC_PIN_GROUP(i2c1),
+ SH_PFC_PIN_GROUP(i2c2),
+ SH_PFC_PIN_GROUP(i2c3),
+ SH_PFC_PIN_GROUP(i2c4),
+ SH_PFC_PIN_GROUP(i2c5),
+ SH_PFC_PIN_GROUP(intc_ex_irq0),
+ SH_PFC_PIN_GROUP(intc_ex_irq1),
+ SH_PFC_PIN_GROUP(intc_ex_irq2),
+ SH_PFC_PIN_GROUP(intc_ex_irq3),
+ SH_PFC_PIN_GROUP(intc_ex_irq4),
+ SH_PFC_PIN_GROUP(intc_ex_irq5),
+ SH_PFC_PIN_GROUP(mmc_data1),
+ SH_PFC_PIN_GROUP(mmc_data4),
+ SH_PFC_PIN_GROUP(mmc_data8),
+ SH_PFC_PIN_GROUP(mmc_ctrl),
+ SH_PFC_PIN_GROUP(mmc_cd),
+ SH_PFC_PIN_GROUP(mmc_wp),
+ SH_PFC_PIN_GROUP(mmc_ds),
+ SH_PFC_PIN_GROUP(msiof0_clk),
+ SH_PFC_PIN_GROUP(msiof0_sync),
+ SH_PFC_PIN_GROUP(msiof0_ss1),
+ SH_PFC_PIN_GROUP(msiof0_ss2),
+ SH_PFC_PIN_GROUP(msiof0_txd),
+ SH_PFC_PIN_GROUP(msiof0_rxd),
+ SH_PFC_PIN_GROUP(msiof1_clk),
+ SH_PFC_PIN_GROUP(msiof1_sync),
+ SH_PFC_PIN_GROUP(msiof1_ss1),
+ SH_PFC_PIN_GROUP(msiof1_ss2),
+ SH_PFC_PIN_GROUP(msiof1_txd),
+ SH_PFC_PIN_GROUP(msiof1_rxd),
+ SH_PFC_PIN_GROUP(msiof2_clk),
+ SH_PFC_PIN_GROUP(msiof2_sync),
+ SH_PFC_PIN_GROUP(msiof2_ss1),
+ SH_PFC_PIN_GROUP(msiof2_ss2),
+ SH_PFC_PIN_GROUP(msiof2_txd),
+ SH_PFC_PIN_GROUP(msiof2_rxd),
+ SH_PFC_PIN_GROUP(msiof3_clk),
+ SH_PFC_PIN_GROUP(msiof3_sync),
+ SH_PFC_PIN_GROUP(msiof3_ss1),
+ SH_PFC_PIN_GROUP(msiof3_ss2),
+ SH_PFC_PIN_GROUP(msiof3_txd),
+ SH_PFC_PIN_GROUP(msiof3_rxd),
+ SH_PFC_PIN_GROUP(pwm0_a),
+ SH_PFC_PIN_GROUP(pwm0_b),
+ SH_PFC_PIN_GROUP(pwm1_a),
+ SH_PFC_PIN_GROUP(pwm1_b),
+ SH_PFC_PIN_GROUP(pwm2_a),
+ SH_PFC_PIN_GROUP(pwm2_b),
+ SH_PFC_PIN_GROUP(pwm3_a),
+ SH_PFC_PIN_GROUP(pwm3_b),
+ SH_PFC_PIN_GROUP(pwm4_a),
+ SH_PFC_PIN_GROUP(pwm4_b),
+ SH_PFC_PIN_GROUP(scif0_data),
+ SH_PFC_PIN_GROUP(scif0_clk),
+ SH_PFC_PIN_GROUP(scif0_ctrl),
+ SH_PFC_PIN_GROUP(scif1_data_a),
+ SH_PFC_PIN_GROUP(scif1_clk),
+ SH_PFC_PIN_GROUP(scif1_ctrl),
+ SH_PFC_PIN_GROUP(scif1_data_b),
+ SH_PFC_PIN_GROUP(scif3_data),
+ SH_PFC_PIN_GROUP(scif3_clk),
+ SH_PFC_PIN_GROUP(scif3_ctrl),
+ SH_PFC_PIN_GROUP(scif4_data),
+ SH_PFC_PIN_GROUP(scif4_clk),
+ SH_PFC_PIN_GROUP(scif4_ctrl),
+ SH_PFC_PIN_GROUP(scif_clk_a),
+ SH_PFC_PIN_GROUP(scif_clk_b),
+ SH_PFC_PIN_GROUP(tmu_tclk1_a),
+ SH_PFC_PIN_GROUP(tmu_tclk1_b),
+ SH_PFC_PIN_GROUP(tmu_tclk2_a),
+ SH_PFC_PIN_GROUP(tmu_tclk2_b),
+ SH_PFC_PIN_GROUP(tpu_to0),
+ SH_PFC_PIN_GROUP(tpu_to1),
+ SH_PFC_PIN_GROUP(tpu_to2),
+ SH_PFC_PIN_GROUP(tpu_to3),
+ VIN_DATA_PIN_GROUP(vin0_data, 8),
+ VIN_DATA_PIN_GROUP(vin0_data, 10),
+ VIN_DATA_PIN_GROUP(vin0_data, 12),
+ VIN_DATA_PIN_GROUP(vin0_data, 16),
+ SH_PFC_PIN_GROUP(vin0_data18),
+ VIN_DATA_PIN_GROUP(vin0_data, 20),
+ VIN_DATA_PIN_GROUP(vin0_data, 24),
+ SH_PFC_PIN_GROUP(vin0_sync),
+ SH_PFC_PIN_GROUP(vin0_field),
+ SH_PFC_PIN_GROUP(vin0_clkenb),
+ SH_PFC_PIN_GROUP(vin0_clk),
+ SH_PFC_PIN_GROUP(vin1_data8),
+ SH_PFC_PIN_GROUP(vin1_data10),
+ SH_PFC_PIN_GROUP(vin1_data12),
+ SH_PFC_PIN_GROUP(vin1_sync),
+ SH_PFC_PIN_GROUP(vin1_field),
+ SH_PFC_PIN_GROUP(vin1_clkenb),
+ SH_PFC_PIN_GROUP(vin1_clk),
+};
+
+static const char * const avb_groups[] = {
+ "avb_link",
+ "avb_magic",
+ "avb_phy_int",
+ "avb_mdio",
+ "avb_rgmii",
+ "avb_txcrefclk",
+ "avb_avtp_pps",
+ "avb_avtp_capture",
+ "avb_avtp_match",
+};
+
+static const char * const canfd0_groups[] = {
+ "canfd0_data_a",
+ "canfd0_data_b",
+};
+
+static const char * const canfd1_groups[] = {
+ "canfd1_data",
+};
+
+static const char * const canfd_clk_groups[] = {
+ "canfd_clk_a",
+ "canfd_clk_b",
+};
+
+static const char * const du_groups[] = {
+ "du_rgb666",
+ "du_rgb888",
+ "du_clk_out",
+ "du_sync",
+ "du_oddf",
+ "du_cde",
+ "du_disp",
+};
+
+static const char * const gether_groups[] = {
+ "gether_link_a",
+ "gether_phy_int_a",
+ "gether_mdio_a",
+ "gether_link_b",
+ "gether_phy_int_b",
+ "gether_mdio_b",
+ "gether_magic",
+ "gether_rgmii",
+ "gether_txcrefclk",
+ "gether_txcrefclk_mega",
+ "gether_rmii",
+};
+
+static const char * const hscif0_groups[] = {
+ "hscif0_data_a",
+ "hscif0_clk_a",
+ "hscif0_ctrl_a",
+ "hscif0_data_b",
+ "hscif0_clk_b",
+ "hscif0_ctrl_b",
+};
+
+static const char * const hscif1_groups[] = {
+ "hscif1_data",
+ "hscif1_clk",
+ "hscif1_ctrl",
+};
+
+static const char * const hscif2_groups[] = {
+ "hscif2_data",
+ "hscif2_clk",
+ "hscif2_ctrl",
+};
+
+static const char * const hscif3_groups[] = {
+ "hscif3_data",
+ "hscif3_clk",
+ "hscif3_ctrl",
+};
+
+static const char * const i2c0_groups[] = {
+ "i2c0",
+};
+
+static const char * const i2c1_groups[] = {
+ "i2c1",
+};
+
+static const char * const i2c2_groups[] = {
+ "i2c2",
+};
+
+static const char * const i2c3_groups[] = {
+ "i2c3",
+};
+
+static const char * const i2c4_groups[] = {
+ "i2c4",
+};
+
+static const char * const i2c5_groups[] = {
+ "i2c5",
+};
+
+static const char * const intc_ex_groups[] = {
+ "intc_ex_irq0",
+ "intc_ex_irq1",
+ "intc_ex_irq2",
+ "intc_ex_irq3",
+ "intc_ex_irq4",
+ "intc_ex_irq5",
+};
+
+static const char * const mmc_groups[] = {
+ "mmc_data1",
+ "mmc_data4",
+ "mmc_data8",
+ "mmc_ctrl",
+ "mmc_cd",
+ "mmc_wp",
+ "mmc_ds",
+};
+
+static const char * const msiof0_groups[] = {
+ "msiof0_clk",
+ "msiof0_sync",
+ "msiof0_ss1",
+ "msiof0_ss2",
+ "msiof0_txd",
+ "msiof0_rxd",
+};
+
+static const char * const msiof1_groups[] = {
+ "msiof1_clk",
+ "msiof1_sync",
+ "msiof1_ss1",
+ "msiof1_ss2",
+ "msiof1_txd",
+ "msiof1_rxd",
+};
+
+static const char * const msiof2_groups[] = {
+ "msiof2_clk",
+ "msiof2_sync",
+ "msiof2_ss1",
+ "msiof2_ss2",
+ "msiof2_txd",
+ "msiof2_rxd",
+};
+
+static const char * const msiof3_groups[] = {
+ "msiof3_clk",
+ "msiof3_sync",
+ "msiof3_ss1",
+ "msiof3_ss2",
+ "msiof3_txd",
+ "msiof3_rxd",
+};
+
+static const char * const pwm0_groups[] = {
+ "pwm0_a",
+ "pwm0_b",
+};
+
+static const char * const pwm1_groups[] = {
+ "pwm1_a",
+ "pwm1_b",
+};
+
+static const char * const pwm2_groups[] = {
+ "pwm2_a",
+ "pwm2_b",
+};
+
+static const char * const pwm3_groups[] = {
+ "pwm3_a",
+ "pwm3_b",
+};
+
+static const char * const pwm4_groups[] = {
+ "pwm4_a",
+ "pwm4_b",
+};
+
+static const char * const scif0_groups[] = {
+ "scif0_data",
+ "scif0_clk",
+ "scif0_ctrl",
+};
+
+static const char * const scif1_groups[] = {
+ "scif1_data_a",
+ "scif1_clk",
+ "scif1_ctrl",
+ "scif1_data_b",
+};
+
+static const char * const scif3_groups[] = {
+ "scif3_data",
+ "scif3_clk",
+ "scif3_ctrl",
+};
+
+static const char * const scif4_groups[] = {
+ "scif4_data",
+ "scif4_clk",
+ "scif4_ctrl",
+};
+
+static const char * const scif_clk_groups[] = {
+ "scif_clk_a",
+ "scif_clk_b",
+};
+
+static const char * const tmu_groups[] = {
+ "tmu_tclk1_a",
+ "tmu_tclk1_b",
+ "tmu_tclk2_a",
+ "tmu_tclk2_b",
+};
+
+static const char * const tpu_groups[] = {
+ "tpu_to0",
+ "tpu_to1",
+ "tpu_to2",
+ "tpu_to3",
+};
+
+static const char * const vin0_groups[] = {
+ "vin0_data8",
+ "vin0_data10",
+ "vin0_data12",
+ "vin0_data16",
+ "vin0_data18",
+ "vin0_data20",
+ "vin0_data24",
+ "vin0_sync",
+ "vin0_field",
+ "vin0_clkenb",
+ "vin0_clk",
+};
+
+static const char * const vin1_groups[] = {
+ "vin1_data8",
+ "vin1_data10",
+ "vin1_data12",
+ "vin1_sync",
+ "vin1_field",
+ "vin1_clkenb",
+ "vin1_clk",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(avb),
+ SH_PFC_FUNCTION(canfd0),
+ SH_PFC_FUNCTION(canfd1),
+ SH_PFC_FUNCTION(canfd_clk),
+ SH_PFC_FUNCTION(du),
+ SH_PFC_FUNCTION(gether),
+ SH_PFC_FUNCTION(hscif0),
+ SH_PFC_FUNCTION(hscif1),
+ SH_PFC_FUNCTION(hscif2),
+ SH_PFC_FUNCTION(hscif3),
+ SH_PFC_FUNCTION(i2c0),
+ SH_PFC_FUNCTION(i2c1),
+ SH_PFC_FUNCTION(i2c2),
+ SH_PFC_FUNCTION(i2c3),
+ SH_PFC_FUNCTION(i2c4),
+ SH_PFC_FUNCTION(i2c5),
+ SH_PFC_FUNCTION(intc_ex),
+ SH_PFC_FUNCTION(mmc),
+ SH_PFC_FUNCTION(msiof0),
+ SH_PFC_FUNCTION(msiof1),
+ SH_PFC_FUNCTION(msiof2),
+ SH_PFC_FUNCTION(msiof3),
+ SH_PFC_FUNCTION(pwm0),
+ SH_PFC_FUNCTION(pwm1),
+ SH_PFC_FUNCTION(pwm2),
+ SH_PFC_FUNCTION(pwm3),
+ SH_PFC_FUNCTION(pwm4),
+ SH_PFC_FUNCTION(scif0),
+ SH_PFC_FUNCTION(scif1),
+ SH_PFC_FUNCTION(scif3),
+ SH_PFC_FUNCTION(scif4),
+ SH_PFC_FUNCTION(scif_clk),
+ SH_PFC_FUNCTION(tmu),
+ SH_PFC_FUNCTION(tpu),
+ SH_PFC_FUNCTION(vin0),
+ SH_PFC_FUNCTION(vin1),
+};
+
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+#define F_(x, y) FN_##y
+#define FM(x) FN_##x
+ { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_0_21_FN, GPSR0_21,
+ GP_0_20_FN, GPSR0_20,
+ GP_0_19_FN, GPSR0_19,
+ GP_0_18_FN, GPSR0_18,
+ GP_0_17_FN, GPSR0_17,
+ GP_0_16_FN, GPSR0_16,
+ GP_0_15_FN, GPSR0_15,
+ GP_0_14_FN, GPSR0_14,
+ GP_0_13_FN, GPSR0_13,
+ GP_0_12_FN, GPSR0_12,
+ GP_0_11_FN, GPSR0_11,
+ GP_0_10_FN, GPSR0_10,
+ GP_0_9_FN, GPSR0_9,
+ GP_0_8_FN, GPSR0_8,
+ GP_0_7_FN, GPSR0_7,
+ GP_0_6_FN, GPSR0_6,
+ GP_0_5_FN, GPSR0_5,
+ GP_0_4_FN, GPSR0_4,
+ GP_0_3_FN, GPSR0_3,
+ GP_0_2_FN, GPSR0_2,
+ GP_0_1_FN, GPSR0_1,
+ GP_0_0_FN, GPSR0_0, }
+ },
+ { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_1_27_FN, GPSR1_27,
+ GP_1_26_FN, GPSR1_26,
+ GP_1_25_FN, GPSR1_25,
+ GP_1_24_FN, GPSR1_24,
+ GP_1_23_FN, GPSR1_23,
+ GP_1_22_FN, GPSR1_22,
+ GP_1_21_FN, GPSR1_21,
+ GP_1_20_FN, GPSR1_20,
+ GP_1_19_FN, GPSR1_19,
+ GP_1_18_FN, GPSR1_18,
+ GP_1_17_FN, GPSR1_17,
+ GP_1_16_FN, GPSR1_16,
+ GP_1_15_FN, GPSR1_15,
+ GP_1_14_FN, GPSR1_14,
+ GP_1_13_FN, GPSR1_13,
+ GP_1_12_FN, GPSR1_12,
+ GP_1_11_FN, GPSR1_11,
+ GP_1_10_FN, GPSR1_10,
+ GP_1_9_FN, GPSR1_9,
+ GP_1_8_FN, GPSR1_8,
+ GP_1_7_FN, GPSR1_7,
+ GP_1_6_FN, GPSR1_6,
+ GP_1_5_FN, GPSR1_5,
+ GP_1_4_FN, GPSR1_4,
+ GP_1_3_FN, GPSR1_3,
+ GP_1_2_FN, GPSR1_2,
+ GP_1_1_FN, GPSR1_1,
+ GP_1_0_FN, GPSR1_0, }
+ },
+ { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
+ 0, 0,
+ 0, 0,
+ GP_2_29_FN, GPSR2_29,
+ GP_2_28_FN, GPSR2_28,
+ GP_2_27_FN, GPSR2_27,
+ GP_2_26_FN, GPSR2_26,
+ GP_2_25_FN, GPSR2_25,
+ GP_2_24_FN, GPSR2_24,
+ GP_2_23_FN, GPSR2_23,
+ GP_2_22_FN, GPSR2_22,
+ GP_2_21_FN, GPSR2_21,
+ GP_2_20_FN, GPSR2_20,
+ GP_2_19_FN, GPSR2_19,
+ GP_2_18_FN, GPSR2_18,
+ GP_2_17_FN, GPSR2_17,
+ GP_2_16_FN, GPSR2_16,
+ GP_2_15_FN, GPSR2_15,
+ GP_2_14_FN, GPSR2_14,
+ GP_2_13_FN, GPSR2_13,
+ GP_2_12_FN, GPSR2_12,
+ GP_2_11_FN, GPSR2_11,
+ GP_2_10_FN, GPSR2_10,
+ GP_2_9_FN, GPSR2_9,
+ GP_2_8_FN, GPSR2_8,
+ GP_2_7_FN, GPSR2_7,
+ GP_2_6_FN, GPSR2_6,
+ GP_2_5_FN, GPSR2_5,
+ GP_2_4_FN, GPSR2_4,
+ GP_2_3_FN, GPSR2_3,
+ GP_2_2_FN, GPSR2_2,
+ GP_2_1_FN, GPSR2_1,
+ GP_2_0_FN, GPSR2_0, }
+ },
+ { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_3_16_FN, GPSR3_16,
+ GP_3_15_FN, GPSR3_15,
+ GP_3_14_FN, GPSR3_14,
+ GP_3_13_FN, GPSR3_13,
+ GP_3_12_FN, GPSR3_12,
+ GP_3_11_FN, GPSR3_11,
+ GP_3_10_FN, GPSR3_10,
+ GP_3_9_FN, GPSR3_9,
+ GP_3_8_FN, GPSR3_8,
+ GP_3_7_FN, GPSR3_7,
+ GP_3_6_FN, GPSR3_6,
+ GP_3_5_FN, GPSR3_5,
+ GP_3_4_FN, GPSR3_4,
+ GP_3_3_FN, GPSR3_3,
+ GP_3_2_FN, GPSR3_2,
+ GP_3_1_FN, GPSR3_1,
+ GP_3_0_FN, GPSR3_0, }
+ },
+ { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_4_24_FN, GPSR4_24,
+ GP_4_23_FN, GPSR4_23,
+ GP_4_22_FN, GPSR4_22,
+ GP_4_21_FN, GPSR4_21,
+ GP_4_20_FN, GPSR4_20,
+ GP_4_19_FN, GPSR4_19,
+ GP_4_18_FN, GPSR4_18,
+ GP_4_17_FN, GPSR4_17,
+ GP_4_16_FN, GPSR4_16,
+ GP_4_15_FN, GPSR4_15,
+ GP_4_14_FN, GPSR4_14,
+ GP_4_13_FN, GPSR4_13,
+ GP_4_12_FN, GPSR4_12,
+ GP_4_11_FN, GPSR4_11,
+ GP_4_10_FN, GPSR4_10,
+ GP_4_9_FN, GPSR4_9,
+ GP_4_8_FN, GPSR4_8,
+ GP_4_7_FN, GPSR4_7,
+ GP_4_6_FN, GPSR4_6,
+ GP_4_5_FN, GPSR4_5,
+ GP_4_4_FN, GPSR4_4,
+ GP_4_3_FN, GPSR4_3,
+ GP_4_2_FN, GPSR4_2,
+ GP_4_1_FN, GPSR4_1,
+ GP_4_0_FN, GPSR4_0, }
+ },
+ { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_5_14_FN, GPSR5_14,
+ GP_5_13_FN, GPSR5_13,
+ GP_5_12_FN, GPSR5_12,
+ GP_5_11_FN, GPSR5_11,
+ GP_5_10_FN, GPSR5_10,
+ GP_5_9_FN, GPSR5_9,
+ GP_5_8_FN, GPSR5_8,
+ GP_5_7_FN, GPSR5_7,
+ GP_5_6_FN, GPSR5_6,
+ GP_5_5_FN, GPSR5_5,
+ GP_5_4_FN, GPSR5_4,
+ GP_5_3_FN, GPSR5_3,
+ GP_5_2_FN, GPSR5_2,
+ GP_5_1_FN, GPSR5_1,
+ GP_5_0_FN, GPSR5_0, }
+ },
+#undef F_
+#undef FM
+
+#define F_(x, y) x,
+#define FM(x) FN_##x,
+ { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
+ IP0_31_28
+ IP0_27_24
+ IP0_23_20
+ IP0_19_16
+ IP0_15_12
+ IP0_11_8
+ IP0_7_4
+ IP0_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
+ IP1_31_28
+ IP1_27_24
+ IP1_23_20
+ IP1_19_16
+ IP1_15_12
+ IP1_11_8
+ IP1_7_4
+ IP1_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
+ IP2_31_28
+ IP2_27_24
+ IP2_23_20
+ IP2_19_16
+ IP2_15_12
+ IP2_11_8
+ IP2_7_4
+ IP2_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
+ IP3_31_28
+ IP3_27_24
+ IP3_23_20
+ IP3_19_16
+ IP3_15_12
+ IP3_11_8
+ IP3_7_4
+ IP3_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
+ IP4_31_28
+ IP4_27_24
+ IP4_23_20
+ IP4_19_16
+ IP4_15_12
+ IP4_11_8
+ IP4_7_4
+ IP4_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
+ IP5_31_28
+ IP5_27_24
+ IP5_23_20
+ IP5_19_16
+ IP5_15_12
+ IP5_11_8
+ IP5_7_4
+ IP5_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
+ IP6_31_28
+ IP6_27_24
+ IP6_23_20
+ IP6_19_16
+ IP6_15_12
+ IP6_11_8
+ IP6_7_4
+ IP6_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
+ IP7_31_28
+ IP7_27_24
+ IP7_23_20
+ IP7_19_16
+ IP7_15_12
+ IP7_11_8
+ IP7_7_4
+ IP7_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
+ IP8_31_28
+ IP8_27_24
+ IP8_23_20
+ IP8_19_16
+ IP8_15_12
+ IP8_11_8
+ IP8_7_4
+ IP8_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
+ IP9_31_28
+ IP9_27_24
+ IP9_23_20
+ IP9_19_16
+ IP9_15_12
+ IP9_11_8
+ IP9_7_4
+ IP9_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
+ IP10_31_28
+ IP10_27_24
+ IP10_23_20
+ IP10_19_16
+ IP10_15_12
+ IP10_11_8
+ IP10_7_4
+ IP10_3_0 }
+ },
+#undef F_
+#undef FM
+
+#define F_(x, y) x,
+#define FM(x) FN_##x,
+ { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
+ 4, 4, 4, 4,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
+ /* RESERVED 31, 30, 29, 28 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 27, 26, 25, 24 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 23, 22, 21, 20 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 19, 18, 17, 16 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 15, 14, 13, 12 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ MOD_SEL0_11
+ MOD_SEL0_10
+ MOD_SEL0_9
+ MOD_SEL0_8
+ MOD_SEL0_7
+ MOD_SEL0_6
+ MOD_SEL0_5
+ MOD_SEL0_4
+ 0, 0,
+ MOD_SEL0_2
+ MOD_SEL0_1
+ MOD_SEL0_0 }
+ },
+ { },
+};
+
+const struct sh_pfc_soc_info r8a77980_pinmux_info = {
+ .name = "r8a77980_pfc",
+ .unlock_reg = 0xe6060000, /* PMMR */
+
+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups,
+ .nr_groups = ARRAY_SIZE(pinmux_groups),
+ .functions = pinmux_functions,
+ .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+ .cfg_regs = pinmux_config_regs,
+
+ .pinmux_data = pinmux_data,
+ .pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
index a4927b78a17b..adade5b7ffbc 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
@@ -988,11 +988,11 @@ static const unsigned int avb0_phy_int_pins[] = {
static const unsigned int avb0_phy_int_mux[] = {
AVB0_PHY_INT_MARK,
};
-static const unsigned int avb0_mdc_pins[] = {
+static const unsigned int avb0_mdio_pins[] = {
/* AVB0_MDC, AVB0_MDIO */
RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 16),
};
-static const unsigned int avb0_mdc_mux[] = {
+static const unsigned int avb0_mdio_mux[] = {
AVB0_MDC_MARK, AVB0_MDIO_MARK,
};
static const unsigned int avb0_mii_pins[] = {
@@ -1114,6 +1114,87 @@ static const unsigned int canfd1_data_mux[] = {
CANFD1_TX_MARK, CANFD1_RX_MARK,
};
+/* - DU --------------------------------------------------------------------- */
+static const unsigned int du_rgb666_pins[] = {
+ /* R[7:2], G[7:2], B[7:2] */
+ RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
+ RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
+ RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
+ RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
+ RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
+};
+static const unsigned int du_rgb666_mux[] = {
+ DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
+ DU_DR3_MARK, DU_DR2_MARK,
+ DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
+ DU_DG3_MARK, DU_DG2_MARK,
+ DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
+ DU_DB3_MARK, DU_DB2_MARK,
+};
+static const unsigned int du_rgb888_pins[] = {
+ /* R[7:0], G[7:0], B[7:0] */
+ RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
+ RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
+ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
+ RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
+ RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
+ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
+ RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
+ RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
+};
+static const unsigned int du_rgb888_mux[] = {
+ DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
+ DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
+ DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
+ DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
+ DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
+ DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
+};
+static const unsigned int du_clk_in_1_pins[] = {
+ /* CLKIN */
+ RCAR_GP_PIN(1, 28),
+};
+static const unsigned int du_clk_in_1_mux[] = {
+ DU_DOTCLKIN1_MARK
+};
+static const unsigned int du_clk_out_0_pins[] = {
+ /* CLKOUT */
+ RCAR_GP_PIN(1, 24),
+};
+static const unsigned int du_clk_out_0_mux[] = {
+ DU_DOTCLKOUT0_MARK
+};
+static const unsigned int du_sync_pins[] = {
+ /* VSYNC, HSYNC */
+ RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
+};
+static const unsigned int du_sync_mux[] = {
+ DU_VSYNC_MARK, DU_HSYNC_MARK
+};
+static const unsigned int du_disp_cde_pins[] = {
+ /* DISP_CDE */
+ RCAR_GP_PIN(1, 28),
+};
+static const unsigned int du_disp_cde_mux[] = {
+ DU_DISP_CDE_MARK,
+};
+static const unsigned int du_cde_pins[] = {
+ /* CDE */
+ RCAR_GP_PIN(1, 29),
+};
+static const unsigned int du_cde_mux[] = {
+ DU_CDE_MARK,
+};
+static const unsigned int du_disp_pins[] = {
+ /* DISP */
+ RCAR_GP_PIN(1, 27),
+};
+static const unsigned int du_disp_mux[] = {
+ DU_DISP_MARK,
+};
+
/* - I2C -------------------------------------------------------------------- */
static const unsigned int i2c0_pins[] = {
/* SCL, SDA */
@@ -1545,6 +1626,90 @@ static const unsigned int usb0_mux[] = {
USB0_PWEN_MARK, USB0_OVC_MARK,
};
+/* - VIN4 ------------------------------------------------------------------- */
+static const unsigned int vin4_data18_pins[] = {
+ RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
+ RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+ RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
+ RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
+ RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
+ RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
+ RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
+ RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
+};
+static const unsigned int vin4_data18_mux[] = {
+ VI4_DATA2_MARK, VI4_DATA3_MARK,
+ VI4_DATA4_MARK, VI4_DATA5_MARK,
+ VI4_DATA6_MARK, VI4_DATA7_MARK,
+ VI4_DATA10_MARK, VI4_DATA11_MARK,
+ VI4_DATA12_MARK, VI4_DATA13_MARK,
+ VI4_DATA14_MARK, VI4_DATA15_MARK,
+ VI4_DATA18_MARK, VI4_DATA19_MARK,
+ VI4_DATA20_MARK, VI4_DATA21_MARK,
+ VI4_DATA22_MARK, VI4_DATA23_MARK,
+};
+static const union vin_data vin4_data_pins = {
+ .data24 = {
+ RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+ RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
+ RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+ RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
+ RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
+ RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
+ RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
+ RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
+ RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
+ RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
+ RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
+ },
+};
+static const union vin_data vin4_data_mux = {
+ .data24 = {
+ VI4_DATA0_MARK, VI4_DATA1_MARK,
+ VI4_DATA2_MARK, VI4_DATA3_MARK,
+ VI4_DATA4_MARK, VI4_DATA5_MARK,
+ VI4_DATA6_MARK, VI4_DATA7_MARK,
+ VI4_DATA8_MARK, VI4_DATA9_MARK,
+ VI4_DATA10_MARK, VI4_DATA11_MARK,
+ VI4_DATA12_MARK, VI4_DATA13_MARK,
+ VI4_DATA14_MARK, VI4_DATA15_MARK,
+ VI4_DATA16_MARK, VI4_DATA17_MARK,
+ VI4_DATA18_MARK, VI4_DATA19_MARK,
+ VI4_DATA20_MARK, VI4_DATA21_MARK,
+ VI4_DATA22_MARK, VI4_DATA23_MARK,
+ },
+};
+static const unsigned int vin4_sync_pins[] = {
+ /* HSYNC#, VSYNC# */
+ RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
+};
+static const unsigned int vin4_sync_mux[] = {
+ VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
+};
+static const unsigned int vin4_field_pins[] = {
+ /* FIELD */
+ RCAR_GP_PIN(2, 27),
+};
+static const unsigned int vin4_field_mux[] = {
+ VI4_FIELD_MARK,
+};
+static const unsigned int vin4_clkenb_pins[] = {
+ /* CLKENB */
+ RCAR_GP_PIN(2, 28),
+};
+static const unsigned int vin4_clkenb_mux[] = {
+ VI4_CLKENB_MARK,
+};
+static const unsigned int vin4_clk_pins[] = {
+ /* CLK */
+ RCAR_GP_PIN(2, 0),
+};
+static const unsigned int vin4_clk_mux[] = {
+ VI4_CLK_MARK,
+};
+
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(audio_clk_a),
SH_PFC_PIN_GROUP(audio_clk_b),
@@ -1553,7 +1718,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(avb0_link),
SH_PFC_PIN_GROUP(avb0_magic),
SH_PFC_PIN_GROUP(avb0_phy_int),
- SH_PFC_PIN_GROUP(avb0_mdc),
+ SH_PFC_PIN_GROUP_ALIAS(avb0_mdc, avb0_mdio), /* Deprecated */
+ SH_PFC_PIN_GROUP(avb0_mdio),
SH_PFC_PIN_GROUP(avb0_mii),
SH_PFC_PIN_GROUP(avb0_avtp_pps_a),
SH_PFC_PIN_GROUP(avb0_avtp_match_a),
@@ -1568,6 +1734,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(can_clk),
SH_PFC_PIN_GROUP(canfd0_data),
SH_PFC_PIN_GROUP(canfd1_data),
+ SH_PFC_PIN_GROUP(du_rgb666),
+ SH_PFC_PIN_GROUP(du_rgb888),
+ SH_PFC_PIN_GROUP(du_clk_in_1),
+ SH_PFC_PIN_GROUP(du_clk_out_0),
+ SH_PFC_PIN_GROUP(du_sync),
+ SH_PFC_PIN_GROUP(du_disp_cde),
+ SH_PFC_PIN_GROUP(du_cde),
+ SH_PFC_PIN_GROUP(du_disp),
SH_PFC_PIN_GROUP(i2c0),
SH_PFC_PIN_GROUP(i2c1),
SH_PFC_PIN_GROUP(i2c2_a),
@@ -1622,6 +1796,17 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(ssi4_ctrl_b),
SH_PFC_PIN_GROUP(ssi4_data_b),
SH_PFC_PIN_GROUP(usb0),
+ VIN_DATA_PIN_GROUP(vin4_data, 8),
+ VIN_DATA_PIN_GROUP(vin4_data, 10),
+ VIN_DATA_PIN_GROUP(vin4_data, 12),
+ VIN_DATA_PIN_GROUP(vin4_data, 16),
+ SH_PFC_PIN_GROUP(vin4_data18),
+ VIN_DATA_PIN_GROUP(vin4_data, 20),
+ VIN_DATA_PIN_GROUP(vin4_data, 24),
+ SH_PFC_PIN_GROUP(vin4_sync),
+ SH_PFC_PIN_GROUP(vin4_field),
+ SH_PFC_PIN_GROUP(vin4_clkenb),
+ SH_PFC_PIN_GROUP(vin4_clk),
};
static const char * const audio_clk_groups[] = {
@@ -1635,7 +1820,8 @@ static const char * const avb0_groups[] = {
"avb0_link",
"avb0_magic",
"avb0_phy_int",
- "avb0_mdc",
+ "avb0_mdc", /* Deprecated, please use "avb0_mdio" instead */
+ "avb0_mdio",
"avb0_mii",
"avb0_avtp_pps_a",
"avb0_avtp_match_a",
@@ -1664,6 +1850,17 @@ static const char * const canfd1_groups[] = {
"canfd1_data",
};
+static const char * const du_groups[] = {
+ "du_rgb666",
+ "du_rgb888",
+ "du_clk_in_1",
+ "du_clk_out_0",
+ "du_sync",
+ "du_disp_cde",
+ "du_cde",
+ "du_disp",
+};
+
static const char * const i2c0_groups[] = {
"i2c0",
};
@@ -1771,6 +1968,20 @@ static const char * const usb0_groups[] = {
"usb0",
};
+static const char * const vin4_groups[] = {
+ "vin4_data8",
+ "vin4_data10",
+ "vin4_data12",
+ "vin4_data16",
+ "vin4_data18",
+ "vin4_data20",
+ "vin4_data24",
+ "vin4_sync",
+ "vin4_field",
+ "vin4_clkenb",
+ "vin4_clk",
+};
+
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(audio_clk),
SH_PFC_FUNCTION(avb0),
@@ -1779,6 +1990,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(can_clk),
SH_PFC_FUNCTION(canfd0),
SH_PFC_FUNCTION(canfd1),
+ SH_PFC_FUNCTION(du),
SH_PFC_FUNCTION(i2c0),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
@@ -1797,6 +2009,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(scif_clk),
SH_PFC_FUNCTION(ssi),
SH_PFC_FUNCTION(usb0),
+ SH_PFC_FUNCTION(vin4),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 736634aee500..70db21638901 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -75,7 +75,7 @@ static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
unsigned offset)
{
- seq_printf(s, "%s", DRV_NAME);
+ seq_puts(s, DRV_NAME);
}
#ifdef CONFIG_OF
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 5747ab0472df..7fad897cd9f5 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -39,13 +39,14 @@ struct sh_pfc_pin {
unsigned int configs;
};
-#define SH_PFC_PIN_GROUP(n) \
+#define SH_PFC_PIN_GROUP_ALIAS(alias, n) \
{ \
- .name = #n, \
+ .name = #alias, \
.pins = n##_pins, \
.mux = n##_mux, \
.nr_pins = ARRAY_SIZE(n##_pins), \
}
+#define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n)
struct sh_pfc_pin_group {
const char *name;
@@ -283,7 +284,9 @@ extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info;
extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
+extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
+extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
extern const struct sh_pfc_soc_info sh7203_pinmux_info;
extern const struct sh_pfc_soc_info sh7264_pinmux_info;
@@ -470,9 +473,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
#define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0)
-#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
+#define PORT_GP_CFG_25(bank, fn, sfx, cfg) \
PORT_GP_CFG_24(bank, fn, sfx, cfg), \
- PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), \
+ PORT_GP_CFG_1(bank, 24, fn, sfx, cfg)
+#define PORT_GP_25(bank, fn, sfx) PORT_GP_CFG_25(bank, fn, sfx, 0)
+
+#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
+ PORT_GP_CFG_25(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
#define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig
index 1c4e00b2eb65..cd3936e3afaa 100644
--- a/drivers/pinctrl/stm32/Kconfig
+++ b/drivers/pinctrl/stm32/Kconfig
@@ -11,37 +11,37 @@ config PINCTRL_STM32
config PINCTRL_STM32F429
bool "STMicroelectronics STM32F429 pin control" if COMPILE_TEST && !MACH_STM32F429
- depends on OF
+ depends on OF && HAS_IOMEM
default MACH_STM32F429
select PINCTRL_STM32
config PINCTRL_STM32F469
bool "STMicroelectronics STM32F469 pin control" if COMPILE_TEST && !MACH_STM32F469
- depends on OF
+ depends on OF && HAS_IOMEM
default MACH_STM32F469
select PINCTRL_STM32
config PINCTRL_STM32F746
bool "STMicroelectronics STM32F746 pin control" if COMPILE_TEST && !MACH_STM32F746
- depends on OF
+ depends on OF && HAS_IOMEM
default MACH_STM32F746
select PINCTRL_STM32
config PINCTRL_STM32F769
bool "STMicroelectronics STM32F769 pin control" if COMPILE_TEST && !MACH_STM32F769
- depends on OF
+ depends on OF && HAS_IOMEM
default MACH_STM32F769
select PINCTRL_STM32
config PINCTRL_STM32H743
bool "STMicroelectronics STM32H743 pin control" if COMPILE_TEST && !MACH_STM32H743
- depends on OF
+ depends on OF && HAS_IOMEM
default MACH_STM32H743
select PINCTRL_STM32
config PINCTRL_STM32MP157
bool "STMicroelectronics STM32MP157 pin control" if COMPILE_TEST && !MACH_STM32MP157
- depends on OF
+ depends on OF && HAS_IOMEM
default MACH_STM32MP157
select PINCTRL_STM32
endif
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
index 617df163067f..6cbcff42ba47 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -268,10 +268,11 @@ static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
static struct irq_chip stm32_gpio_irq_chip = {
.name = "stm32gpio",
- .irq_eoi = irq_chip_eoi_parent,
+ .irq_ack = irq_chip_ack_parent,
.irq_mask = irq_chip_mask_parent,
.irq_unmask = irq_chip_unmask_parent,
.irq_set_type = irq_chip_set_type_parent,
+ .irq_set_wake = irq_chip_set_wake_parent,
.irq_request_resources = stm32_gpio_irq_request_resources,
.irq_release_resources = stm32_gpio_irq_release_resources,
};
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index bfce99d86dfc..5de1f63b07bb 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -77,4 +77,8 @@ config PINCTRL_SUN50I_H5
def_bool ARM64 && ARCH_SUNXI
select PINCTRL_SUNXI
+config PINCTRL_SUN50I_H6
+ def_bool ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
endif
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index 12a752e836ef..3c4aec6611e9 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -18,5 +18,6 @@ obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o
obj-$(CONFIG_PINCTRL_SUN8I_V3S) += pinctrl-sun8i-v3s.o
obj-$(CONFIG_PINCTRL_SUN50I_H5) += pinctrl-sun50i-h5.o
+obj-$(CONFIG_PINCTRL_SUN50I_H6) += pinctrl-sun50i-h6.o
obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o
obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
new file mode 100644
index 000000000000..aa8b58125568
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
@@ -0,0 +1,614 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Allwinner H6 SoC pinctrl driver.
+ *
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin h6_pins[] = {
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
+ SUNXI_FUNCTION(0x2, "emac")), /* ERXD1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
+ SUNXI_FUNCTION(0x2, "emac")), /* ERXD0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
+ SUNXI_FUNCTION(0x2, "emac")), /* ECRS_DV */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
+ SUNXI_FUNCTION(0x2, "emac")), /* ERXERR */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
+ SUNXI_FUNCTION(0x2, "emac")), /* ETXD1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
+ SUNXI_FUNCTION(0x2, "emac")), /* ETXD0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
+ SUNXI_FUNCTION(0x2, "emac")), /* ETXCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
+ SUNXI_FUNCTION(0x2, "emac")), /* ETXEN */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
+ SUNXI_FUNCTION(0x2, "emac")), /* EMDC */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
+ SUNXI_FUNCTION(0x2, "emac")), /* EMDIO */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
+ SUNXI_FUNCTION(0x2, "ccir"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
+ SUNXI_FUNCTION(0x2, "ccir"), /* DE */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
+ SUNXI_FUNCTION(0x2, "ccir"), /* HSYNC */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
+ SUNXI_FUNCTION(0x2, "ccir"), /* VSYNC */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
+ SUNXI_FUNCTION(0x2, "ccir"), /* DO0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
+ SUNXI_FUNCTION(0x2, "ccir"), /* DO1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
+ SUNXI_FUNCTION(0x2, "ccir"), /* DO2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
+ SUNXI_FUNCTION(0x2, "ccir"), /* DO3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
+ SUNXI_FUNCTION(0x2, "ccir"), /* DO4 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
+ SUNXI_FUNCTION(0x2, "ccir"), /* DO5 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
+ SUNXI_FUNCTION(0x2, "ccir"), /* DO6 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
+ SUNXI_FUNCTION(0x2, "ccir"), /* DO7 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
+ SUNXI_FUNCTION(0x2, "i2s3"), /* SYNC */
+ SUNXI_FUNCTION(0x4, "h_i2s3"), /* SYNC */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
+ SUNXI_FUNCTION(0x2, "i2s3"), /* CLK */
+ SUNXI_FUNCTION(0x4, "h_i2s3"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
+ SUNXI_FUNCTION(0x2, "i2s3"), /* DOUT */
+ SUNXI_FUNCTION(0x4, "h_i2s3"), /* DOUT */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
+ SUNXI_FUNCTION(0x2, "i2s3"), /* DIN */
+ SUNXI_FUNCTION(0x4, "h_i2s3"), /* DIN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
+ SUNXI_FUNCTION(0x2, "i2s3"), /* MCLK */
+ SUNXI_FUNCTION(0x4, "h_i2s3"), /* MCLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
+ SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
+ SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19),
+ SUNXI_FUNCTION(0x2, "pwm1"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)),
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* WE */
+ SUNXI_FUNCTION(0x4, "spi0")), /* CLK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* DS */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
+ SUNXI_FUNCTION(0x4, "spi0")), /* MOSI */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */
+ SUNXI_FUNCTION(0x4, "spi0")), /* MISO */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* RE */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
+ SUNXI_FUNCTION(0x4, "spi0")), /* CS */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
+ SUNXI_FUNCTION(0x4, "spi0")), /* HOLD */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
+ SUNXI_FUNCTION(0x4, "spi0")), /* WP */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
+ SUNXI_FUNCTION(0x3, "ts0"), /* CLK */
+ SUNXI_FUNCTION(0x4, "csi"), /* PCLK */
+ SUNXI_FUNCTION(0x5, "emac")), /* ERXD3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
+ SUNXI_FUNCTION(0x3, "ts0"), /* ERR */
+ SUNXI_FUNCTION(0x4, "csi"), /* MCLK */
+ SUNXI_FUNCTION(0x5, "emac")), /* ERXD2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
+ SUNXI_FUNCTION(0x3, "ts0"), /* SYNC */
+ SUNXI_FUNCTION(0x4, "csi"), /* HSYNC */
+ SUNXI_FUNCTION(0x5, "emac")), /* ERXD1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
+ SUNXI_FUNCTION(0x3, "ts0"), /* DVLD */
+ SUNXI_FUNCTION(0x4, "csi"), /* VSYNC */
+ SUNXI_FUNCTION(0x5, "emac")), /* ERXD0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
+ SUNXI_FUNCTION(0x3, "ts0"), /* D0 */
+ SUNXI_FUNCTION(0x4, "csi"), /* D0 */
+ SUNXI_FUNCTION(0x5, "emac")), /* ERXCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
+ SUNXI_FUNCTION(0x3, "ts0"), /* D1 */
+ SUNXI_FUNCTION(0x4, "csi"), /* D1 */
+ SUNXI_FUNCTION(0x5, "emac")), /* ERXCTL */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
+ SUNXI_FUNCTION(0x3, "ts0"), /* D2 */
+ SUNXI_FUNCTION(0x4, "csi"), /* D2 */
+ SUNXI_FUNCTION(0x5, "emac")), /* ENULL */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
+ SUNXI_FUNCTION(0x3, "ts0"), /* D3 */
+ SUNXI_FUNCTION(0x4, "csi"), /* D3 */
+ SUNXI_FUNCTION(0x5, "emac")), /* ETXD3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
+ SUNXI_FUNCTION(0x3, "ts0"), /* D4 */
+ SUNXI_FUNCTION(0x4, "csi"), /* D4 */
+ SUNXI_FUNCTION(0x5, "emac")), /* ETXD2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
+ SUNXI_FUNCTION(0x3, "ts0"), /* D5 */
+ SUNXI_FUNCTION(0x4, "csi"), /* D5 */
+ SUNXI_FUNCTION(0x5, "emac")), /* ETXD1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
+ SUNXI_FUNCTION(0x3, "ts0"), /* D6 */
+ SUNXI_FUNCTION(0x4, "csi"), /* D6 */
+ SUNXI_FUNCTION(0x5, "emac")), /* ETXD0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
+ SUNXI_FUNCTION(0x3, "ts0"), /* D7 */
+ SUNXI_FUNCTION(0x4, "csi"), /* D7 */
+ SUNXI_FUNCTION(0x5, "emac")), /* ETXCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
+ SUNXI_FUNCTION(0x3, "ts1"), /* CLK */
+ SUNXI_FUNCTION(0x4, "csi"), /* SCK */
+ SUNXI_FUNCTION(0x5, "emac")), /* ETXCTL */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
+ SUNXI_FUNCTION(0x3, "ts1"), /* ERR */
+ SUNXI_FUNCTION(0x4, "csi"), /* SDA */
+ SUNXI_FUNCTION(0x5, "emac")), /* ECLKIN */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
+ SUNXI_FUNCTION(0x3, "ts1"), /* SYNC */
+ SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
+ SUNXI_FUNCTION(0x5, "csi")), /* D8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
+ SUNXI_FUNCTION(0x3, "ts1"), /* DVLD */
+ SUNXI_FUNCTION(0x4, "dmic"), /* DATA0 */
+ SUNXI_FUNCTION(0x5, "csi")), /* D9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
+ SUNXI_FUNCTION(0x3, "ts1"), /* D0 */
+ SUNXI_FUNCTION(0x4, "dmic")), /* DATA1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
+ SUNXI_FUNCTION(0x3, "ts2"), /* CLK */
+ SUNXI_FUNCTION(0x4, "dmic")), /* DATA2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
+ SUNXI_FUNCTION(0x3, "ts2"), /* ERR */
+ SUNXI_FUNCTION(0x4, "dmic")), /* DATA3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
+ SUNXI_FUNCTION(0x3, "ts2"), /* SYNC */
+ SUNXI_FUNCTION(0x4, "uart2"), /* TX */
+ SUNXI_FUNCTION(0x5, "emac")), /* EMDC */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
+ SUNXI_FUNCTION(0x3, "ts2"), /* DVLD */
+ SUNXI_FUNCTION(0x4, "uart2"), /* RX */
+ SUNXI_FUNCTION(0x5, "emac")), /* EMDIO */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
+ SUNXI_FUNCTION(0x3, "ts2"), /* D0 */
+ SUNXI_FUNCTION(0x4, "uart2")), /* RTS */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */
+ SUNXI_FUNCTION(0x3, "ts3"), /* CLK */
+ SUNXI_FUNCTION(0x4, "uart2")), /* CTS */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c2"), /* SCK */
+ SUNXI_FUNCTION(0x3, "ts3"), /* ERR */
+ SUNXI_FUNCTION(0x4, "uart3"), /* TX */
+ SUNXI_FUNCTION(0x5, "jtag")), /* MS */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c2"), /* SDA */
+ SUNXI_FUNCTION(0x3, "ts3"), /* SYNC */
+ SUNXI_FUNCTION(0x4, "uart3"), /* RX */
+ SUNXI_FUNCTION(0x5, "jtag")), /* CK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
+ SUNXI_FUNCTION(0x3, "ts3"), /* DVLD */
+ SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
+ SUNXI_FUNCTION(0x5, "jtag")), /* DO */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
+ SUNXI_FUNCTION(0x3, "ts3"), /* D0 */
+ SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
+ SUNXI_FUNCTION(0x5, "jtag")), /* DI */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
+ SUNXI_FUNCTION(0x3, "jtag"), /* MS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PF_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
+ SUNXI_FUNCTION(0x3, "jtag"), /* DI */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PF_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
+ SUNXI_FUNCTION(0x3, "uart0"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PF_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
+ SUNXI_FUNCTION(0x3, "jtag"), /* DO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PF_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
+ SUNXI_FUNCTION(0x3, "uart0"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PF_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
+ SUNXI_FUNCTION(0x3, "jtag"), /* CK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PF_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PF_EINT6 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PG_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PG_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PG_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PG_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PG_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PG_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart1"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PG_EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart1"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PG_EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
+ SUNXI_FUNCTION(0x4, "sim0"), /* VPPEN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PG_EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
+ SUNXI_FUNCTION(0x4, "sim0"), /* VPPPP */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PG_EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s2"), /* SYNC */
+ SUNXI_FUNCTION(0x3, "h_i2s2"), /* SYNC */
+ SUNXI_FUNCTION(0x4, "sim0"), /* PWREN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PG_EINT10 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s2"), /* CLK */
+ SUNXI_FUNCTION(0x3, "h_i2s2"), /* CLK */
+ SUNXI_FUNCTION(0x4, "sim0"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PG_EINT11 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s2"), /* DOUT */
+ SUNXI_FUNCTION(0x3, "h_i2s2"), /* DOUT */
+ SUNXI_FUNCTION(0x4, "sim0"), /* DATA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PG_EINT12 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s2"), /* DIN */
+ SUNXI_FUNCTION(0x3, "h_i2s2"), /* DIN */
+ SUNXI_FUNCTION(0x4, "sim0"), /* RST */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PG_EINT13 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s2"), /* MCLK */
+ SUNXI_FUNCTION(0x3, "h_i2s2"), /* MCLK */
+ SUNXI_FUNCTION(0x4, "sim0"), /* DET */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PG_EINT14 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart0"), /* TX */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* SYNC */
+ SUNXI_FUNCTION(0x4, "h_i2s0"), /* SYNC */
+ SUNXI_FUNCTION(0x5, "sim1"), /* VPPEN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PH_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart0"), /* RX */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* CLK */
+ SUNXI_FUNCTION(0x4, "h_i2s0"), /* CLK */
+ SUNXI_FUNCTION(0x5, "sim1"), /* VPPPP */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PH_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ir_tx"),
+ SUNXI_FUNCTION(0x3, "i2s0"), /* DOUT */
+ SUNXI_FUNCTION(0x4, "h_i2s0"), /* DOUT */
+ SUNXI_FUNCTION(0x5, "sim1"), /* PWREN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PH_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* CS */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* DIN */
+ SUNXI_FUNCTION(0x4, "h_i2s0"), /* DIN */
+ SUNXI_FUNCTION(0x5, "sim1"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PH_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* MCLK */
+ SUNXI_FUNCTION(0x4, "h_i2s0"), /* MCLK */
+ SUNXI_FUNCTION(0x5, "sim1"), /* DATA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PH_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
+ SUNXI_FUNCTION(0x3, "spdif"), /* MCLK */
+ SUNXI_FUNCTION(0x4, "i2c1"), /* SCK */
+ SUNXI_FUNCTION(0x5, "sim1"), /* RST */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PH_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
+ SUNXI_FUNCTION(0x3, "spdif"), /* IN */
+ SUNXI_FUNCTION(0x4, "i2c1"), /* SDA */
+ SUNXI_FUNCTION(0x5, "sim1"), /* DET */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PH_EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "spdif"), /* OUT */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PH_EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "hdmi"), /* HSCL */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PH_EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "hdmi"), /* HSDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PH_EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "hdmi"), /* HCEC */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PH_EINT10 */
+};
+
+static const unsigned int h6_irq_bank_map[] = { 1, 5, 6, 7 };
+
+static const struct sunxi_pinctrl_desc h6_pinctrl_data = {
+ .pins = h6_pins,
+ .npins = ARRAY_SIZE(h6_pins),
+ .irq_banks = 3,
+ .irq_bank_map = h6_irq_bank_map,
+ .irq_read_needs_mux = true,
+};
+
+static int h6_pinctrl_probe(struct platform_device *pdev)
+{
+ return sunxi_pinctrl_init(pdev,
+ &h6_pinctrl_data);
+}
+
+static const struct of_device_id h6_pinctrl_match[] = {
+ { .compatible = "allwinner,sun50i-h6-pinctrl", },
+ {}
+};
+
+static struct platform_driver h6_pinctrl_driver = {
+ .probe = h6_pinctrl_probe,
+ .driver = {
+ .name = "sun50i-h6-pinctrl",
+ .of_match_table = h6_pinctrl_match,
+ },
+};
+builtin_platform_driver(h6_pinctrl_driver);
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
index da387211a75e..f043afa1aac5 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
@@ -481,11 +481,13 @@ static const struct sunxi_desc_pin sun8i_a33_pins[] = {
SUNXI_FUNCTION(0x3, "uart3")), /* CTS */
};
+static const unsigned int sun8i_a33_pinctrl_irq_bank_map[] = { 1, 2 };
+
static const struct sunxi_pinctrl_desc sun8i_a33_pinctrl_data = {
.pins = sun8i_a33_pins,
.npins = ARRAY_SIZE(sun8i_a33_pins),
.irq_banks = 2,
- .irq_bank_base = 1,
+ .irq_bank_map = sun8i_a33_pinctrl_irq_bank_map,
.disable_strict_mode = true,
};
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
index 496ba34e1f5f..6704ce8e5e3d 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
@@ -293,11 +293,13 @@ static const struct sunxi_desc_pin sun8i_v3s_pins[] = {
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */
};
+static const unsigned int sun8i_v3s_pinctrl_irq_bank_map[] = { 1, 2 };
+
static const struct sunxi_pinctrl_desc sun8i_v3s_pinctrl_data = {
.pins = sun8i_v3s_pins,
.npins = ARRAY_SIZE(sun8i_v3s_pins),
.irq_banks = 2,
- .irq_bank_base = 1,
+ .irq_bank_map = sun8i_v3s_pinctrl_irq_bank_map,
.irq_read_needs_mux = true
};
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 341312d66512..020d6d84639c 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -835,7 +835,7 @@ static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
{
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
- u32 reg = sunxi_irq_cfg_reg(d->hwirq, pctl->desc->irq_bank_base);
+ u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq);
u8 index = sunxi_irq_cfg_offset(d->hwirq);
unsigned long flags;
u32 regval;
@@ -882,8 +882,7 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
static void sunxi_pinctrl_irq_ack(struct irq_data *d)
{
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
- u32 status_reg = sunxi_irq_status_reg(d->hwirq,
- pctl->desc->irq_bank_base);
+ u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq);
u8 status_idx = sunxi_irq_status_offset(d->hwirq);
/* Clear the IRQ */
@@ -893,7 +892,7 @@ static void sunxi_pinctrl_irq_ack(struct irq_data *d)
static void sunxi_pinctrl_irq_mask(struct irq_data *d)
{
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
- u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base);
+ u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
unsigned long flags;
u32 val;
@@ -910,7 +909,7 @@ static void sunxi_pinctrl_irq_mask(struct irq_data *d)
static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
{
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
- u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base);
+ u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
unsigned long flags;
u32 val;
@@ -1002,7 +1001,7 @@ static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
if (bank == pctl->desc->irq_banks)
return;
- reg = sunxi_irq_status_reg_from_bank(bank, pctl->desc->irq_bank_base);
+ reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank);
val = readl(pctl->membase + reg);
if (val) {
@@ -1234,8 +1233,7 @@ static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,
writel(src | div << 4,
pctl->membase +
- sunxi_irq_debounce_reg_from_bank(i,
- pctl->desc->irq_bank_base));
+ sunxi_irq_debounce_reg_from_bank(pctl->desc, i));
}
return 0;
@@ -1363,7 +1361,8 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
goto gpiochip_error;
}
- clk = devm_clk_get(&pdev->dev, NULL);
+ ret = of_count_phandle_with_args(node, "clocks", "#clock-cells");
+ clk = devm_clk_get(&pdev->dev, ret == 1 ? NULL : "apb");
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
goto gpiochip_error;
@@ -1410,11 +1409,11 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
for (i = 0; i < pctl->desc->irq_banks; i++) {
/* Mask and clear all IRQs before registering a handler */
- writel(0, pctl->membase + sunxi_irq_ctrl_reg_from_bank(i,
- pctl->desc->irq_bank_base));
+ writel(0, pctl->membase +
+ sunxi_irq_ctrl_reg_from_bank(pctl->desc, i));
writel(0xffffffff,
- pctl->membase + sunxi_irq_status_reg_from_bank(i,
- pctl->desc->irq_bank_base));
+ pctl->membase +
+ sunxi_irq_status_reg_from_bank(pctl->desc, i));
irq_set_chained_handler_and_data(pctl->irq[i],
sunxi_pinctrl_irq_handler,
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
index 11b128f54ed2..4a892e7dde66 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
@@ -110,7 +110,7 @@ struct sunxi_pinctrl_desc {
int npins;
unsigned pin_base;
unsigned irq_banks;
- unsigned irq_bank_base;
+ const unsigned int *irq_bank_map;
bool irq_read_needs_mux;
bool disable_strict_mode;
};
@@ -263,12 +263,22 @@ static inline u32 sunxi_pull_offset(u16 pin)
return pin_num * PULL_PINS_BITS;
}
-static inline u32 sunxi_irq_cfg_reg(u16 irq, unsigned bank_base)
+static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank)
+{
+ if (!desc->irq_bank_map)
+ return bank;
+ else
+ return desc->irq_bank_map[bank];
+}
+
+static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc,
+ u16 irq)
{
u8 bank = irq / IRQ_PER_BANK;
u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;
- return IRQ_CFG_REG + (bank_base + bank) * IRQ_MEM_SIZE + reg;
+ return IRQ_CFG_REG +
+ sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg;
}
static inline u32 sunxi_irq_cfg_offset(u16 irq)
@@ -277,16 +287,17 @@ static inline u32 sunxi_irq_cfg_offset(u16 irq)
return irq_num * IRQ_CFG_IRQ_BITS;
}
-static inline u32 sunxi_irq_ctrl_reg_from_bank(u8 bank, unsigned bank_base)
+static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
{
- return IRQ_CTRL_REG + (bank_base + bank) * IRQ_MEM_SIZE;
+ return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
}
-static inline u32 sunxi_irq_ctrl_reg(u16 irq, unsigned bank_base)
+static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc *desc,
+ u16 irq)
{
u8 bank = irq / IRQ_PER_BANK;
- return sunxi_irq_ctrl_reg_from_bank(bank, bank_base);
+ return sunxi_irq_ctrl_reg_from_bank(desc, bank);
}
static inline u32 sunxi_irq_ctrl_offset(u16 irq)
@@ -295,21 +306,24 @@ static inline u32 sunxi_irq_ctrl_offset(u16 irq)
return irq_num * IRQ_CTRL_IRQ_BITS;
}
-static inline u32 sunxi_irq_debounce_reg_from_bank(u8 bank, unsigned bank_base)
+static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
{
- return IRQ_DEBOUNCE_REG + (bank_base + bank) * IRQ_MEM_SIZE;
+ return IRQ_DEBOUNCE_REG +
+ sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
}
-static inline u32 sunxi_irq_status_reg_from_bank(u8 bank, unsigned bank_base)
+static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
{
- return IRQ_STATUS_REG + (bank_base + bank) * IRQ_MEM_SIZE;
+ return IRQ_STATUS_REG +
+ sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
}
-static inline u32 sunxi_irq_status_reg(u16 irq, unsigned bank_base)
+static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl_desc *desc,
+ u16 irq)
{
u8 bank = irq / IRQ_PER_BANK;
- return sunxi_irq_status_reg_from_bank(bank, bank_base);
+ return sunxi_irq_status_reg_from_bank(desc, bank);
}
static inline u32 sunxi_irq_status_offset(u16 irq)
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
index 8a5ecd6277d8..0976fbfecd50 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
@@ -470,8 +470,10 @@ static const struct pinctrl_pin_desc uniphier_ld11_pins[] = {
166, UNIPHIER_PIN_PULL_DOWN),
};
-static const unsigned aout_pins[] = {135, 136, 137, 138, 139, 140, 141, 142};
-static const int aout_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned aout1_pins[] = {137, 138, 139, 140, 141, 142};
+static const int aout1_muxvals[] = {0, 0, 0, 0, 0, 0};
+static const unsigned aoutiec1_pins[] = {135, 136};
+static const int aoutiec1_muxvals[] = {0, 0};
static const unsigned int emmc_pins[] = {19, 20, 21, 22, 23, 24, 25};
static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0};
static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29};
@@ -504,6 +506,8 @@ static const unsigned uart2_pins[] = {90, 91};
static const int uart2_muxvals[] = {1, 1};
static const unsigned uart3_pins[] = {94, 95};
static const int uart3_muxvals[] = {1, 1};
+static const unsigned uart3_ctsrts_pins[] = {96, 97, 98, 99, 100, 101};
+static const int uart3_ctsrts_muxvals[] = {1, 1, 1, 1, 1, 1};
static const unsigned usb0_pins[] = {46, 47};
static const int usb0_muxvals[] = {0, 0};
static const unsigned usb1_pins[] = {48, 49};
@@ -547,7 +551,8 @@ static const unsigned int gpio_range5_pins[] = {
};
static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = {
- UNIPHIER_PINCTRL_GROUP(aout),
+ UNIPHIER_PINCTRL_GROUP(aout1),
+ UNIPHIER_PINCTRL_GROUP(aoutiec1),
UNIPHIER_PINCTRL_GROUP(emmc),
UNIPHIER_PINCTRL_GROUP(emmc_dat8),
UNIPHIER_PINCTRL_GROUP(ether_rmii),
@@ -562,6 +567,7 @@ static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = {
UNIPHIER_PINCTRL_GROUP(uart1),
UNIPHIER_PINCTRL_GROUP(uart2),
UNIPHIER_PINCTRL_GROUP(uart3),
+ UNIPHIER_PINCTRL_GROUP(uart3_ctsrts),
UNIPHIER_PINCTRL_GROUP(usb0),
UNIPHIER_PINCTRL_GROUP(usb1),
UNIPHIER_PINCTRL_GROUP(usb2),
@@ -573,7 +579,8 @@ static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = {
UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range5),
};
-static const char * const aout_groups[] = {"aout"};
+static const char * const aout1_groups[] = {"aout1"};
+static const char * const aoutiec1_groups[] = {"aoutiec1"};
static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
static const char * const ether_rmii_groups[] = {"ether_rmii"};
static const char * const i2c0_groups[] = {"i2c0"};
@@ -586,13 +593,14 @@ static const char * const system_bus_groups[] = {"system_bus",
static const char * const uart0_groups[] = {"uart0"};
static const char * const uart1_groups[] = {"uart1"};
static const char * const uart2_groups[] = {"uart2"};
-static const char * const uart3_groups[] = {"uart3"};
+static const char * const uart3_groups[] = {"uart3", "uart3_ctsrts"};
static const char * const usb0_groups[] = {"usb0"};
static const char * const usb1_groups[] = {"usb1"};
static const char * const usb2_groups[] = {"usb2"};
static const struct uniphier_pinmux_function uniphier_ld11_functions[] = {
- UNIPHIER_PINMUX_FUNCTION(aout),
+ UNIPHIER_PINMUX_FUNCTION(aout1),
+ UNIPHIER_PINMUX_FUNCTION(aoutiec1),
UNIPHIER_PINMUX_FUNCTION(emmc),
UNIPHIER_PINMUX_FUNCTION(ether_rmii),
UNIPHIER_PINMUX_FUNCTION(i2c0),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
index 3be7967edae0..bf8f0c3bea5e 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
@@ -551,8 +551,10 @@ static const struct pinctrl_pin_desc uniphier_ld20_pins[] = {
175, UNIPHIER_PIN_PULL_DOWN),
};
-static const unsigned aout_pins[] = {135, 136, 137, 138, 139, 140, 141, 142};
-static const int aout_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned aout1_pins[] = {137, 138, 139, 140, 141, 142};
+static const int aout1_muxvals[] = {0, 0, 0, 0, 0, 0};
+static const unsigned aoutiec1_pins[] = {135, 136};
+static const int aoutiec1_muxvals[] = {0, 0};
static const unsigned int emmc_pins[] = {19, 20, 21, 22, 23, 24, 25};
static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0};
static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29};
@@ -591,6 +593,8 @@ static const unsigned uart2_pins[] = {90, 91};
static const int uart2_muxvals[] = {1, 1};
static const unsigned uart3_pins[] = {94, 95};
static const int uart3_muxvals[] = {1, 1};
+static const unsigned uart3_ctsrts_pins[] = {96, 97, 98, 99, 100, 101};
+static const int uart3_ctsrts_muxvals[] = {1, 1, 1, 1, 1, 1};
static const unsigned usb0_pins[] = {46, 47};
static const int usb0_muxvals[] = {0, 0};
static const unsigned usb1_pins[] = {48, 49};
@@ -631,7 +635,8 @@ static const unsigned int gpio_range2_pins[] = {
};
static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
- UNIPHIER_PINCTRL_GROUP(aout),
+ UNIPHIER_PINCTRL_GROUP(aout1),
+ UNIPHIER_PINCTRL_GROUP(aoutiec1),
UNIPHIER_PINCTRL_GROUP(emmc),
UNIPHIER_PINCTRL_GROUP(emmc_dat8),
UNIPHIER_PINCTRL_GROUP(ether_rgmii),
@@ -648,6 +653,7 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
UNIPHIER_PINCTRL_GROUP(uart1),
UNIPHIER_PINCTRL_GROUP(uart2),
UNIPHIER_PINCTRL_GROUP(uart3),
+ UNIPHIER_PINCTRL_GROUP(uart3_ctsrts),
UNIPHIER_PINCTRL_GROUP(usb0),
UNIPHIER_PINCTRL_GROUP(usb1),
UNIPHIER_PINCTRL_GROUP(usb2),
@@ -657,7 +663,8 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range2),
};
-static const char * const aout_groups[] = {"aout"};
+static const char * const aout1_groups[] = {"aout1"};
+static const char * const aoutiec1_groups[] = {"aoutiec1"};
static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
static const char * const ether_rgmii_groups[] = {"ether_rgmii"};
static const char * const ether_rmii_groups[] = {"ether_rmii"};
@@ -672,14 +679,15 @@ static const char * const system_bus_groups[] = {"system_bus",
static const char * const uart0_groups[] = {"uart0"};
static const char * const uart1_groups[] = {"uart1"};
static const char * const uart2_groups[] = {"uart2"};
-static const char * const uart3_groups[] = {"uart3"};
+static const char * const uart3_groups[] = {"uart3", "uart3_ctsrts"};
static const char * const usb0_groups[] = {"usb0"};
static const char * const usb1_groups[] = {"usb1"};
static const char * const usb2_groups[] = {"usb2"};
static const char * const usb3_groups[] = {"usb3"};
static const struct uniphier_pinmux_function uniphier_ld20_functions[] = {
- UNIPHIER_PINMUX_FUNCTION(aout),
+ UNIPHIER_PINMUX_FUNCTION(aout1),
+ UNIPHIER_PINMUX_FUNCTION(aoutiec1),
UNIPHIER_PINMUX_FUNCTION(emmc),
UNIPHIER_PINMUX_FUNCTION(ether_rgmii),
UNIPHIER_PINMUX_FUNCTION(ether_rmii),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
index 840382847212..0b10ebc07eb8 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
@@ -590,6 +590,8 @@ static const unsigned system_bus_cs3_pins[] = {156};
static const int system_bus_cs3_muxvals[] = {1};
static const unsigned uart0_pins[] = {85, 88};
static const int uart0_muxvals[] = {1, 1};
+static const unsigned uart0_ctsrts_pins[] = {86, 87, 89};
+static const int uart0_ctsrts_muxvals[] = {1, 1, 1};
static const unsigned uart1_pins[] = {155, 156};
static const int uart1_muxvals[] = {13, 13};
static const unsigned uart1b_pins[] = {69, 70};
@@ -644,6 +646,7 @@ static const struct uniphier_pinctrl_group uniphier_ld4_groups[] = {
UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart0_ctsrts),
UNIPHIER_PINCTRL_GROUP(uart1),
UNIPHIER_PINCTRL_GROUP(uart1b),
UNIPHIER_PINCTRL_GROUP(uart2),
@@ -669,7 +672,7 @@ static const char * const system_bus_groups[] = {"system_bus",
"system_bus_cs1",
"system_bus_cs2",
"system_bus_cs3"};
-static const char * const uart0_groups[] = {"uart0"};
+static const char * const uart0_groups[] = {"uart0", "uart0_ctsrts"};
static const char * const uart1_groups[] = {"uart1", "uart1b"};
static const char * const uart2_groups[] = {"uart2"};
static const char * const uart3_groups[] = {"uart3"};
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
index 493a90c6d733..8e4d45fea885 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
@@ -785,6 +785,8 @@ static const unsigned system_bus_cs5_pins[] = {55};
static const int system_bus_cs5_muxvals[] = {6};
static const unsigned uart0_pins[] = {135, 136};
static const int uart0_muxvals[] = {3, 3};
+static const unsigned uart0_ctsrts_pins[] = {137, 138, 139, 140, 141, 124};
+static const int uart0_ctsrts_muxvals[] = {3, 3, 3, 3, 3, 3};
static const unsigned uart0b_pins[] = {11, 12};
static const int uart0b_muxvals[] = {2, 2};
static const unsigned uart1_pins[] = {115, 116};
@@ -856,6 +858,7 @@ static const struct uniphier_pinctrl_group uniphier_ld6b_groups[] = {
UNIPHIER_PINCTRL_GROUP(system_bus_cs4),
UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart0_ctsrts),
UNIPHIER_PINCTRL_GROUP(uart0b),
UNIPHIER_PINCTRL_GROUP(uart1),
UNIPHIER_PINCTRL_GROUP(uart1b),
@@ -885,7 +888,7 @@ static const char * const system_bus_groups[] = {"system_bus",
"system_bus_cs3",
"system_bus_cs4",
"system_bus_cs5"};
-static const char * const uart0_groups[] = {"uart0", "uart0b"};
+static const char * const uart0_groups[] = {"uart0", "uart0_ctsrts", "uart0b"};
static const char * const uart1_groups[] = {"uart1", "uart1b"};
static const char * const uart2_groups[] = {"uart2", "uart2b"};
static const char * const usb0_groups[] = {"usb0"};
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
index 603204a00213..24788a74c254 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
@@ -1078,6 +1078,8 @@ static const unsigned uart2_pins[] = {131, 132};
static const int uart2_muxvals[] = {0, 0};
static const unsigned uart3_pins[] = {88, 89};
static const int uart3_muxvals[] = {2, 2};
+static const unsigned uart3_ctsrts_pins[] = {80, 81, 82, 83, 90, 91};
+static const int uart3_ctsrts_muxvals[] = {2, 2, 2, 2, 2, 2};
static const unsigned usb0_pins[] = {180, 181};
static const int usb0_muxvals[] = {0, 0};
static const unsigned usb1_pins[] = {182, 183};
@@ -1149,6 +1151,7 @@ static const struct uniphier_pinctrl_group uniphier_pro4_groups[] = {
UNIPHIER_PINCTRL_GROUP(uart1),
UNIPHIER_PINCTRL_GROUP(uart2),
UNIPHIER_PINCTRL_GROUP(uart3),
+ UNIPHIER_PINCTRL_GROUP(uart3_ctsrts),
UNIPHIER_PINCTRL_GROUP(usb0),
UNIPHIER_PINCTRL_GROUP(usb1),
UNIPHIER_PINCTRL_GROUP(usb2),
@@ -1180,7 +1183,7 @@ static const char * const system_bus_groups[] = {"system_bus",
static const char * const uart0_groups[] = {"uart0"};
static const char * const uart1_groups[] = {"uart1"};
static const char * const uart2_groups[] = {"uart2"};
-static const char * const uart3_groups[] = {"uart3"};
+static const char * const uart3_groups[] = {"uart3", "uart3_ctsrts"};
static const char * const usb0_groups[] = {"usb0"};
static const char * const usb1_groups[] = {"usb1"};
static const char * const usb2_groups[] = {"usb2"};
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
index 9381a4ff4389..d5d5e579cb08 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
@@ -842,6 +842,8 @@ static const unsigned uart0_pins[] = {47, 48};
static const int uart0_muxvals[] = {0, 0};
static const unsigned uart0b_pins[] = {227, 228};
static const int uart0b_muxvals[] = {3, 3};
+static const unsigned uart0b_ctsrts_pins[] = {229, 230, 231, 232, 233, 234};
+static const int uart0b_ctsrts_muxvals[] = {3, 3, 3, 3, 3, 3};
static const unsigned uart1_pins[] = {49, 50};
static const int uart1_muxvals[] = {0, 0};
static const unsigned uart2_pins[] = {51, 52};
@@ -913,6 +915,7 @@ static const struct uniphier_pinctrl_group uniphier_pro5_groups[] = {
UNIPHIER_PINCTRL_GROUP(system_bus_cs7),
UNIPHIER_PINCTRL_GROUP(uart0),
UNIPHIER_PINCTRL_GROUP(uart0b),
+ UNIPHIER_PINCTRL_GROUP(uart0b_ctsrts),
UNIPHIER_PINCTRL_GROUP(uart1),
UNIPHIER_PINCTRL_GROUP(uart2),
UNIPHIER_PINCTRL_GROUP(uart3),
@@ -940,7 +943,7 @@ static const char * const system_bus_groups[] = {"system_bus",
"system_bus_cs5",
"system_bus_cs6",
"system_bus_cs7"};
-static const char * const uart0_groups[] = {"uart0", "uart0b"};
+static const char * const uart0_groups[] = {"uart0", "uart0b", "uart0b_ctsrts"};
static const char * const uart1_groups[] = {"uart1"};
static const char * const uart2_groups[] = {"uart2"};
static const char * const uart3_groups[] = {"uart3"};
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
index c0ef40ae99a7..032619ad0e73 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
@@ -728,6 +728,20 @@ static const struct pinctrl_pin_desc uniphier_pxs2_pins[] = {
234, UNIPHIER_PIN_PULL_DOWN),
};
+static const unsigned ain1_pins[] = {161, 162, 173, 174};
+static const int ain1_muxvals[] = {8, 8, 8, 8};
+static const unsigned ain2_pins[] = {98, 99, 100, 101, 102, 103, 104};
+static const int ain2_muxvals[] = {8, 8, 8, 8, 8, 8, 8};
+static const unsigned ainiec1_pins[] = {91};
+static const int ainiec1_muxvals[] = {11};
+static const unsigned aout2_pins[] = {175, 176, 177, 178, 183, 184, 185};
+static const int aout2_muxvals[] = {8, 8, 8, 8, 9, 9, 9};
+static const unsigned aout3_pins[] = {105, 106, 107, 108};
+static const int aout3_muxvals[] = {8, 8, 8, 8};
+static const unsigned aoutiec1_pins[] = {95};
+static const int aoutiec1_muxvals[] = {11};
+static const unsigned aoutiec2_pins[] = {97};
+static const int aoutiec2_muxvals[] = {8};
static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
static const int emmc_muxvals[] = {9, 9, 9, 9, 9, 9, 9};
static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
@@ -774,6 +788,8 @@ static const unsigned uart0_pins[] = {217, 218};
static const int uart0_muxvals[] = {8, 8};
static const unsigned uart0b_pins[] = {179, 180};
static const int uart0b_muxvals[] = {10, 10};
+static const unsigned uart0b_ctsrts_pins[] = {176, 177, 178, 183, 184, 185};
+static const int uart0b_ctsrts_muxvals[] = {10, 10, 10, 10, 10, 10};
static const unsigned uart1_pins[] = {115, 116};
static const int uart1_muxvals[] = {8, 8};
static const unsigned uart2_pins[] = {113, 114};
@@ -824,6 +840,13 @@ static const unsigned int gpio_range1_pins[] = {
};
static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(ain1),
+ UNIPHIER_PINCTRL_GROUP(ain2),
+ UNIPHIER_PINCTRL_GROUP(ainiec1),
+ UNIPHIER_PINCTRL_GROUP(aout2),
+ UNIPHIER_PINCTRL_GROUP(aout3),
+ UNIPHIER_PINCTRL_GROUP(aoutiec1),
+ UNIPHIER_PINCTRL_GROUP(aoutiec2),
UNIPHIER_PINCTRL_GROUP(emmc),
UNIPHIER_PINCTRL_GROUP(emmc_dat8),
UNIPHIER_PINCTRL_GROUP(ether_mii),
@@ -842,6 +865,7 @@ static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = {
UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
UNIPHIER_PINCTRL_GROUP(uart0),
UNIPHIER_PINCTRL_GROUP(uart0b),
+ UNIPHIER_PINCTRL_GROUP(uart0b_ctsrts),
UNIPHIER_PINCTRL_GROUP(uart1),
UNIPHIER_PINCTRL_GROUP(uart2),
UNIPHIER_PINCTRL_GROUP(uart3),
@@ -854,6 +878,13 @@ static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = {
UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range1),
};
+static const char * const ain1_groups[] = {"ain1"};
+static const char * const ain2_groups[] = {"ain2"};
+static const char * const ainiec1_groups[] = {"ainiec1"};
+static const char * const aout2_groups[] = {"aout2"};
+static const char * const aout3_groups[] = {"aout3"};
+static const char * const aoutiec1_groups[] = {"aoutiec1"};
+static const char * const aoutiec2_groups[] = {"aoutiec2"};
static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
static const char * const ether_mii_groups[] = {"ether_mii"};
static const char * const ether_rgmii_groups[] = {"ether_rgmii"};
@@ -868,7 +899,7 @@ static const char * const nand_groups[] = {"nand", "nand_cs1"};
static const char * const sd_groups[] = {"sd"};
static const char * const system_bus_groups[] = {"system_bus",
"system_bus_cs1"};
-static const char * const uart0_groups[] = {"uart0", "uart0b"};
+static const char * const uart0_groups[] = {"uart0", "uart0b", "uart0b_ctsrts"};
static const char * const uart1_groups[] = {"uart1"};
static const char * const uart2_groups[] = {"uart2"};
static const char * const uart3_groups[] = {"uart3", "uart3b"};
@@ -878,6 +909,13 @@ static const char * const usb2_groups[] = {"usb2"};
static const char * const usb3_groups[] = {"usb3"};
static const struct uniphier_pinmux_function uniphier_pxs2_functions[] = {
+ UNIPHIER_PINMUX_FUNCTION(ain1),
+ UNIPHIER_PINMUX_FUNCTION(ain2),
+ UNIPHIER_PINMUX_FUNCTION(ainiec1),
+ UNIPHIER_PINMUX_FUNCTION(aout2),
+ UNIPHIER_PINMUX_FUNCTION(aout3),
+ UNIPHIER_PINMUX_FUNCTION(aoutiec1),
+ UNIPHIER_PINMUX_FUNCTION(aoutiec2),
UNIPHIER_PINMUX_FUNCTION(emmc),
UNIPHIER_PINMUX_FUNCTION(ether_mii),
UNIPHIER_PINMUX_FUNCTION(ether_rgmii),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c
index dbe94a9a0353..535bb2e935e4 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c
@@ -816,6 +816,8 @@ static const unsigned int system_bus_cs1_pins[] = {15};
static const int system_bus_cs1_muxvals[] = {0};
static const unsigned int uart0_pins[] = {92, 93};
static const int uart0_muxvals[] = {0, 0};
+static const unsigned int uart0_ctsrts_pins[] = {243, 244, 245, 246, 247, 248};
+static const int uart0_ctsrts_muxvals[] = {3, 3, 3, 3, 3, 3};
static const unsigned int uart1_pins[] = {94, 95};
static const int uart1_muxvals[] = {0, 0};
static const unsigned int uart2_pins[] = {96, 97};
@@ -887,6 +889,7 @@ static const struct uniphier_pinctrl_group uniphier_pxs3_groups[] = {
UNIPHIER_PINCTRL_GROUP(system_bus),
UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart0_ctsrts),
UNIPHIER_PINCTRL_GROUP(uart1),
UNIPHIER_PINCTRL_GROUP(uart2),
UNIPHIER_PINCTRL_GROUP(uart3),
@@ -912,7 +915,7 @@ static const char * const nand_groups[] = {"nand"};
static const char * const sd_groups[] = {"sd"};
static const char * const system_bus_groups[] = {"system_bus",
"system_bus_cs1"};
-static const char * const uart0_groups[] = {"uart0"};
+static const char * const uart0_groups[] = {"uart0", "uart0_ctsrts"};
static const char * const uart1_groups[] = {"uart1"};
static const char * const uart2_groups[] = {"uart2"};
static const char * const uart3_groups[] = {"uart3"};
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
index 1af430d701be..0f921a653164 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
@@ -520,6 +520,8 @@ static const unsigned system_bus_cs5_pins[] = {13};
static const int system_bus_cs5_muxvals[] = {1};
static const unsigned uart0_pins[] = {70, 71};
static const int uart0_muxvals[] = {3, 3};
+static const unsigned uart0_ctsrts_pins[] = {72, 73, 74};
+static const int uart0_ctsrts_muxvals[] = {3, 3, 3};
static const unsigned uart1_pins[] = {114, 115};
static const int uart1_muxvals[] = {0, 0};
static const unsigned uart2_pins[] = {112, 113};
@@ -575,6 +577,7 @@ static const struct uniphier_pinctrl_group uniphier_sld8_groups[] = {
UNIPHIER_PINCTRL_GROUP(system_bus_cs4),
UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart0_ctsrts),
UNIPHIER_PINCTRL_GROUP(uart1),
UNIPHIER_PINCTRL_GROUP(uart2),
UNIPHIER_PINCTRL_GROUP(uart3),
@@ -601,7 +604,7 @@ static const char * const system_bus_groups[] = {"system_bus",
"system_bus_cs3",
"system_bus_cs4",
"system_bus_cs5"};
-static const char * const uart0_groups[] = {"uart0"};
+static const char * const uart0_groups[] = {"uart0", "uart0_ctsrts"};
static const char * const uart1_groups[] = {"uart1"};
static const char * const uart2_groups[] = {"uart2"};
static const char * const uart3_groups[] = {"uart3"};