Merge tag 'pinctrl-v5.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "It is pretty calm and chill in pin control for the moment. Just
  incremental development.

  There is an odd patch to the Super-H architecture, it's coming from
  the maintainers so should be fine.

  Summary:

  New drivers:
   - Bitmain BM1880 pin controller
   - Mediatek MT8516
   - Cirrus Logich Lochnagar PMIC pins

  Updates:
   - Incremental development on Renesas SH-PFC
   - Incremental development on Intel pin controller and some particular
     updates for Cedarfork.
   - Pin configuration support in Allwinner SunXi drivers
   - Suspend/resume support in the NXP/Freescale i.MX8MQ driver
   - Support for more packaging of the ST Micro STM32"

* tag 'pinctrl-v5.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits)
  pinctrl: mcp23s08: Do not complain about unsupported params
  pinctrl: Rework Kconfig dependency for BM1880 pinctrl driver
  MAINTAINERS: Add entry for BM1880 pinctrl
  pinctrl: Add pinctrl support for BM1880 SoC
  dt-bindings: pinctrl: Add BM1880 pinctrl binding
  pinctrl: stm32: check irq controller availability at probe
  pinctrl: mediatek: Add MT8516 Pinctrl driver
  pinctrl: zte: fix leaked of_node references
  pinctrl: intel: Increase readability of intel_gpio_update_pad_mode()
  pinctrl: intel: Retain HOSTSW_OWN for requested gpio pin
  pinctrl: pistachio: fix leaked of_node references
  pinctrl: sunxi: Support I/O bias voltage setting on H6
  pinctrl: sunxi: Prepare for alternative bias voltage setting methods
  pinctrl: st: fix leaked of_node references
  pinctrl: samsung: fix leaked of_node references
  pinctrl: stm32: align stm32mp157 pin names
  pinctrl: stm32: add package information for stm32mp157c
  pinctrl: stm32: introduce package support
  dt-bindings: pinctrl: stm32: add new entry for package information
  pinctrl: imx8mq: Add suspend/resume ops
  ...

1 files changed, 17 insertions, 1 deletions

diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
index ee15ab067b5f..44e30deeee38 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
@@ -95,6 +95,22 @@
 #define PINCTRL_SUN7I_A20	BIT(7)
 #define PINCTRL_SUN8I_R40	BIT(8)
 
+#define PIO_POW_MOD_SEL_REG	0x340
+
+enum sunxi_desc_bias_voltage {
+	BIAS_VOLTAGE_NONE,
+	/*
+	 * Bias voltage configuration is done through
+	 * Pn_GRP_CONFIG registers, as seen on A80 SoC.
+	 */
+	BIAS_VOLTAGE_GRP_CONFIG,
+	/*
+	 * Bias voltage is set through PIO_POW_MOD_SEL_REG
+	 * register, as seen on H6 SoC, for example.
+	 */
+	BIAS_VOLTAGE_PIO_POW_MODE_SEL,
+};
+
 struct sunxi_desc_function {
 	unsigned long	variant;
 	const char	*name;
@@ -117,7 +133,7 @@ struct sunxi_pinctrl_desc {
 	const unsigned int		*irq_bank_map;
 	bool				irq_read_needs_mux;
 	bool				disable_strict_mode;
-	bool				has_io_bias_cfg;
+	enum sunxi_desc_bias_voltage	io_bias_cfg_variant;
 };
 
 struct sunxi_pinctrl_function {