diff options
| author | Icenowy Zheng <icenowy@aosc.io> | 2018-03-16 22:02:09 +0800 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2018-03-27 15:07:49 +0200 |
| commit | 35817d34bd07b4e1cd597e054fa2bd9c9c111aab (patch) | |
| tree | 4e0c17938c4a90cff2b3f1dbe127d5760629b7d8 /drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c | |
| parent | 29dfc6bbcc5e1ef7ce1008c4713387efb8f567d2 (diff) | |
| download | linux-35817d34bd07b4e1cd597e054fa2bd9c9c111aab.tar.bz2 | |
pinctrl: sunxi: change irq_bank_base to irq_bank_map
The Allwinner H6 SoC have its pin controllers with the first IRQ-capable
GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5.
Change the current code that uses IRQ bank base to a IRQ bank map, in
order to support the case that holes exist among IRQ banks.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c')
| -rw-r--r-- | drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c index 496ba34e1f5f..6704ce8e5e3d 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c @@ -293,11 +293,13 @@ static const struct sunxi_desc_pin sun8i_v3s_pins[] = { SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */ }; +static const unsigned int sun8i_v3s_pinctrl_irq_bank_map[] = { 1, 2 }; + static const struct sunxi_pinctrl_desc sun8i_v3s_pinctrl_data = { .pins = sun8i_v3s_pins, .npins = ARRAY_SIZE(sun8i_v3s_pins), .irq_banks = 2, - .irq_bank_base = 1, + .irq_bank_map = sun8i_v3s_pinctrl_irq_bank_map, .irq_read_needs_mux = true }; |