diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-04-13 19:23:47 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-05-05 12:02:26 +0200 |
| commit | ade1ef9904ecd81fcda302abfd81e1aaccb238a7 (patch) | |
| tree | 0b5672eca5af4f4375d01634ed31c1c7cb46dcad /drivers/pinctrl/renesas | |
| parent | 72ee7f9b6fd34076a8c6d443450b9f1e5208e3fc (diff) | |
| download | linux-ade1ef9904ecd81fcda302abfd81e1aaccb238a7.tar.bz2 | |
pinctrl: renesas: r8a77470: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 70 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/c5183fcb3dd417d57ced0f60d091e2c7d37e1c8c.1649865241.git.geert+renesas@glider.be
Diffstat (limited to 'drivers/pinctrl/renesas')
| -rw-r--r-- | drivers/pinctrl/renesas/pfc-r8a77470.c | 56 |
1 files changed, 20 insertions, 36 deletions
diff --git a/drivers/pinctrl/renesas/pfc-r8a77470.c b/drivers/pinctrl/renesas/pfc-r8a77470.c index 15a6dffdffcf..b5725c3ed2b6 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77470.c +++ b/drivers/pinctrl/renesas/pfc-r8a77470.c @@ -2485,16 +2485,11 @@ static const struct sh_pfc_function pinmux_functions[] = { }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { - { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR0", 0xE6060004, 32, + GROUP(-9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP0_31_23 RESERVED */ GP_0_22_FN, FN_MMC0_D7, GP_0_21_FN, FN_MMC0_D6, GP_0_20_FN, FN_IP1_7_4, @@ -2519,16 +2514,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_1_FN, FN_USB0_OVC, GP_0_0_FN, FN_USB0_PWEN, )) }, - { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR1", 0xE6060008, 32, + GROUP(-9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP1_31_23 RESERVED */ GP_1_22_FN, FN_IP4_3_0, GP_1_21_FN, FN_IP3_31_28, GP_1_20_FN, FN_IP3_27_24, @@ -2587,22 +2577,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_1_FN, FN_IP4_11_8, GP_2_0_FN, FN_IP4_7_4, )) }, - { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP( - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR3", 0xE6060010, 32, + GROUP(-2, 1, 1, -10, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP3_31_30 RESERVED */ GP_3_29_FN, FN_IP10_19_16, GP_3_28_FN, FN_IP10_15_12, GP_3_27_FN, FN_IP10_11_8, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + /* GP3_26_17 RESERVED */ GP_3_16_FN, FN_IP10_7_4, GP_3_15_FN, FN_IP10_3_0, GP_3_14_FN, FN_IP9_31_28, @@ -3139,9 +3122,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SSI_SDATA4_A, 0, FN_AVB_CRS, 0, 0, 0, FN_VI0_R6, 0, 0, 0, 0, 0, 0, 0, 0, 0, )) }, - { PINMUX_CFG_REG("IPSR17", 0xE6060084, 32, 4, GROUP( - /* IP17_31_28 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060084, 32, + GROUP(-4, 4, 4, 4, 4, 4, 4, 4), + GROUP( + /* IP17_31_28 [4] RESERVED */ /* IP17_27_24 [4] */ FN_AUDIO_CLKOUT_A, FN_SDA4_B, 0, 0, 0, 0, FN_VI0_VSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, |