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author | Linus Walleij <linus.walleij@linaro.org> | 2018-10-01 13:20:45 +0200 |
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committer | Linus Walleij <linus.walleij@linaro.org> | 2018-10-01 13:20:45 +0200 |
commit | 30aa69e7bd9f7af3574120249eecb3726dcaf737 (patch) | |
tree | b4a9ec1374ec9aed1022fdb32802c483952e5a97 /drivers/pinctrl/qcom | |
parent | 63e037bc51b32d414cd07dd700e71359ce27a11f (diff) | |
parent | 17b57b1883c1285f3d0dc2266e8f79286a7bef38 (diff) | |
download | linux-30aa69e7bd9f7af3574120249eecb3726dcaf737.tar.bz2 |
Merge tag 'v4.19-rc6' into devel
This is the 4.19-rc6 release
I needed to merge this in because of extensive conflicts in
the MSM and Intel pin control drivers. I know how to resolve
them, so let's do it like this.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/qcom')
-rw-r--r-- | drivers/pinctrl/qcom/pinctrl-msm.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 6f02bbdb0865..0726c8a09065 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -669,6 +669,29 @@ static void msm_gpio_irq_mask(struct irq_data *d) raw_spin_lock_irqsave(&pctrl->lock, flags); val = msm_readl_intr_cfg(pctrl, g); + /* + * There are two bits that control interrupt forwarding to the CPU. The + * RAW_STATUS_EN bit causes the level or edge sensed on the line to be + * latched into the interrupt status register when the hardware detects + * an irq that it's configured for (either edge for edge type or level + * for level type irq). The 'non-raw' status enable bit causes the + * hardware to assert the summary interrupt to the CPU if the latched + * status bit is set. There's a bug though, the edge detection logic + * seems to have a problem where toggling the RAW_STATUS_EN bit may + * cause the status bit to latch spuriously when there isn't any edge + * so we can't touch that bit for edge type irqs and we have to keep + * the bit set anyway so that edges are latched while the line is masked. + * + * To make matters more complicated, leaving the RAW_STATUS_EN bit + * enabled all the time causes level interrupts to re-latch into the + * status register because the level is still present on the line after + * we ack it. We clear the raw status enable bit during mask here and + * set the bit on unmask so the interrupt can't latch into the hardware + * while it's masked. + */ + if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK) + val &= ~BIT(g->intr_raw_status_bit); + val &= ~BIT(g->intr_enable_bit); msm_writel_intr_cfg(val, pctrl, g); @@ -690,6 +713,7 @@ static void msm_gpio_irq_unmask(struct irq_data *d) raw_spin_lock_irqsave(&pctrl->lock, flags); val = msm_readl_intr_cfg(pctrl, g); + val |= BIT(g->intr_raw_status_bit); val |= BIT(g->intr_enable_bit); msm_writel_intr_cfg(val, pctrl, g); |