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authorSean Wang <sean.wang@mediatek.com>2018-09-08 19:07:38 +0800
committerLinus Walleij <linus.walleij@linaro.org>2018-09-18 14:53:42 -0700
commit6561859b067fcd6c5b89fd625b2c7dc324b706b5 (patch)
tree8a9ac55237bdf531704c65e86c247221d43031a2 /drivers/pinctrl/mediatek
parent89132dd8ffd2218fad3f53a9ca529e609237448a (diff)
downloadlinux-6561859b067fcd6c5b89fd625b2c7dc324b706b5.tar.bz2
pinctrl: mediatek: add eint support to MT8183 pinctrl driver
Just add eint support to MT8183 pinctrl driver as usual as happens on the other SoCs. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/mediatek')
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mt8183.c8
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-paris.c22
2 files changed, 30 insertions, 0 deletions
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8183.c b/drivers/pinctrl/mediatek/pinctrl-mt8183.c
index 9d5aa277911c..6262fd3678ea 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8183.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8183.c
@@ -492,11 +492,19 @@ static const char * const mt8183_pinctrl_register_base_names[] = {
"iocfg6", "iocfg7", "iocfg8",
};
+static const struct mtk_eint_hw mt8183_eint_hw = {
+ .port_mask = 7,
+ .ports = 6,
+ .ap_num = 212,
+ .db_cnt = 13,
+};
+
static const struct mtk_pin_soc mt8183_data = {
.reg_cal = mt8183_reg_cals,
.pins = mtk_pins_mt8183,
.npins = ARRAY_SIZE(mtk_pins_mt8183),
.ngrps = ARRAY_SIZE(mtk_pins_mt8183),
+ .eint_hw = &mt8183_eint_hw,
.gpio_m = 0,
.ies_present = true,
.base_names = mt8183_pinctrl_register_base_names,
diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c
index 50d689371590..9f4224f9d605 100644
--- a/drivers/pinctrl/mediatek/pinctrl-paris.c
+++ b/drivers/pinctrl/mediatek/pinctrl-paris.c
@@ -718,6 +718,22 @@ static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
return pinctrl_gpio_direction_output(chip->base + gpio);
}
+static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
+{
+ struct mtk_pinctrl *hw = gpiochip_get_data(chip);
+ const struct mtk_pin_desc *desc;
+
+ if (!hw->eint)
+ return -ENOTSUPP;
+
+ desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
+
+ if (desc->eint.eint_n == EINT_NA)
+ return -ENOTSUPP;
+
+ return mtk_eint_find_irq(hw->eint, desc->eint.eint_n);
+}
+
static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
unsigned long config)
{
@@ -751,6 +767,7 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
chip->direction_output = mtk_gpio_direction_output;
chip->get = mtk_gpio_get;
chip->set = mtk_gpio_set;
+ chip->to_irq = mtk_gpio_to_irq,
chip->set_config = mtk_gpio_set_config,
chip->base = -1;
chip->ngpio = hw->soc->npins;
@@ -871,6 +888,11 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev,
if (err)
return err;
+ err = mtk_build_eint(hw, pdev);
+ if (err)
+ dev_warn(&pdev->dev,
+ "Failed to add EINT, but pinctrl still can work\n");
+
/* Build gpiochip should be after pinctrl_enable is done */
err = mtk_build_gpiochip(hw, pdev->dev.of_node);
if (err) {