diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2020-12-16 15:02:49 -0800 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2020-12-16 15:02:49 -0800 |
commit | f68e4041ef63f03091e44b4eebf1ab5c5d427e6f (patch) | |
tree | 9ff864e69caf508408f98fefedb15a5098910587 /drivers/pinctrl/intel | |
parent | a701262c02cec71dc29b10fe910ba3c2298f5ba3 (diff) | |
parent | 3df09cb8c92e2bdfb78c81f678f6990bd780f09a (diff) | |
download | linux-f68e4041ef63f03091e44b4eebf1ab5c5d427e6f.tar.bz2 |
Merge tag 'pinctrl-v5.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v5.11 kernel.
Drivers, drivers and drivers. Not a single core change.
Some new stuff, especially a bunch of new Intel, Qualcomm and Ocelot
SoCs.
As part of the modularization attempt, I applied one patch affecting
the firmware subsystem as a functional (not syntactic/semantic)
dependency and then it blew up in our face, so I had to revert it,
bummer. It will come in later, through that subsystem, I guess.
New drivers:
- New driver for the Microchip Serial GPIO "SGPIO".
- Qualcomm SM8250 LPASS (Low Power Audio Subsystem) GPIO driver.
New subdrivers:
- Intel Lakefield subdriver.
- Intel Elkhart Lake subdriver.
- Intel Alder Lake-S subdriver.
- Qualcomm MSM8953 subdriver.
- Qualcomm SDX55 subdriver.
- Qualcomm SDX55 PMIC subdriver.
- Ocelot Luton SoC subdriver.
- Ocelot Serval SoC subdriver.
Modularization:
- The Meson driver can now be built as modules.
- The Qualcomm driver(s) can now be built as modules.
Incremental improvements:
- The Intel driver now supports pin configuration for GPIO-related
configurations.
- A bunch of Renesas PFC drivers have been augmented with support for
QSPI pins, groups and functions.
- Non-critical fixes to the irq handling in the Allwinner Sunxi
driver"
* tag 'pinctrl-v5.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (80 commits)
pinctrl/spear: simplify the return expression of spear300_pinctrl_probe()
pinctrl: mediatek: simplify the return expression of mtk_pinconf_bias_disable_set_rev1()
dt-bindings: pinctrl: pinctrl-microchip-sgpio: Add irq support
pinctrl: pinctrl-microchip-sgpio: Add irq support (for sparx5)
pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver
dt-bindings: pinctrl: qcom: Add sm8250 lpass lpi pinctrl bindings
pinctrl: qcom-pmic-gpio: Add support for pmx55
dt-bindings: pinctrl: qcom-pmic-gpio: Add pmx55 support
pinctrl: pinctrl-microchip-sgpio: Mark some symbols with static keyword
pinctrl: at91-pio4: Make PINCTRL_AT91PIO4 depend on HAS_IOMEM to fix build error
pinctrl: mtk: Fix low level output voltage issue
pinctrl: falcon: add missing put_device() call in pinctrl_falcon_probe()
pinctrl: actions: pinctrl-s500: Constify s500_padinfo[]
pinctrl: pinctrl-microchip-sgpio: Add OF config dependency
pinctrl: pinctrl-microchip-sgpio: Add pinctrl driver for Microsemi Serial GPIO
dt-bindings: pinctrl: Add bindings for pinctrl-microchip-sgpio driver
pinctrl: at91-pio4: add support for fewer lines on last PIO bank
pinctrl: sunxi: Always call chained_irq_{enter, exit} in sunxi_pinctrl_irq_handler
pinctrl: sunxi: Mark the irq bank not found in sunxi_pinctrl_irq_handler() with WARN_ON
pinctrl: sunxi: fix irq bank map for the Allwinner A100 pin controller
...
Diffstat (limited to 'drivers/pinctrl/intel')
-rw-r--r-- | drivers/pinctrl/intel/Kconfig | 25 | ||||
-rw-r--r-- | drivers/pinctrl/intel/Makefile | 3 | ||||
-rw-r--r-- | drivers/pinctrl/intel/pinctrl-alderlake.c | 437 | ||||
-rw-r--r-- | drivers/pinctrl/intel/pinctrl-elkhartlake.c | 513 | ||||
-rw-r--r-- | drivers/pinctrl/intel/pinctrl-lakefield.c | 375 | ||||
-rw-r--r-- | drivers/pinctrl/intel/pinctrl-lynxpoint.c | 10 |
6 files changed, 1359 insertions, 4 deletions
diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index 28e5f824ba45..fb1495bd77c4 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -55,6 +55,14 @@ config PINCTRL_INTEL select GPIOLIB select GPIOLIB_IRQCHIP +config PINCTRL_ALDERLAKE + tristate "Intel Alder Lake pinctrl and GPIO driver" + depends on ACPI + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + of Intel Alder Lake PCH pins and using them as GPIOs. + config PINCTRL_BROXTON tristate "Intel Broxton pinctrl and GPIO driver" depends on ACPI @@ -87,6 +95,14 @@ config PINCTRL_DENVERTON This pinctrl driver provides an interface that allows configuring of Intel Denverton SoC pins and using them as GPIOs. +config PINCTRL_ELKHARTLAKE + tristate "Intel Elkhart Lake SoC pinctrl and GPIO driver" + depends on ACPI + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + of Intel Elkhart Lake SoC pins and using them as GPIOs. + config PINCTRL_EMMITSBURG tristate "Intel Emmitsburg pinctrl and GPIO driver" depends on ACPI @@ -119,6 +135,14 @@ config PINCTRL_JASPERLAKE This pinctrl driver provides an interface that allows configuring of Intel Jasper Lake PCH pins and using them as GPIOs. +config PINCTRL_LAKEFIELD + tristate "Intel Lakefield SoC pinctrl and GPIO driver" + depends on ACPI + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + of Intel Lakefield SoC pins and using them as GPIOs. + config PINCTRL_LEWISBURG tristate "Intel Lewisburg pinctrl and GPIO driver" depends on ACPI @@ -143,4 +167,5 @@ config PINCTRL_TIGERLAKE help This pinctrl driver provides an interface that allows configuring of Intel Tiger Lake PCH pins and using them as GPIOs. + endif diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile index 1c1c316f98b9..181ffcf34d62 100644 --- a/drivers/pinctrl/intel/Makefile +++ b/drivers/pinctrl/intel/Makefile @@ -6,14 +6,17 @@ obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o obj-$(CONFIG_PINCTRL_LYNXPOINT) += pinctrl-lynxpoint.o obj-$(CONFIG_PINCTRL_MERRIFIELD) += pinctrl-merrifield.o obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o +obj-$(CONFIG_PINCTRL_ALDERLAKE) += pinctrl-alderlake.o obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o obj-$(CONFIG_PINCTRL_CANNONLAKE) += pinctrl-cannonlake.o obj-$(CONFIG_PINCTRL_CEDARFORK) += pinctrl-cedarfork.o obj-$(CONFIG_PINCTRL_DENVERTON) += pinctrl-denverton.o +obj-$(CONFIG_PINCTRL_ELKHARTLAKE) += pinctrl-elkhartlake.o obj-$(CONFIG_PINCTRL_EMMITSBURG) += pinctrl-emmitsburg.o obj-$(CONFIG_PINCTRL_GEMINILAKE) += pinctrl-geminilake.o obj-$(CONFIG_PINCTRL_ICELAKE) += pinctrl-icelake.o obj-$(CONFIG_PINCTRL_JASPERLAKE) += pinctrl-jasperlake.o +obj-$(CONFIG_PINCTRL_LAKEFIELD) += pinctrl-lakefield.o obj-$(CONFIG_PINCTRL_LEWISBURG) += pinctrl-lewisburg.o obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o obj-$(CONFIG_PINCTRL_TIGERLAKE) += pinctrl-tigerlake.o diff --git a/drivers/pinctrl/intel/pinctrl-alderlake.c b/drivers/pinctrl/intel/pinctrl-alderlake.c new file mode 100644 index 000000000000..efb664f12b5d --- /dev/null +++ b/drivers/pinctrl/intel/pinctrl-alderlake.c @@ -0,0 +1,437 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Intel Alder Lake PCH pinctrl/GPIO driver + * + * Copyright (C) 2020, Intel Corporation + * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> + */ + +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/platform_device.h> + +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-intel.h" + +#define ADL_PAD_OWN 0x0a0 +#define ADL_PADCFGLOCK 0x110 +#define ADL_HOSTSW_OWN 0x150 +#define ADL_GPI_IS 0x200 +#define ADL_GPI_IE 0x220 + +#define ADL_GPP(r, s, e, g) \ + { \ + .reg_num = (r), \ + .base = (s), \ + .size = ((e) - (s) + 1), \ + .gpio_base = (g), \ + } + +#define ADL_COMMUNITY(b, s, e, g) \ + { \ + .barno = (b), \ + .padown_offset = ADL_PAD_OWN, \ + .padcfglock_offset = ADL_PADCFGLOCK, \ + .hostown_offset = ADL_HOSTSW_OWN, \ + .is_offset = ADL_GPI_IS, \ + .ie_offset = ADL_GPI_IE, \ + .pin_base = (s), \ + .npins = ((e) - (s) + 1), \ + .gpps = (g), \ + .ngpps = ARRAY_SIZE(g), \ + } + +/* Alder Lake-S */ +static const struct pinctrl_pin_desc adls_pins[] = { + /* GPP_I */ + PINCTRL_PIN(0, "EXT_PWR_GATEB"), + PINCTRL_PIN(1, "DDSP_HPD_1"), + PINCTRL_PIN(2, "DDSP_HPD_2"), + PINCTRL_PIN(3, "DDSP_HPD_3"), + PINCTRL_PIN(4, "DDSP_HPD_4"), + PINCTRL_PIN(5, "DDPB_CTRLCLK"), + PINCTRL_PIN(6, "DDPB_CTRLDATA"), + PINCTRL_PIN(7, "DDPC_CTRLCLK"), + PINCTRL_PIN(8, "DDPC_CTRLDATA"), + PINCTRL_PIN(9, "GSPI0_CS1B"), + PINCTRL_PIN(10, "GSPI1_CS1B"), + PINCTRL_PIN(11, "USB2_OCB_4"), + PINCTRL_PIN(12, "USB2_OCB_5"), + PINCTRL_PIN(13, "USB2_OCB_6"), + PINCTRL_PIN(14, "USB2_OCB_7"), + PINCTRL_PIN(15, "GSPI0_CS0B"), + PINCTRL_PIN(16, "GSPI0_CLK"), + PINCTRL_PIN(17, "GSPI0_MISO"), + PINCTRL_PIN(18, "GSPI0_MOSI"), + PINCTRL_PIN(19, "GSPI1_CS0B"), + PINCTRL_PIN(20, "GSPI1_CLK"), + PINCTRL_PIN(21, "GSPI1_MISO"), + PINCTRL_PIN(22, "GSPI1_MOSI"), + PINCTRL_PIN(23, "GSPI0_CLK_LOOPBK"), + PINCTRL_PIN(24, "GSPI1_CLK_LOOPBK"), + /* GPP_R */ + PINCTRL_PIN(25, "HDA_BCLK"), + PINCTRL_PIN(26, "HDA_SYNC"), + PINCTRL_PIN(27, "HDA_SDO"), + PINCTRL_PIN(28, "HDA_SDI_0"), + PINCTRL_PIN(29, "HDA_RSTB"), + PINCTRL_PIN(30, "HDA_SDI_1"), + PINCTRL_PIN(31, "GPP_R_6"), + PINCTRL_PIN(32, "GPP_R_7"), + PINCTRL_PIN(33, "GPP_R_8"), + PINCTRL_PIN(34, "DDSP_HPD_A"), + PINCTRL_PIN(35, "DDSP_HPD_B"), + PINCTRL_PIN(36, "DDSP_HPD_C"), + PINCTRL_PIN(37, "ISH_SPI_CSB"), + PINCTRL_PIN(38, "ISH_SPI_CLK"), + PINCTRL_PIN(39, "ISH_SPI_MISO"), + PINCTRL_PIN(40, "ISH_SPI_MOSI"), + PINCTRL_PIN(41, "DDP1_CTRLCLK"), + PINCTRL_PIN(42, "DDP1_CTRLDATA"), + PINCTRL_PIN(43, "DDP2_CTRLCLK"), + PINCTRL_PIN(44, "DDP2_CTRLDATA"), + PINCTRL_PIN(45, "DDPA_CTRLCLK"), + PINCTRL_PIN(46, "DDPA_CTRLDATA"), + PINCTRL_PIN(47, "GSPI2_CLK_LOOPBK"), + /* GPP_J */ + PINCTRL_PIN(48, "CNV_PA_BLANKING"), + PINCTRL_PIN(49, "CPU_C10_GATEB"), + PINCTRL_PIN(50, "CNV_BRI_DT"), + PINCTRL_PIN(51, "CNV_BRI_RSP"), + PINCTRL_PIN(52, "CNV_RGI_DT"), + PINCTRL_PIN(53, "CNV_RGI_RSP"), + PINCTRL_PIN(54, "CNV_MFUART2_RXD"), + PINCTRL_PIN(55, "CNV_MFUART2_TXD"), + PINCTRL_PIN(56, "SRCCLKREQB_16"), + PINCTRL_PIN(57, "SRCCLKREQB_17"), + PINCTRL_PIN(58, "BSSB_LS_RX"), + PINCTRL_PIN(59, "BSSB_LS_TX"), + /* vGPIO */ + PINCTRL_PIN(60, "CNV_BTEN"), + PINCTRL_PIN(61, "CNV_BT_HOST_WAKEB"), + PINCTRL_PIN(62, "CNV_BT_IF_SELECT"), + PINCTRL_PIN(63, "vCNV_BT_UART_TXD"), + PINCTRL_PIN(64, "vCNV_BT_UART_RXD"), + PINCTRL_PIN(65, "vCNV_BT_UART_CTS_B"), + PINCTRL_PIN(66, "vCNV_BT_UART_RTS_B"), + PINCTRL_PIN(67, "vCNV_MFUART1_TXD"), + PINCTRL_PIN(68, "vCNV_MFUART1_RXD"), + PINCTRL_PIN(69, "vCNV_MFUART1_CTS_B"), + PINCTRL_PIN(70, "vCNV_MFUART1_RTS_B"), + PINCTRL_PIN(71, "vUART0_TXD"), + PINCTRL_PIN(72, "vUART0_RXD"), + PINCTRL_PIN(73, "vUART0_CTS_B"), + PINCTRL_PIN(74, "vUART0_RTS_B"), + PINCTRL_PIN(75, "vISH_UART0_TXD"), + PINCTRL_PIN(76, "vISH_UART0_RXD"), + PINCTRL_PIN(77, "vISH_UART0_CTS_B"), + PINCTRL_PIN(78, "vISH_UART0_RTS_B"), + PINCTRL_PIN(79, "vCNV_BT_I2S_BCLK"), + PINCTRL_PIN(80, "vCNV_BT_I2S_WS_SYNC"), + PINCTRL_PIN(81, "vCNV_BT_I2S_SDO"), + PINCTRL_PIN(82, "vCNV_BT_I2S_SDI"), + PINCTRL_PIN(83, "vI2S2_SCLK"), + PINCTRL_PIN(84, "vI2S2_SFRM"), + PINCTRL_PIN(85, "vI2S2_TXD"), + PINCTRL_PIN(86, "vI2S2_RXD"), + /* vGPIO_0 */ + PINCTRL_PIN(87, "ESPI_USB_OCB_0"), + PINCTRL_PIN(88, "ESPI_USB_OCB_1"), + PINCTRL_PIN(89, "ESPI_USB_OCB_2"), + PINCTRL_PIN(90, "ESPI_USB_OCB_3"), + PINCTRL_PIN(91, "USB_CPU_OCB_0"), + PINCTRL_PIN(92, "USB_CPU_OCB_1"), + PINCTRL_PIN(93, "USB_CPU_OCB_2"), + PINCTRL_PIN(94, "USB_CPU_OCB_3"), + /* GPP_B */ + PINCTRL_PIN(95, "PCIE_LNK_DOWN"), + PINCTRL_PIN(96, "ISH_UART0_RTSB"), + PINCTRL_PIN(97, "VRALERTB"), + PINCTRL_PIN(98, "CPU_GP_2"), + PINCTRL_PIN(99, "CPU_GP_3"), + PINCTRL_PIN(100, "SX_EXIT_HOLDOFFB"), + PINCTRL_PIN(101, "CLKOUT_48"), + PINCTRL_PIN(102, "ISH_GP_7"), + PINCTRL_PIN(103, "ISH_GP_0"), + PINCTRL_PIN(104, "ISH_GP_1"), + PINCTRL_PIN(105, "ISH_GP_2"), + PINCTRL_PIN(106, "I2S_MCLK"), + PINCTRL_PIN(107, "SLP_S0B"), + PINCTRL_PIN(108, "PLTRSTB"), + PINCTRL_PIN(109, "SPKR"), + PINCTRL_PIN(110, "ISH_GP_3"), + PINCTRL_PIN(111, "ISH_GP_4"), + PINCTRL_PIN(112, "ISH_GP_5"), + PINCTRL_PIN(113, "PMCALERTB"), + PINCTRL_PIN(114, "FUSA_DIAGTEST_EN"), + PINCTRL_PIN(115, "FUSA_DIAGTEST_MODE"), + PINCTRL_PIN(116, "GPP_B_21"), + PINCTRL_PIN(117, "GPP_B_22"), + PINCTRL_PIN(118, "SML1ALERTB"), + /* GPP_G */ + PINCTRL_PIN(119, "GPP_G_0"), + PINCTRL_PIN(120, "GPP_G_1"), + PINCTRL_PIN(121, "DNX_FORCE_RELOAD"), + PINCTRL_PIN(122, "GMII_MDC_0"), + PINCTRL_PIN(123, "GMII_MDIO_0"), + PINCTRL_PIN(124, "SLP_DRAMB"), + PINCTRL_PIN(125, "GPP_G_6"), + PINCTRL_PIN(126, "GPP_G_7"), + /* GPP_H */ + PINCTRL_PIN(127, "SRCCLKREQB_18"), + PINCTRL_PIN(128, "GPP_H_1"), + PINCTRL_PIN(129, "SRCCLKREQB_8"), + PINCTRL_PIN(130, "SRCCLKREQB_9"), + PINCTRL_PIN(131, "SRCCLKREQB_10"), + PINCTRL_PIN(132, "SRCCLKREQB_11"), + PINCTRL_PIN(133, "SRCCLKREQB_12"), + PINCTRL_PIN(134, "SRCCLKREQB_13"), + PINCTRL_PIN(135, "SRCCLKREQB_14"), + PINCTRL_PIN(136, "SRCCLKREQB_15"), + PINCTRL_PIN(137, "SML2CLK"), + PINCTRL_PIN(138, "SML2DATA"), + PINCTRL_PIN(139, "SML2ALERTB"), + PINCTRL_PIN(140, "SML3CLK"), + PINCTRL_PIN(141, "SML3DATA"), + PINCTRL_PIN(142, "SML3ALERTB"), + PINCTRL_PIN(143, "SML4CLK"), + PINCTRL_PIN(144, "SML4DATA"), + PINCTRL_PIN(145, "SML4ALERTB"), + PINCTRL_PIN(146, "ISH_I2C0_SDA"), + PINCTRL_PIN(147, "ISH_I2C0_SCL"), + PINCTRL_PIN(148, "ISH_I2C1_SDA"), + PINCTRL_PIN(149, "ISH_I2C1_SCL"), + PINCTRL_PIN(150, "TIME_SYNC_0"), + /* SPI0 */ + PINCTRL_PIN(151, "SPI0_IO_2"), + PINCTRL_PIN(152, "SPI0_IO_3"), + PINCTRL_PIN(153, "SPI0_MOSI_IO_0"), + PINCTRL_PIN(154, "SPI0_MISO_IO_1"), + PINCTRL_PIN(155, "SPI0_TPM_CSB"), + PINCTRL_PIN(156, "SPI0_FLASH_0_CSB"), + PINCTRL_PIN(157, "SPI0_FLASH_1_CSB"), + PINCTRL_PIN(158, "SPI0_CLK"), + PINCTRL_PIN(159, "SPI0_CLK_LOOPBK"), + /* GPP_A */ + PINCTRL_PIN(160, "ESPI_IO_0"), + PINCTRL_PIN(161, "ESPI_IO_1"), + PINCTRL_PIN(162, "ESPI_IO_2"), + PINCTRL_PIN(163, "ESPI_IO_3"), + PINCTRL_PIN(164, "ESPI_CS0B"), + PINCTRL_PIN(165, "ESPI_CLK"), + PINCTRL_PIN(166, "ESPI_RESETB"), + PINCTRL_PIN(167, "ESPI_CS1B"), + PINCTRL_PIN(168, "ESPI_CS2B"), + PINCTRL_PIN(169, "ESPI_CS3B"), + PINCTRL_PIN(170, "ESPI_ALERT0B"), + PINCTRL_PIN(171, "ESPI_ALERT1B"), + PINCTRL_PIN(172, "ESPI_ALERT2B"), + PINCTRL_PIN(173, "ESPI_ALERT3B"), + PINCTRL_PIN(174, "GPP_A_14"), + PINCTRL_PIN(175, "ESPI_CLK_LOOPBK"), + /* GPP_C */ + PINCTRL_PIN(176, "SMBCLK"), + PINCTRL_PIN(177, "SMBDATA"), + PINCTRL_PIN(178, "SMBALERTB"), + PINCTRL_PIN(179, "ISH_UART0_RXD"), + PINCTRL_PIN(180, "ISH_UART0_TXD"), + PINCTRL_PIN(181, "SML0ALERTB"), + PINCTRL_PIN(182, "ISH_I2C2_SDA"), + PINCTRL_PIN(183, "ISH_I2C2_SCL"), + PINCTRL_PIN(184, "UART0_RXD"), + PINCTRL_PIN(185, "UART0_TXD"), + PINCTRL_PIN(186, "UART0_RTSB"), + PINCTRL_PIN(187, "UART0_CTSB"), + PINCTRL_PIN(188, "UART1_RXD"), + PINCTRL_PIN(189, "UART1_TXD"), + PINCTRL_PIN(190, "UART1_RTSB"), + PINCTRL_PIN(191, "UART1_CTSB"), + PINCTRL_PIN(192, "I2C0_SDA"), + PINCTRL_PIN(193, "I2C0_SCL"), + PINCTRL_PIN(194, "I2C1_SDA"), + PINCTRL_PIN(195, "I2C1_SCL"), + PINCTRL_PIN(196, "UART2_RXD"), + PINCTRL_PIN(197, "UART2_TXD"), + PINCTRL_PIN(198, "UART2_RTSB"), + PINCTRL_PIN(199, "UART2_CTSB"), + /* GPP_S */ + PINCTRL_PIN(200, "SNDW1_CLK"), + PINCTRL_PIN(201, "SNDW1_DATA"), + PINCTRL_PIN(202, "SNDW2_CLK"), + PINCTRL_PIN(203, "SNDW2_DATA"), + PINCTRL_PIN(204, "SNDW3_CLK"), + PINCTRL_PIN(205, "SNDW3_DATA"), + PINCTRL_PIN(206, "SNDW4_CLK"), + PINCTRL_PIN(207, "SNDW4_DATA"), + /* GPP_E */ + PINCTRL_PIN(208, "SATAXPCIE_0"), + PINCTRL_PIN(209, "SATAXPCIE_1"), + PINCTRL_PIN(210, "SATAXPCIE_2"), + PINCTRL_PIN(211, "CPU_GP_0"), + PINCTRL_PIN(212, "SATA_DEVSLP_0"), + PINCTRL_PIN(213, "SATA_DEVSLP_1"), + PINCTRL_PIN(214, "SATA_DEVSLP_2"), + PINCTRL_PIN(215, "CPU_GP_1"), + PINCTRL_PIN(216, "SATA_LEDB"), + PINCTRL_PIN(217, "USB2_OCB_0"), + PINCTRL_PIN(218, "USB2_OCB_1"), + PINCTRL_PIN(219, "USB2_OCB_2"), + PINCTRL_PIN(220, "USB2_OCB_3"), + PINCTRL_PIN(221, "SPI1_CSB"), + PINCTRL_PIN(222, "SPI1_CLK"), + PINCTRL_PIN(223, "SPI1_MISO_IO_1"), + PINCTRL_PIN(224, "SPI1_MOSI_IO_0"), + PINCTRL_PIN(225, "SPI1_IO_2"), + PINCTRL_PIN(226, "SPI1_IO_3"), + PINCTRL_PIN(227, "GPP_E_19"), + PINCTRL_PIN(228, "GPP_E_20"), + PINCTRL_PIN(229, "ISH_UART0_CTSB"), + PINCTRL_PIN(230, "SPI1_CLK_LOOPBK"), + /* GPP_K */ + PINCTRL_PIN(231, "GSXDOUT"), + PINCTRL_PIN(232, "GSXSLOAD"), + PINCTRL_PIN(233, "GSXDIN"), + PINCTRL_PIN(234, "GSXSRESETB"), + PINCTRL_PIN(235, "GSXCLK"), + PINCTRL_PIN(236, "ADR_COMPLETE"), + PINCTRL_PIN(237, "GPP_K_6"), + PINCTRL_PIN(238, "GPP_K_7"), + PINCTRL_PIN(239, "CORE_VID_0"), + PINCTRL_PIN(240, "CORE_VID_1"), + PINCTRL_PIN(241, "GPP_K_10"), + PINCTRL_PIN(242, "GPP_K_11"), + PINCTRL_PIN(243, "SYS_PWROK"), + PINCTRL_PIN(244, "SYS_RESETB"), + PINCTRL_PIN(245, "MLK_RSTB"), + /* GPP_F */ + PINCTRL_PIN(246, "SATAXPCIE_3"), + PINCTRL_PIN(247, "SATAXPCIE_4"), + PINCTRL_PIN(248, "SATAXPCIE_5"), + PINCTRL_PIN(249, "SATAXPCIE_6"), + PINCTRL_PIN(250, "SATAXPCIE_7"), + PINCTRL_PIN(251, "SATA_DEVSLP_3"), + PINCTRL_PIN(252, "SATA_DEVSLP_4"), + PINCTRL_PIN(253, "SATA_DEVSLP_5"), + PINCTRL_PIN(254, "SATA_DEVSLP_6"), + PINCTRL_PIN(255, "SATA_DEVSLP_7"), + PINCTRL_PIN(256, "SATA_SCLOCK"), + PINCTRL_PIN(257, "SATA_SLOAD"), + PINCTRL_PIN(258, "SATA_SDATAOUT1"), + PINCTRL_PIN(259, "SATA_SDATAOUT0"), + PINCTRL_PIN(260, "PS_ONB"), + PINCTRL_PIN(261, "M2_SKT2_CFG_0"), + PINCTRL_PIN(262, "M2_SKT2_CFG_1"), + PINCTRL_PIN(263, "M2_SKT2_CFG_2"), + PINCTRL_PIN(264, "M2_SKT2_CFG_3"), + PINCTRL_PIN(265, "L_VDDEN"), + PINCTRL_PIN(266, "L_BKLTEN"), + PINCTRL_PIN(267, "L_BKLTCTL"), + PINCTRL_PIN(268, "VNN_CTRL"), + PINCTRL_PIN(269, "GPP_F_23"), + /* GPP_D */ + PINCTRL_PIN(270, "SRCCLKREQB_0"), + PINCTRL_PIN(271, "SRCCLKREQB_1"), + PINCTRL_PIN(272, "SRCCLKREQB_2"), + PINCTRL_PIN(273, "SRCCLKREQB_3"), + PINCTRL_PIN(274, "SML1CLK"), + PINCTRL_PIN(275, "I2S2_SFRM"), + PINCTRL_PIN(276, "I2S2_TXD"), + PINCTRL_PIN(277, "I2S2_RXD"), + PINCTRL_PIN(278, "I2S2_SCLK"), + PINCTRL_PIN(279, "SML0CLK"), + PINCTRL_PIN(280, "SML0DATA"), + PINCTRL_PIN(281, "SRCCLKREQB_4"), + PINCTRL_PIN(282, "SRCCLKREQB_5"), + PINCTRL_PIN(283, "SRCCLKREQB_6"), + PINCTRL_PIN(284, "SRCCLKREQB_7"), + PINCTRL_PIN(285, "SML1DATA"), + PINCTRL_PIN(286, "GSPI3_CS0B"), + PINCTRL_PIN(287, "GSPI3_CLK"), + PINCTRL_PIN(288, "GSPI3_MISO"), + PINCTRL_PIN(289, "GSPI3_MOSI"), + PINCTRL_PIN(290, "UART3_RXD"), + PINCTRL_PIN(291, "UART3_TXD"), + PINCTRL_PIN(292, "UART3_RTSB"), + PINCTRL_PIN(293, "UART3_CTSB"), + PINCTRL_PIN(294, "GSPI3_CLK_LOOPBK"), + /* JTAG */ + PINCTRL_PIN(295, "JTAG_TDO"), + PINCTRL_PIN(296, "JTAGX"), + PINCTRL_PIN(297, "PRDYB"), + PINCTRL_PIN(298, "PREQB"), + PINCTRL_PIN(299, "JTAG_TDI"), + PINCTRL_PIN(300, "JTAG_TMS"), + PINCTRL_PIN(301, "JTAG_TCK"), + PINCTRL_PIN(302, "DBG_PMODE"), + PINCTRL_PIN(303, "CPU_TRSTB"), +}; + +static const struct intel_padgroup adls_community0_gpps[] = { + ADL_GPP(0, 0, 24, 0), /* GPP_I */ + ADL_GPP(1, 25, 47, 32), /* GPP_R */ + ADL_GPP(2, 48, 59, 64), /* GPP_J */ + ADL_GPP(3, 60, 86, 96), /* vGPIO */ + ADL_GPP(4, 87, 94, 128), /* vGPIO_0 */ +}; + +static const struct intel_padgroup adls_community1_gpps[] = { + ADL_GPP(0, 95, 118, 160), /* GPP_B */ + ADL_GPP(1, 119, 126, 192), /* GPP_G */ + ADL_GPP(2, 127, 150, 224), /* GPP_H */ +}; + +static const struct intel_padgroup adls_community3_gpps[] = { + ADL_GPP(0, 151, 159, INTEL_GPIO_BASE_NOMAP), /* SPI0 */ + ADL_GPP(1, 160, 175, 256), /* GPP_A */ + ADL_GPP(2, 176, 199, 288), /* GPP_C */ +}; + +static const struct intel_padgroup adls_community4_gpps[] = { + ADL_GPP(0, 200, 207, 320), /* GPP_S */ + ADL_GPP(1, 208, 230, 352), /* GPP_E */ + ADL_GPP(2, 231, 245, 384), /* GPP_K */ + ADL_GPP(3, 246, 269, 416), /* GPP_F */ +}; + +static const struct intel_padgroup adls_community5_gpps[] = { + ADL_GPP(0, 270, 294, 448), /* GPP_D */ + ADL_GPP(1, 295, 303, INTEL_GPIO_BASE_NOMAP), /* JTAG */ +}; + +static const struct intel_community adls_communities[] = { + ADL_COMMUNITY(0, 0, 94, adls_community0_gpps), + ADL_COMMUNITY(1, 95, 150, adls_community1_gpps), + ADL_COMMUNITY(2, 151, 199, adls_community3_gpps), + ADL_COMMUNITY(3, 200, 269, adls_community4_gpps), + ADL_COMMUNITY(4, 270, 303, adls_community5_gpps), +}; + +static const struct intel_pinctrl_soc_data adls_soc_data = { + .pins = adls_pins, + .npins = ARRAY_SIZE(adls_pins), + .communities = adls_communities, + .ncommunities = ARRAY_SIZE(adls_communities), +}; + +static const struct acpi_device_id adl_pinctrl_acpi_match[] = { + { "INTC1056", (kernel_ulong_t)&adls_soc_data }, + { } +}; +MODULE_DEVICE_TABLE(acpi, adl_pinctrl_acpi_match); + +static INTEL_PINCTRL_PM_OPS(adl_pinctrl_pm_ops); + +static struct platform_driver adl_pinctrl_driver = { + .probe = intel_pinctrl_probe_by_hid, + .driver = { + .name = "alderlake-pinctrl", + .acpi_match_table = adl_pinctrl_acpi_match, + .pm = &adl_pinctrl_pm_ops, + }, +}; +module_platform_driver(adl_pinctrl_driver); + +MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); +MODULE_DESCRIPTION("Intel Alder Lake PCH pinctrl/GPIO driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/intel/pinctrl-elkhartlake.c b/drivers/pinctrl/intel/pinctrl-elkhartlake.c new file mode 100644 index 000000000000..4702bdfa10e3 --- /dev/null +++ b/drivers/pinctrl/intel/pinctrl-elkhartlake.c @@ -0,0 +1,513 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Intel Elkhart Lake PCH pinctrl/GPIO driver + * + * Copyright (C) 2019, Intel Corporation + * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> + */ + +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/platform_device.h> + +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-intel.h" + +#define EHL_PAD_OWN 0x020 +#define EHL_PADCFGLOCK 0x080 +#define EHL_HOSTSW_OWN 0x0b0 +#define EHL_GPI_IS 0x100 +#define EHL_GPI_IE 0x120 + +#define EHL_GPP(r, s, e) \ + { \ + .reg_num = (r), \ + .base = (s), \ + .size = ((e) - (s) + 1), \ + } + +#define EHL_COMMUNITY(s, e, g) \ + { \ + .padown_offset = EHL_PAD_OWN, \ + .padcfglock_offset = EHL_PADCFGLOCK, \ + .hostown_offset = EHL_HOSTSW_OWN, \ + .is_offset = EHL_GPI_IS, \ + .ie_offset = EHL_GPI_IE, \ + .pin_base = (s), \ + .npins = ((e) - (s) + 1), \ + .gpps = (g), \ + .ngpps = ARRAY_SIZE(g), \ + } + +/* Elkhart Lake */ +static const struct pinctrl_pin_desc ehl_community0_pins[] = { + /* GPP_B */ + PINCTRL_PIN(0, "CORE_VID_0"), + PINCTRL_PIN(1, "CORE_VID_1"), + PINCTRL_PIN(2, "VRALERTB"), + PINCTRL_PIN(3, "CPU_GP_2"), + PINCTRL_PIN(4, "CPU_GP_3"), + PINCTRL_PIN(5, "OSE_I2C0_SCLK"), + PINCTRL_PIN(6, "OSE_I2C0_SDAT"), + PINCTRL_PIN(7, "OSE_I2C1_SCLK"), + PINCTRL_PIN(8, "OSE_I2C1_SDAT"), + PINCTRL_PIN(9, "I2C5_SDA"), + PINCTRL_PIN(10, "I2C5_SCL"), + PINCTRL_PIN(11, "PMCALERTB"), + PINCTRL_PIN(12, "SLP_S0B"), + PINCTRL_PIN(13, "PLTRSTB"), + PINCTRL_PIN(14, "SPKR"), + PINCTRL_PIN(15, "GSPI0_CS0B"), + PINCTRL_PIN(16, "GSPI0_CLK"), + PINCTRL_PIN(17, "GSPI0_MISO"), + PINCTRL_PIN(18, "GSPI0_MOSI"), + PINCTRL_PIN(19, "GSPI1_CS0B"), + PINCTRL_PIN(20, "GSPI1_CLK"), + PINCTRL_PIN(21, "GSPI1_MISO"), + PINCTRL_PIN(22, "GSPI1_MOSI"), + PINCTRL_PIN(23, "GPPC_B_23"), + PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK"), + PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK"), + /* GPP_T */ + PINCTRL_PIN(26, "OSE_QEPA_2"), + PINCTRL_PIN(27, "OSE_QEPB_2"), + PINCTRL_PIN(28, "OSE_QEPI_2"), + PINCTRL_PIN(29, "GPPC_T_3"), + PINCTRL_PIN(30, "RGMII0_INT"), + PINCTRL_PIN(31, "RGMII0_RESETB"), + PINCTRL_PIN(32, "RGMII0_AUXTS"), + PINCTRL_PIN(33, "RGMII0_PPS"), + PINCTRL_PIN(34, "USB2_OCB_2"), + PINCTRL_PIN(35, "OSE_HSUART2_EN"), + PINCTRL_PIN(36, "OSE_HSUART2_RE"), + PINCTRL_PIN(37, "USB2_OCB_3"), + PINCTRL_PIN(38, "OSE_UART2_RXD"), + PINCTRL_PIN(39, "OSE_UART2_TXD"), + PINCTRL_PIN(40, "OSE_UART2_RTSB"), + PINCTRL_PIN(41, "OSE_UART2_CTSB"), + /* GPP_G */ + PINCTRL_PIN(42, "SD3_CMD"), + PINCTRL_PIN(43, "SD3_D0"), + PINCTRL_PIN(44, "SD3_D1"), + PINCTRL_PIN(45, "SD3_D2"), + PINCTRL_PIN(46, "SD3_D3"), + PINCTRL_PIN(47, "SD3_CDB"), + PINCTRL_PIN(48, "SD3_CLK"), + PINCTRL_PIN(49, "I2S2_SCLK"), + PINCTRL_PIN(50, "I2S2_SFRM"), + PINCTRL_PIN(51, "I2S2_TXD"), + PINCTRL_PIN(52, "I2S2_RXD"), + PINCTRL_PIN(53, "I2S3_SCLK"), + PINCTRL_PIN(54, "I2S3_SFRM"), + PINCTRL_PIN(55, "I2S3_TXD"), + PINCTRL_PIN(56, "I2S3_RXD"), + PINCTRL_PIN(57, "ESPI_IO_0"), + PINCTRL_PIN(58, "ESPI_IO_1"), + PINCTRL_PIN(59, "ESPI_IO_2"), + PINCTRL_PIN(60, "ESPI_IO_3"), + PINCTRL_PIN(61, "I2S1_SCLK"), + PINCTRL_PIN(62, "ESPI_CSB"), + PINCTRL_PIN(63, "ESPI_CLK"), + PINCTRL_PIN(64, "ESPI_RESETB"), + PINCTRL_PIN(65, "SD3_WP"), + PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"), +}; + +static const struct intel_padgroup ehl_community0_gpps[] = { + EHL_GPP(0, 0, 25), /* GPP_B */ + EHL_GPP(1, 26, 41), /* GPP_T */ + EHL_GPP(2, 42, 66), /* GPP_G */ +}; + +static const struct intel_community ehl_community0[] = { + EHL_COMMUNITY(0, 66, ehl_community0_gpps), +}; + +static const struct intel_pinctrl_soc_data ehl_community0_soc_data = { + .uid = "0", + .pins = ehl_community0_pins, + .npins = ARRAY_SIZE(ehl_community0_pins), + .communities = ehl_community0, + .ncommunities = ARRAY_SIZE(ehl_community0), +}; + +static const struct pinctrl_pin_desc ehl_community1_pins[] = { + /* GPP_V */ + PINCTRL_PIN(0, "EMMC_CMD"), + PINCTRL_PIN(1, "EMMC_DATA0"), + PINCTRL_PIN(2, "EMMC_DATA1"), + PINCTRL_PIN(3, "EMMC_DATA2"), + PINCTRL_PIN(4, "EMMC_DATA3"), + PINCTRL_PIN(5, "EMMC_DATA4"), + PINCTRL_PIN(6, "EMMC_DATA5"), + PINCTRL_PIN(7, "EMMC_DATA6"), + PINCTRL_PIN(8, "EMMC_DATA7"), + PINCTRL_PIN(9, "EMMC_RCLK"), + PINCTRL_PIN(10, "EMMC_CLK"), + PINCTRL_PIN(11, "EMMC_RESETB"), + PINCTRL_PIN(12, "OSE_TGPIO0"), + PINCTRL_PIN(13, "OSE_TGPIO1"), + PINCTRL_PIN(14, "OSE_TGPIO2"), + PINCTRL_PIN(15, "OSE_TGPIO3"), + /* GPP_H */ + PINCTRL_PIN(16, "RGMII1_INT"), + PINCTRL_PIN(17, "RGMII1_RESETB"), + PINCTRL_PIN(18, "RGMII1_AUXTS"), + PINCTRL_PIN(19, "RGMII1_PPS"), + PINCTRL_PIN(20, "I2C2_SDA"), + PINCTRL_PIN(21, "I2C2_SCL"), + PINCTRL_PIN(22, "I2C3_SDA"), + PINCTRL_PIN(23, "I2C3_SCL"), + PINCTRL_PIN(24, "I2C4_SDA"), + PINCTRL_PIN(25, "I2C4_SCL"), + PINCTRL_PIN(26, "SRCCLKREQB_4"), + PINCTRL_PIN(27, "SRCCLKREQB_5"), + PINCTRL_PIN(28, "OSE_UART1_RXD"), + PINCTRL_PIN(29, "OSE_UART1_TXD"), + PINCTRL_PIN(30, "GPPC_H_14"), + PINCTRL_PIN(31, "OSE_UART1_CTSB"), + PINCTRL_PIN(32, "PCIE_LNK_DOWN"), + PINCTRL_PIN(33, "SD_PWR_EN_B"), + PINCTRL_PIN(34, "CPU_C10_GATEB"), + PINCTRL_PIN(35, "GPPC_H_19"), + PINCTRL_PIN(36, "OSE_PWM7"), + PINCTRL_PIN(37, "OSE_HSUART1_DE"), + PINCTRL_PIN(38, "OSE_HSUART1_RE"), + PINCTRL_PIN(39, "OSE_HSUART1_EN"), + /* GPP_D */ + PINCTRL_PIN(40, "OSE_QEPA_0"), + PINCTRL_PIN(41, "OSE_QEPB_0"), + PINCTRL_PIN(42, "OSE_QEPI_0"), + PINCTRL_PIN(43, "OSE_PWM6"), + PINCTRL_PIN(44, "OSE_PWM2"), + PINCTRL_PIN(45, "SRCCLKREQB_0"), + PINCTRL_PIN(46, "SRCCLKREQB_1"), + PINCTRL_PIN(47, "SRCCLKREQB_2"), + PINCTRL_PIN(48, "SRCCLKREQB_3"), + PINCTRL_PIN(49, "OSE_SPI0_CSB"), + PINCTRL_PIN(50, "OSE_SPI0_SCLK"), + PINCTRL_PIN(51, "OSE_SPI0_MISO"), + PINCTRL_PIN(52, "OSE_SPI0_MOSI"), + PINCTRL_PIN(53, "OSE_QEPA_1"), + PINCTRL_PIN(54, "OSE_QEPB_1"), + PINCTRL_PIN(55, "OSE_PWM3"), + PINCTRL_PIN(56, "OSE_QEPI_1"), + PINCTRL_PIN(57, "OSE_PWM4"), + PINCTRL_PIN(58, "OSE_PWM5"), + PINCTRL_PIN(59, "I2S_MCLK1_OUT"), + PINCTRL_PIN(60, "GSPI2_CLK_LOOPBK"), + /* GPP_U */ + PINCTRL_PIN(61, "RGMII2_INT"), + PINCTRL_PIN(62, "RGMII2_RESETB"), + PINCTRL_PIN(63, "RGMII2_PPS"), + PINCTRL_PIN(64, "RGMII2_AUXTS"), + PINCTRL_PIN(65, "ISI_SPIM_CS"), + PINCTRL_PIN(66, "ISI_SPIM_SCLK"), + PINCTRL_PIN(67, "ISI_SPIM_MISO"), + PINCTRL_PIN(68, "OSE_QEPA_3"), + PINCTRL_PIN(69, "ISI_SPIS_CS"), + PINCTRL_PIN(70, "ISI_SPIS_SCLK"), + PINCTRL_PIN(71, "ISI_SPIS_MISO"), + PINCTRL_PIN(72, "OSE_QEPB_3"), + PINCTRL_PIN(73, "ISI_CHX_OKNOK_0"), + PINCTRL_PIN(74, "ISI_CHX_OKNOK_1"), + PINCTRL_PIN(75, "ISI_CHX_RLY_SWTCH"), + PINCTRL_PIN(76, "ISI_CHX_PMIC_EN"), + PINCTRL_PIN(77, "ISI_OKNOK_0"), + PINCTRL_PIN(78, "ISI_OKNOK_1"), + PINCTRL_PIN(79, "ISI_ALERT"), + PINCTRL_PIN(80, "OSE_QEPI_3"), + PINCTRL_PIN(81, "GSPI3_CLK_LOOPBK"), + PINCTRL_PIN(82, "GSPI4_CLK_LOOPBK"), + PINCTRL_PIN(83, "GSPI5_CLK_LOOPBK"), + PINCTRL_PIN(84, "GSPI6_CLK_LOOPBK"), + /* vGPIO */ + PINCTRL_PIN(85, "CNV_BTEN"), + PINCTRL_PIN(86, "CNV_BT_HOST_WAKEB"), + PINCTRL_PIN(87, "CNV_BT_IF_SELECT"), + PINCTRL_PIN(88, "vCNV_BT_UART_TXD"), + PINCTRL_PIN(89, "vCNV_BT_UART_RXD"), + PINCTRL_PIN(90, "vCNV_BT_UART_CTS_B"), + PINCTRL_PIN(91, "vCNV_BT_UART_RTS_B"), + PINCTRL_PIN(92, "vCNV_MFUART1_TXD"), + PINCTRL_PIN(93, "vCNV_MFUART1_RXD"), + PINCTRL_PIN(94, "vCNV_MFUART1_CTS_B"), + PINCTRL_PIN(95, "vCNV_MFUART1_RTS_B"), + PINCTRL_PIN(96, "vUART0_TXD"), + PINCTRL_PIN(97, "vUART0_RXD"), + PINCTRL_PIN(98, "vUART0_CTS_B"), + PINCTRL_PIN(99, "vUART0_RTS_B"), + PINCTRL_PIN(100, "vOSE_UART0_TXD"), + PINCTRL_PIN(101, "vOSE_UART0_RXD"), + PINCTRL_PIN(102, "vOSE_UART0_CTS_B"), + PINCTRL_PIN(103, "vOSE_UART0_RTS_B"), + PINCTRL_PIN(104, "vCNV_BT_I2S_BCLK"), + PINCTRL_PIN(105, "vCNV_BT_I2S_WS_SYNC"), + PINCTRL_PIN(106, "vCNV_BT_I2S_SDO"), + PINCTRL_PIN(107, "vCNV_BT_I2S_SDI"), + PINCTRL_PIN(108, "vI2S2_SCLK"), + PINCTRL_PIN(109, "vI2S2_SFRM"), + PINCTRL_PIN(110, "vI2S2_TXD"), + PINCTRL_PIN(111, "vI2S2_RXD"), + PINCTRL_PIN(112, "vSD3_CD_B"), +}; + +static const struct intel_padgroup ehl_community1_gpps[] = { + EHL_GPP(0, 0, 15), /* GPP_V */ + EHL_GPP(1, 16, 39), /* GPP_H */ + EHL_GPP(2, 40, 60), /* GPP_D */ + EHL_GPP(3, 61, 84), /* GPP_U */ + EHL_GPP(4, 85, 112), /* vGPIO */ +}; + +static const struct intel_community ehl_community1[] = { + EHL_COMMUNITY(0, 112, ehl_community1_gpps), +}; + +static const struct intel_pinctrl_soc_data ehl_community1_soc_data = { + .uid = "1", + .pins = ehl_community1_pins, + .npins = ARRAY_SIZE(ehl_community1_pins), + .communities = ehl_community1, + .ncommunities = ARRAY_SIZE(ehl_community1), +}; + +static const struct pinctrl_pin_desc ehl_community3_pins[] = { + /* CPU */ + PINCTRL_PIN(0, "HDACPU_SDI"), + PINCTRL_PIN(1, "HDACPU_SDO"), + PINCTRL_PIN(2, "HDACPU_BCLK"), + PINCTRL_PIN(3, "PM_SYNC"), + PINCTRL_PIN(4, "PECI"), + PINCTRL_PIN(5, "CPUPWRGD"), + PINCTRL_PIN(6, "THRMTRIPB"), + PINCTRL_PIN(7, "PLTRST_CPUB"), + PINCTRL_PIN(8, "PM_DOWN"), + PINCTRL_PIN(9, "TRIGGER_IN"), + PINCTRL_PIN(10, "TRIGGER_OUT"), + PINCTRL_PIN(11, "UFS_RESETB"), + PINCTRL_PIN(12, "CLKOUT_CPURTC"), + PINCTRL_PIN(13, "VCCST_OVERRIDE"), + PINCTRL_PIN(14, "C10_WAKE"), + PINCTRL_PIN(15, "PROCHOTB"), + PINCTRL_PIN(16, "CATERRB"), + /* GPP_S */ + PINCTRL_PIN(17, "UFS_REF_CLK_0"), + PINCTRL_PIN(18, "UFS_REF_CLK_1"), + /* GPP_A */ + PINCTRL_PIN(19, "RGMII0_TXDATA_3"), + PINCTRL_PIN(20, "RGMII0_TXDATA_2"), + PINCTRL_PIN(21, "RGMII0_TXDATA_1"), + PINCTRL_PIN(22, "RGMII0_TXDATA_0"), + PINCTRL_PIN(23, "RGMII0_TXCLK"), + PINCTRL_PIN(24, "RGMII0_TXCTL"), + PINCTRL_PIN(25, "RGMII0_RXCLK"), + PINCTRL_PIN(26, "RGMII0_RXDATA_3"), + PINCTRL_PIN(27, "RGMII0_RXDATA_2"), + PINCTRL_PIN(28, "RGMII0_RXDATA_1"), + PINCTRL_PIN(29, "RGMII0_RXDATA_0"), + PINCTRL_PIN(30, "RGMII1_TXDATA_3"), + PINCTRL_PIN(31, "RGMII1_TXDATA_2"), + PINCTRL_PIN(32, "RGMII1_TXDATA_1"), + PINCTRL_PIN(33, "RGMII1_TXDATA_0"), + PINCTRL_PIN(34, "RGMII1_TXCLK"), + PINCTRL_PIN(35, "RGMII1_TXCTL"), + PINCTRL_PIN(36, "RGMII1_RXCLK"), + PINCTRL_PIN(37, "RGMII1_RXCTL"), + PINCTRL_PIN(38, "RGMII1_RXDATA_3"), + PINCTRL_PIN(39, "RGMII1_RXDATA_2"), + PINCTRL_PIN(40, "RGMII1_RXDATA_1"), + PINCTRL_PIN(41, "RGMII1_RXDATA_0"), + PINCTRL_PIN(42, "RGMII0_RXCTL"), + /* vGPIO_3 */ + PINCTRL_PIN(43, "ESPI_USB_OCB_0"), + PINCTRL_PIN(44, "ESPI_USB_OCB_1"), + PINCTRL_PIN(45, "ESPI_USB_OCB_2"), + PINCTRL_PIN(46, "ESPI_USB_OCB_3"), +}; + +static const struct intel_padgroup ehl_community3_gpps[] = { + EHL_GPP(0, 0, 16), /* CPU */ + EHL_GPP(1, 17, 18), /* GPP_S */ + EHL_GPP(2, 19, 42), /* GPP_A */ + EHL_GPP(3, 43, 46), /* vGPIO_3 */ +}; + +static const struct intel_community ehl_community3[] = { + EHL_COMMUNITY(0, 46, ehl_community3_gpps), +}; + +static const struct intel_pinctrl_soc_data ehl_community3_soc_data = { + .uid = "3", + .pins = ehl_community3_pins, + .npins = ARRAY_SIZE(ehl_community3_pins), + .communities = ehl_community3, + .ncommunities = ARRAY_SIZE(ehl_community3), +}; + +static const struct pinctrl_pin_desc ehl_community4_pins[] = { + /* GPP_C */ + PINCTRL_PIN(0, "SMBCLK"), + PINCTRL_PIN(1, "SMBDATA"), + PINCTRL_PIN(2, "OSE_PWM0"), + PINCTRL_PIN(3, "RGMII0_MDC"), + PINCTRL_PIN(4, "RGMII0_MDIO"), + PINCTRL_PIN(5, "OSE_PWM1"), + PINCTRL_PIN(6, "RGMII1_MDC"), + PINCTRL_PIN(7, "RGMII1_MDIO"), + PINCTRL_PIN(8, "OSE_TGPIO4"), + PINCTRL_PIN(9, "OSE_HSUART0_EN"), + PINCTRL_PIN(10, "OSE_TGPIO5"), + PINCTRL_PIN(11, "OSE_HSUART0_RE"), + PINCTRL_PIN(12, "OSE_UART0_RXD"), + PINCTRL_PIN(13, "OSE_UART0_TXD"), + PINCTRL_PIN(14, "OSE_UART0_RTSB"), + PINCTRL_PIN(15, "OSE_UART0_CTSB"), + PINCTRL_PIN(16, "RGMII2_MDIO"), + PINCTRL_PIN(17, "RGMII2_MDC"), + PINCTRL_PIN(18, "OSE_I2C4_SDAT"), + PINCTRL_PIN(19, "OSE_I2C4_SCLK"), + PINCTRL_PIN(20, "OSE_UART4_RXD"), + PINCTRL_PIN(21, "OSE_UART4_TXD"), + PINCTRL_PIN(22, "OSE_UART4_RTSB"), + PINCTRL_PIN(23, "OSE_UART4_CTSB"), + /* GPP_F */ + PINCTRL_PIN(24, "CNV_BRI_DT"), + PINCTRL_PIN(25, "CNV_BRI_RSP"), + PINCTRL_PIN(26, "CNV_RGI_DT"), + PINCTRL_PIN(27, "CNV_RGI_RSP"), + PINCTRL_PIN(28, "CNV_RF_RESET_B"), + PINCTRL_PIN(29, "EMMC_HIP_MON"), + PINCTRL_PIN(30, "CNV_PA_BLANKING"), + PINCTRL_PIN(31, "OSE_I2S1_SCLK"), + PINCTRL_PIN(32, "I2S_MCLK2_INOUT"), + PINCTRL_PIN(33, "BOOTMPC"), + PINCTRL_PIN(34, "OSE_I2S1_SFRM"), + PINCTRL_PIN(35, "GPPC_F_11"), + PINCTRL_PIN(36, "GSXDOUT"), + PINCTRL_PIN(37, "GSXSLOAD"), + PINCTRL_PIN(38, "GSXDIN"), + PINCTRL_PIN(39, "GSXSRESETB"), + PINCTRL_PIN(40, "GSXCLK"), + PINCTRL_PIN(41, "GPPC_F_17"), + PINCTRL_PIN(42, "OSE_I2S1_TXD"), + PINCTRL_PIN(43, "OSE_I2S1_RXD"), + PINCTRL_PIN(44, "EXT_PWR_GATEB"), + PINCTRL_PIN(45, "EXT_PWR_GATE2B"), + PINCTRL_PIN(46, "VNN_CTRL"), + PINCTRL_PIN(47, "V1P05_CTRL"), + PINCTRL_PIN(48, "GPPF_CLK_LOOPBACK"), + /* HVCMOS */ + PINCTRL_PIN(49, "L_BKLTEN"), + PINCTRL_PIN(50, "L_BKLTCTL"), + PINCTRL_PIN(51, "L_VDDEN"), + PINCTRL_PIN(52, "SYS_PWROK"), + PINCTRL_PIN(53, "SYS_RESETB"), + PINCTRL_PIN(54, "MLK_RSTB"), + /* GPP_E */ + PINCTRL_PIN(55, "SATA_LEDB"), + PINCTRL_PIN(56, "GPPC_E_1"), + PINCTRL_PIN(57, "GPPC_E_2"), + PINCTRL_PIN(58, "DDSP_HPD_B"), + PINCTRL_PIN(59, "SATA_DEVSLP_0"), + PINCTRL_PIN(60, "DDPB_CTRLDATA"), + PINCTRL_PIN(61, "GPPC_E_6"), + PINCTRL_PIN(62, "DDPB_CTRLCLK"), + PINCTRL_PIN(63, "GPPC_E_8"), + PINCTRL_PIN(64, "USB2_OCB_0"), + PINCTRL_PIN(65, "GPPC_E_10"), + PINCTRL_PIN(66, "GPPC_E_11"), + PINCTRL_PIN(67, "GPPC_E_12"), + PINCTRL_PIN(68, "GPPC_E_13"), + PINCTRL_PIN(69, "DDSP_HPD_A"), + PINCTRL_PIN(70, "OSE_I2S0_RXD"), + PINCTRL_PIN(71, "OSE_I2S0_TXD"), + PINCTRL_PIN(72, "DDSP_HPD_C"), + PINCTRL_PIN(73, "DDPA_CTRLDATA"), + PINCTRL_PIN(74, "DDPA_CTRLCLK"), + PINCTRL_PIN(75, "OSE_I2S0_SCLK"), + PINCTRL_PIN(76, "OSE_I2S0_SFRM"), + PINCTRL_PIN(77, "DDPC_CTRLDATA"), + PINCTRL_PIN(78, "DDPC_CTRLCLK"), + PINCTRL_PIN(79, "SPI1_CLK_LOOPBK"), +}; + +static const struct intel_padgroup ehl_community4_gpps[] = { + EHL_GPP(0, 0, 23), /* GPP_C */ + EHL_GPP(1, 24, 48), /* GPP_F */ + EHL_GPP(2, 49, 54), /* HVCMOS */ + EHL_GPP(3, 55, 79), /* GPP_E */ +}; + +static const struct intel_community ehl_community4[] = { + EHL_COMMUNITY(0, 79, ehl_community4_gpps), +}; + +static const struct intel_pinctrl_soc_data ehl_community4_soc_data = { + .uid = "4", + .pins = ehl_community4_pins, + .npins = ARRAY_SIZE(ehl_community4_pins), + .communities = ehl_community4, + .ncommunities = ARRAY_SIZE(ehl_community4), +}; + +static const struct pinctrl_pin_desc ehl_community5_pins[] = { + /* GPP_R */ + PINCTRL_PIN(0, "HDA_BCLK"), + PINCTRL_PIN(1, "HDA_SYNC"), + PINCTRL_PIN(2, "HDA_SDO"), + PINCTRL_PIN(3, "HDA_SDI_0"), + PINCTRL_PIN(4, "HDA_RSTB"), + PINCTRL_PIN(5, "HDA_SDI_1"), + PINCTRL_PIN(6, "GPP_R_6"), + PINCTRL_PIN(7, "GPP_R_7"), +}; + +static const struct intel_padgroup ehl_community5_gpps[] = { + EHL_GPP(0, 0, 7), /* GPP_R */ +}; + +static const struct intel_community ehl_community5[] = { + EHL_COMMUNITY(0, 7, ehl_community5_gpps), +}; + +static const struct intel_pinctrl_soc_data ehl_community5_soc_data = { + .uid = "5", + .pins = ehl_community5_pins, + .npins = ARRAY_SIZE(ehl_community5_pins), + .communities = ehl_community5, + .ncommunities = ARRAY_SIZE(ehl_community5), +}; + +static const struct intel_pinctrl_soc_data *ehl_soc_data_array[] = { + &ehl_community0_soc_data, + &ehl_community1_soc_data, + &ehl_community3_soc_data, + &ehl_community4_soc_data, + &ehl_community5_soc_data, + NULL +}; + +static const struct acpi_device_id ehl_pinctrl_acpi_match[] = { + { "INTC1020", (kernel_ulong_t)ehl_soc_data_array }, + { } +}; +MODULE_DEVICE_TABLE(acpi, ehl_pinctrl_acpi_match); + +static INTEL_PINCTRL_PM_OPS(ehl_pinctrl_pm_ops); + +static struct platform_driver ehl_pinctrl_driver = { + .probe = intel_pinctrl_probe_by_uid, + .driver = { + .name = "elkhartlake-pinctrl", + .acpi_match_table = ehl_pinctrl_acpi_match, + .pm = &ehl_pinctrl_pm_ops, + }, +}; + +module_platform_driver(ehl_pinctrl_driver); + +MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); +MODULE_DESCRIPTION("Intel Elkhart Lake PCH pinctrl/GPIO driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/intel/pinctrl-lakefield.c b/drivers/pinctrl/intel/pinctrl-lakefield.c new file mode 100644 index 000000000000..3c6283c4827f --- /dev/null +++ b/drivers/pinctrl/intel/pinctrl-lakefield.c @@ -0,0 +1,375 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Intel Lakefield PCH pinctrl/GPIO driver + * + * Copyright (C) 2020, Intel Corporation + * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> + */ + +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/platform_device.h> + +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-intel.h" + +#define LKF_PAD_OWN 0x020 +#define LKF_PADCFGLOCK 0x070 +#define LKF_HOSTSW_OWN 0x090 +#define LKF_GPI_IS 0x100 +#define LKF_GPI_IE 0x110 + +#define LKF_GPP(r, s, e, g) \ + { \ + .reg_num = (r), \ + .base = (s), \ + .size = ((e) - (s) + 1), \ + .gpio_base = (g), \ + } + +#define LKF_COMMUNITY(b, s, e, g) \ + { \ + .barno = (b), \ + .padown_offset = LKF_PAD_OWN, \ + .padcfglock_offset = LKF_PADCFGLOCK, \ + .hostown_offset = LKF_HOSTSW_OWN, \ + .is_offset = LKF_GPI_IS, \ + .ie_offset = LKF_GPI_IE, \ + .pin_base = (s), \ + .npins = ((e) - (s) + 1), \ + .gpps = (g), \ + .ngpps = ARRAY_SIZE(g), \ + } + +/* Lakefield */ +static const struct pinctrl_pin_desc lkf_pins[] = { + /* EAST */ + PINCTRL_PIN(0, "MDSI_A_TE0"), + PINCTRL_PIN(1, "MDSI_A_TE1"), + PINCTRL_PIN(2, "PANEL0_AVDD_EN"), + PINCTRL_PIN(3, "PANEL0_BKLTEN"), + PINCTRL_PIN(4, "PANEL0_BKLTCTL"), + PINCTRL_PIN(5, "PANEL1_AVDD_EN"), + PINCTRL_PIN(6, "PANEL1_BKLTEN"), + PINCTRL_PIN(7, "PANEL1_BKLTCTL"), + PINCTRL_PIN(8, "THC0_SPI1_IO_0"), + PINCTRL_PIN(9, "THC0_SPI1_IO_1"), + PINCTRL_PIN(10, "THC0_SPI1_IO_2"), + PINCTRL_PIN(11, "THC0_SPI1_IO_3"), + PINCTRL_PIN(12, "THC0_SPI1_CSB"), + PINCTRL_PIN(13, "THC0_SPI1_CLK"), + PINCTRL_PIN(14, "THC0_SPI1_RESETB"), + PINCTRL_PIN(15, "THC0_SPI1_CLK_FB"), + PINCTRL_PIN(16, "SPI_TOUCH_CLK_FB"), + PINCTRL_PIN(17, "THC1_SPI2_IO_0"), + PINCTRL_PIN(18, "THC1_SPI2_IO_1"), + PINCTRL_PIN(19, "THC1_SPI2_IO_2"), + PINCTRL_PIN(20, "THC1_SPI2_IO_3"), + PINCTRL_PIN(21, "THC1_SPI2_CSB"), + PINCTRL_PIN(22, "THC1_SPI2_CLK"), + PINCTRL_PIN(23, "THC1_SPI2_RESETB"), + PINCTRL_PIN(24, "THC1_SPI2_CLK_FB"), + PINCTRL_PIN(25, "eSPI_IO_0"), + PINCTRL_PIN(26, "eSPI_IO_1"), + PINCTRL_PIN(27, "eSPI_IO_2"), + PINCTRL_PIN(28, "eSPI_IO_3"), + PINCTRL_PIN(29, "eSPI_CSB"), + PINCTRL_PIN(30, "eSPI_RESETB"), + PINCTRL_PIN(31, "eSPI_CLK"), + PINCTRL_PIN(32, "eSPI_CLK_FB"), + PINCTRL_PIN(33, "FAST_SPI0_IO_0"), + PINCTRL_PIN(34, "FAST_SPI0_IO_1"), + PINCTRL_PIN(35, "FAST_SPI0_IO_2"), + PINCTRL_PIN(36, "FAST_SPI0_IO_3"), + PINCTRL_PIN(37, "FAST_SPI0_CSB_0"), + PINCTRL_PIN(38, "FAST_SPI0_CSB_2"), + PINCTRL_PIN(39, "FAST_SPI0_CLK"), + PINCTRL_PIN(40, "FAST_SPI_CLK_FB"), + PINCTRL_PIN(41, "FAST_SPI0_CSB_1"), + PINCTRL_PIN(42, "ISH_GP_12"), + PINCTRL_PIN(43, "THC0_SPI1_INTB"), + PINCTRL_PIN(44, "THC1_SPI2_INTB"), + PINCTRL_PIN(45, "PANEL0_AVEE_EN"), + PINCTRL_PIN(46, "PANEL0_VIO_EN"), + PINCTRL_PIN(47, "PANEL1_AVEE_EN"), + PINCTRL_PIN(48, "PANEL1_VIO_EN"), + PINCTRL_PIN(49, "PANEL0_RESET"), + PINCTRL_PIN(50, "PANEL1_RESET"), + PINCTRL_PIN(51, "ISH_GP_15"), + PINCTRL_PIN(52, "ISH_GP_16"), + PINCTRL_PIN(53, "ISH_GP_17"), + PINCTRL_PIN(54, "ISH_GP_18"), + PINCTRL_PIN(55, "ISH_GP_19"), + PINCTRL_PIN(56, "ISH_GP_20"), + PINCTRL_PIN(57, "ISH_GP_21"), + PINCTRL_PIN(58, "ISH_GP_22"), + PINCTRL_PIN(59, "ISH_GP_23"), + /* NORTHWEST */ + PINCTRL_PIN(60, "MCSI_GPIO_0"), + PINCTRL_PIN(61, "MCSI_GPIO_1"), + PINCTRL_PIN(62, "MCSI_GPIO_2"), + PINCTRL_PIN(63, "MCSI_GPIO_3"), + PINCTRL_PIN(64, "LPSS_I2C0_SDA"), + PINCTRL_PIN(65, "LPSS_I2C0_SCL"), + PINCTRL_PIN(66, "LPSS_I2C1_SDA"), + PINCTRL_PIN(67, "LPSS_I2C1_SCL"), + PINCTRL_PIN(68, "LPSS_I2C2_SDA"), + PINCTRL_PIN(69, "LPSS_I2C2_SCL"), + PINCTRL_PIN(70, "LPSS_I2C3_SDA"), + PINCTRL_PIN(71, "LPSS_I2C3_SCL"), + PINCTRL_PIN(72, "LPSS_I2C4_SDA"), + PINCTRL_PIN(73, "LPSS_I2C4_SCL"), + PINCTRL_PIN(74, "LPSS_I2C5_SDA"), + PINCTRL_PIN(75, "LPSS_I2C5_SCL"), + PINCTRL_PIN(76, "LPSS_I3C0_SDA"), + PINCTRL_PIN(77, "LPSS_I3C0_SCL"), + PINCTRL_PIN(78, "LPSS_I3C0_SCL_FB"), + PINCTRL_PIN(79, "LPSS_I3C1_SDA"), + PINCTRL_PIN(80, "LPSS_I3C1_SCL"), + PINCTRL_PIN(81, "LPSS_I3C1_SCL_FB"), + PINCTRL_PIN(82, "ISH_I2C0_SDA"), + PINCTRL_PIN(83, "ISH_I2C0_SCL"), + PINCTRL_PIN(84, "ISH_I2C1_SCL"), + PINCTRL_PIN(85, "ISH_I2C1_SDA"), + PINCTRL_PIN(86, "DBG_PMODE"), + PINCTRL_PIN(87, "BJTAG_TCK"), + PINCTRL_PIN(88, "BJTAG_TDI"), + PINCTRL_PIN(89, "BJTAGX"), + PINCTRL_PIN(90, "BPREQ_B"), + PINCTRL_PIN(91, "BJTAG_TMS"), + PINCTRL_PIN(92, "BPRDY_B"), + PINCTRL_PIN(93, "BJTAG_TDO"), + PINCTRL_PIN(94, "BJTAG_TRST_B_0"), + PINCTRL_PIN(95, "ISH_I3C0_SDA"), + PINCTRL_PIN(96, "ISH_I3C0_SCL"), + PINCTRL_PIN(97, "ISH_I3C0_SCL_FB"), + PINCTRL_PIN(98, "AVS_I2S_BCLK_0"), + PINCTRL_PIN(99, "AVS_I2S_MCLK_0"), + PINCTRL_PIN(100, "AVS_I2S_SFRM_0"), + PINCTRL_PIN(101, "AVS_I2S_RXD_0"), + PINCTRL_PIN(102, "AVS_I2S_TXD_0"), + PINCTRL_PIN(103, "AVS_I2S_BCLK_1"), + PINCTRL_PIN(104, "AVS_I2S_SFRM_1"), + PINCTRL_PIN(105, "AVS_I2S_RXD_1"), + PINCTRL_PIN(106, "AVS_I2S_TXD_1"), + PINCTRL_PIN(107, "AVS_I2S_BCLK_2"), + PINCTRL_PIN(108, "AVS_I2S_SFRM_2"), + PINCTRL_PIN(109, "AVS_I2S_RXD_2"), + PINCTRL_PIN(110, "AVS_I2S_TXD_2"), + PINCTRL_PIN(111, "AVS_I2S_BCLK_3"), + PINCTRL_PIN(112, "AVS_I2S_SFRM_3"), + PINCTRL_PIN(113, "AVS_I2S_RXD_3"), + PINCTRL_PIN(114, "AVS_I2S_TXD_3"), + PINCTRL_PIN(115, "AVS_I2S_BCLK_4"), + PINCTRL_PIN(116, "AVS_I2S_SFRM_4"), + PINCTRL_PIN(117, "AVS_I2S_RXD_4"), + PINCTRL_PIN(118, "AVS_I2S_TXD_4"), + PINCTRL_PIN(119, "AVS_I2S_SFRM_5"), + PINCTRL_PIN(120, "AVS_I2S_RXD_5"), + PINCTRL_PIN(121, "AVS_I2S_TXD_5"), + PINCTRL_PIN(122, "AVS_I2S_BCLK_5"), + PINCTRL_PIN(123, "AVS_SNDW_CLK_0"), + PINCTRL_PIN(124, "AVS_SNDW_DATA_0"), + PINCTRL_PIN(125, "AVS_SNDW_CLK_1"), + PINCTRL_PIN(126, "AVS_SNDW_DATA_1"), + PINCTRL_PIN(127, "AVS_SNDW_CLK_2"), + PINCTRL_PIN(128, "AVS_SNDW_DATA_2"), + PINCTRL_PIN(129, "AVS_SNDW_CLK_3"), + PINCTRL_PIN(130, "AVS_SNDW_DATA_3"), + PINCTRL_PIN(131, "VISA_PTI_CH0_D0_internal"), + PINCTRL_PIN(132, "VISA_PTI_CH0_D1_internal"), + PINCTRL_PIN(133, "VISA_PTI_CH0_D2_internal"), + PINCTRL_PIN(134, "VISA_PTI_CH0_D3_internal"), + PINCTRL_PIN(135, "VISA_PTI_CH0_D4_internal"), + PINCTRL_PIN(136, "VISA_PTI_CH0_D5_internal"), + PINCTRL_PIN(137, "VISA_PTI_CH0_D6_internal"), + PINCTRL_PIN(138, "VISA_PTI_CH0_D7_internal"), + PINCTRL_PIN(139, "VISA_PTI_CH0_CLK_internal"), + PINCTRL_PIN(140, "VISA_PTI_CH1_D0_internal"), + PINCTRL_PIN(141, "VISA_PTI_CH1_D1_internal"), + PINCTRL_PIN(142, "VISA_PTI_CH1_D2_internal"), + PINCTRL_PIN(143, "VISA_PTI_CH1_D3_internal"), + PINCTRL_PIN(144, "VISA_PTI_CH1_D4_internal"), + PINCTRL_PIN(145, "VISA_PTI_CH1_D5_internal"), + PINCTRL_PIN(146, "VISA_PTI_CH1_D6_internal"), + PINCTRL_PIN(147, "VISA_PTI_CH1_D7_internal"), + PINCTRL_PIN(148, "VISA_PTI_CH1_CLK_internal"), + /* WEST */ + PINCTRL_PIN(149, "LPSS_UART0_TXD"), + PINCTRL_PIN(150, "LPSS_UART0_RXD"), + PINCTRL_PIN(151, "LPSS_UART0_RTS_B"), + PINCTRL_PIN(152, "LPSS_UART0_CTS_B"), + PINCTRL_PIN(153, "LPSS_UART1_RXD"), + PINCTRL_PIN(154, "LPSS_UART1_TXD"), + PINCTRL_PIN(155, "LPSS_UART1_RTS_B"), + PINCTRL_PIN(156, "LPSS_UART1_CTS_B"), + PINCTRL_PIN(157, "ISH_UART0_RXD"), + PINCTRL_PIN(158, "ISH_UART0_TXD"), + PINCTRL_PIN(159, "ISH_UART0_RTSB"), + PINCTRL_PIN(160, "ISH_UART0_CTSB"), + PINCTRL_PIN(161, "LPSS_SSP_0_CLK"), + PINCTRL_PIN(162, "LPSS_SSP_0_CLK_FB"), + PINCTRL_PIN(163, "LPSS_SSP_0_FS0"), + PINCTRL_PIN(164, "LPSS_SSP_0_FS1"), + PINCTRL_PIN(165, "LPSS_SSP_0_RXD"), + PINCTRL_PIN(166, "LPSS_SSP_0_TXD"), + PINCTRL_PIN(167, "ISH_UART1_RXD"), + PINCTRL_PIN(168, "ISH_UART1_TXD"), + PINCTRL_PIN(169, "ISH_UART1_RTSB"), + PINCTRL_PIN(170, "ISH_UART1_CTSB"), + PINCTRL_PIN(171, "LPSS_SSP_1_FS0"), + PINCTRL_PIN(172, "LPSS_SSP_1_FS1"), + PINCTRL_PIN(173, "LPSS_SSP_1_CLK"), + PINCTRL_PIN(174, "LPSS_SSP_1_CLK_FB"), + PINCTRL_PIN(175, "LPSS_SSP_1_RXD"), + PINCTRL_PIN(176, "LPSS_SSP_1_TXD"), + PINCTRL_PIN(177, "LPSS_SSP_2_CLK"), + PINCTRL_PIN(178, "LPSS_SSP_2_CLK_FB"), + PINCTRL_PIN(179, "LPSS_SSP_2_FS0"), + PINCTRL_PIN(180, "LPSS_SSP_2_FS1"), + PINCTRL_PIN(181, "LPSS_SSP_2_RXD"), + PINCTRL_PIN(182, "LPSS_SSP_2_TXD"), + PINCTRL_PIN(183, "ISH_SPI0_CSB0"), + PINCTRL_PIN(184, "ISH_SPI0_CSB1"), + PINCTRL_PIN(185, "ISH_SPI0_CLK"), + PINCTRL_PIN(186, "ISH_SPI0_MISO"), + PINCTRL_PIN(187, "ISH_SPI0_MOSI"), + PINCTRL_PIN(188, "ISH_GP_0"), + PINCTRL_PIN(189, "ISH_GP_1"), + PINCTRL_PIN(190, "ISH_GP_2"), + PINCTRL_PIN(191, "ISH_GP_13"), + PINCTRL_PIN(192, "ISH_GP_3"), + PINCTRL_PIN(193, "ISH_GP_4"), + PINCTRL_PIN(194, "ISH_GP_5"), + PINCTRL_PIN(195, "ISH_GP_6"), + PINCTRL_PIN(196, "ISH_GP_7"), + PINCTRL_PIN(197, "ISH_GP_8"), + PINCTRL_PIN(198, "ISH_GP_9"), + PINCTRL_PIN(199, "ISH_GP_10"), + PINCTRL_PIN(200, "ISH_GP_11"), + PINCTRL_PIN(201, "ISH_GP_14"), + PINCTRL_PIN(202, "ISH_GP_15"), + PINCTRL_PIN(203, "ISH_GP_22"), + PINCTRL_PIN(204, "ISH_GP_12"), + PINCTRL_PIN(205, "ISH_GP_30_USB_OC"), + PINCTRL_PIN(206, "LPDDRx_RESET0_n"), + PINCTRL_PIN(207, "UFS_RESET_B"), + PINCTRL_PIN(208, "UFS_REFCLK0"), + PINCTRL_PIN(209, "EMMC_SD_CLK"), + PINCTRL_PIN(210, "EMMC_SD_D0"), + PINCTRL_PIN(211, "EMMC_SD_D1"), + PINCTRL_PIN(212, "EMMC_SD_D2"), + PINCTRL_PIN(213, "EMMC_SD_D3"), + PINCTRL_PIN(214, "EMMC_D4"), + PINCTRL_PIN(215, "EMMC_D5"), + PINCTRL_PIN(216, "EMMC_D6"), + PINCTRL_PIN(217, "EMMC_D7"), + PINCTRL_PIN(218, "EMMC_SD_CMD"), + PINCTRL_PIN(219, "EMMC_RCLK"), + PINCTRL_PIN(220, "SDCARD_CLK_FB"), + PINCTRL_PIN(221, "SD_Virtual_GPIO"), + PINCTRL_PIN(222, "OSC_CLK_OUT_NFC"), + PINCTRL_PIN(223, "OSC_CLK_OUT_CAM_0"), + PINCTRL_PIN(224, "OSC_CLK_OUT_CAM_1"), + PINCTRL_PIN(225, "OSC_CLK_OUT_CAM_2"), + PINCTRL_PIN(226, "OSC_CLK_OUT_CAM_3"), + PINCTRL_PIN(227, "PCIe_LINKDOWN"), + PINCTRL_PIN(228, "NFC_CLK_REQ"), + PINCTRL_PIN(229, "PCIE_CLKREQ_N_DEV2"), + PINCTRL_PIN(230, "PCIE_CLKREQ_N_DEV3"), + PINCTRL_PIN(231, "PCIE_CLKREQ_N_DEV4"), + PINCTRL_PIN(232, "PCIE_CLKREQ_N_DEV1"), + PINCTRL_PIN(233, "PCIE_CLKREQ_N_DEV0"), + PINCTRL_PIN(234, "GMBUS_1_SCL"), + PINCTRL_PIN(235, "GMBUS_1_SDA"), + PINCTRL_PIN(236, "GMBUS_0_SCL"), + PINCTRL_PIN(237, "GMBUS_0_SDA"), + /* SOUTHEAST */ + PINCTRL_PIN(238, "COMPUTE_PMIC_SVID_DATA"), + PINCTRL_PIN(239, "COMPUTE_PMIC_SVID_CLK"), + PINCTRL_PIN(240, "COMPUTE_PMIC_SVID_ALERT_B"), + PINCTRL_PIN(241, "ROP_PMIC_I2C_SCL"), + PINCTRL_PIN(242, "ROP_PMIC_I2C_SDA"), + PINCTRL_PIN(243, "ISH_TYPEC_I2C2_SDA"), + PINCTRL_PIN(244, "ISH_TYPEC_I2C2_SCL"), + PINCTRL_PIN(245, "COMPUTE_PMU_PROCHOT_B"), + PINCTRL_PIN(246, "PMU_CATERR_B"), + PINCTRL_PIN(247, "COMPUTE_PMIC_VR_READY"), + PINCTRL_PIN(248, "FORCE_FW_RELOAD"), + PINCTRL_PIN(249, "ROP_PMIC_IRQ_ISH_GPIO31_TPC_ALERT_B"), + PINCTRL_PIN(250, "ROP_PMIC_RESET_B"), + PINCTRL_PIN(251, "ROP_PMIC_STNBY_SLP_S0_B"), + PINCTRL_PIN(252, "ROP_PMIC_THERMTRIP_B"), + PINCTRL_PIN(253, "MODEM_CLKREQ"), + PINCTRL_PIN(254, "TPC0_BSSB_SBU1"), + PINCTRL_PIN(255, "TPC0_BSSB_SBU2"), + PINCTRL_PIN(256, "OSC_CLK_OUT_CAM_4"), + PINCTRL_PIN(257, "HPD1"), + PINCTRL_PIN(258, "HPD0"), + PINCTRL_PIN(259, "PMC_TIME_SYNC_0"), + PINCTRL_PIN(260, "PMC_TIME_SYNC_1"), + PINCTRL_PIN(261, "OSC_CLK_OUT_CAM_5"), + PINCTRL_PIN(262, "ISH_GP_20"), + PINCTRL_PIN(263, "ISH_GP_16"), + PINCTRL_PIN(264, "ISH_GP_17"), + PINCTRL_PIN(265, "ISH_GP_18"), + PINCTRL_PIN(266, "ISH_GP_19"), +}; + +static const struct intel_padgroup lkf_community0_gpps[] = { + LKF_GPP(0, 0, 31, 0), /* EAST_0 */ + LKF_GPP(1, 32, 59, 32), /* EAST_1 */ +}; + +static const struct intel_padgroup lkf_community1_gpps[] = { + LKF_GPP(0, 60, 91, 64), /* NORTHWEST_0 */ + LKF_GPP(1, 92, 123, 96), /* NORTHWEST_1 */ + LKF_GPP(2, 124, 148, 128), /* NORTHWEST_2 */ +}; + +static const struct intel_padgroup lkf_community2_gpps[] = { + LKF_GPP(0, 149, 180, 160), /* WEST_0 */ + LKF_GPP(1, 181, 212, 192), /* WEST_1 */ + LKF_GPP(2, 213, 237, 224), /* WEST_2 */ +}; + +static const struct intel_padgroup lkf_community3_gpps[] = { + LKF_GPP(0, 238, 266, 256), /* SOUTHEAST */ +}; + +static const struct intel_community lkf_communities[] = { + LKF_COMMUNITY(0, 0, 59, lkf_community0_gpps), /* EAST */ + LKF_COMMUNITY(1, 60, 148, lkf_community1_gpps), /* NORTHWEST */ + LKF_COMMUNITY(2, 149, 237, lkf_community2_gpps), /* WEST */ + LKF_COMMUNITY(3, 238, 266, lkf_community3_gpps), /* SOUTHEAST */ +}; + +static const struct intel_pinctrl_soc_data lkf_soc_data = { + .pins = lkf_pins, + .npins = ARRAY_SIZE(lkf_pins), + .communities = lkf_communities, + .ncommunities = ARRAY_SIZE(lkf_communities), +}; + +static const struct acpi_device_id lkf_pinctrl_acpi_match[] = { + { "INT34C4", (kernel_ulong_t)&lkf_soc_data }, + { } +}; +MODULE_DEVICE_TABLE(acpi, lkf_pinctrl_acpi_match); + +static INTEL_PINCTRL_PM_OPS(lkf_pinctrl_pm_ops); + +static struct platform_driver lkf_pinctrl_driver = { + .probe = intel_pinctrl_probe_by_hid, + .driver = { + .name = "lakefield-pinctrl", + .acpi_match_table = lkf_pinctrl_acpi_match, + .pm = &lkf_pinctrl_pm_ops, + }, +}; +module_platform_driver(lkf_pinctrl_driver); + +MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); +MODULE_DESCRIPTION("Intel Lakefield PCH pinctrl/GPIO driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index 96589d01fe35..0a48ca46ab59 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -496,7 +496,7 @@ static int lp_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin, enum pin_config_param param = pinconf_to_config_param(*config); unsigned long flags; u32 value, pull; - u16 arg = 0; + u16 arg; raw_spin_lock_irqsave(&lg->lock, flags); value = ioread32(conf2); @@ -506,8 +506,9 @@ static int lp_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin, switch (param) { case PIN_CONFIG_BIAS_DISABLE: - if (pull) + if (pull != GPIWP_NONE) return -EINVAL; + arg = 0; break; case PIN_CONFIG_BIAS_PULL_DOWN: if (pull != GPIWP_DOWN) @@ -550,6 +551,7 @@ static int lp_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin, switch (param) { case PIN_CONFIG_BIAS_DISABLE: value &= ~GPIWP_MASK; + value |= GPIWP_NONE; break; case PIN_CONFIG_BIAS_PULL_DOWN: value &= ~GPIWP_MASK; @@ -872,6 +874,7 @@ static int lp_gpio_probe(struct platform_device *pdev) gc->direction_output = lp_gpio_direction_output; gc->get = lp_gpio_get; gc->set = lp_gpio_set; + gc->set_config = gpiochip_generic_config; gc->get_direction = lp_gpio_get_direction; gc->base = -1; gc->ngpio = LP_NUM_GPIO; @@ -967,13 +970,12 @@ static int __init lp_gpio_init(void) { return platform_driver_register(&lp_gpio_driver); } +subsys_initcall(lp_gpio_init); static void __exit lp_gpio_exit(void) { platform_driver_unregister(&lp_gpio_driver); } - -subsys_initcall(lp_gpio_init); module_exit(lp_gpio_exit); MODULE_AUTHOR("Mathias Nyman (Intel)"); |