summaryrefslogtreecommitdiffstats
path: root/drivers/pinctrl/intel
diff options
context:
space:
mode:
authorMika Westerberg <mika.westerberg@linux.intel.com>2017-06-06 16:18:18 +0300
committerLinus Walleij <linus.walleij@linaro.org>2017-06-09 13:02:50 +0200
commit1f6b419b24285409a9365461bf7367a220eff1db (patch)
treeb0c0b97d3d8aa431b63e97576edb083e75c4096d /drivers/pinctrl/intel
parent919eb4756ef41fd71b5eaae8a2a067fcde9d44d7 (diff)
downloadlinux-1f6b419b24285409a9365461bf7367a220eff1db.tar.bz2
pinctrl: intel: Make it possible to specify mode per pin in a group
On some SoCs not all pins in a group use the same mode when a certain function is muxed out of them. This makes it possible to specify mode per pin as an array instead in addition to single integer. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/intel')
-rw-r--r--drivers/pinctrl/intel/pinctrl-intel.c6
-rw-r--r--drivers/pinctrl/intel/pinctrl-intel.h28
2 files changed, 26 insertions, 8 deletions
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index 78c48497c9e6..6dc1096d3d34 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -398,7 +398,11 @@ static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
value = readl(padcfg0);
value &= ~PADCFG0_PMODE_MASK;
- value |= grp->mode << PADCFG0_PMODE_SHIFT;
+
+ if (grp->modes)
+ value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
+ else
+ value |= grp->mode << PADCFG0_PMODE_SHIFT;
writel(value, padcfg0);
}
diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h
index b251a9e86970..7fdb07753c2d 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.h
+++ b/drivers/pinctrl/intel/pinctrl-intel.h
@@ -22,13 +22,16 @@ struct device;
* @name: Name of the groups
* @pins: All pins in this group
* @npins: Number of pins in this groups
- * @mode: Native mode in which the group is muxed out @pins
+ * @mode: Native mode in which the group is muxed out @pins. Used if @modes
+ * is %NULL.
+ * @modes: If not %NULL this will hold mode for each pin in @pins
*/
struct intel_pingroup {
const char *name;
const unsigned *pins;
size_t npins;
unsigned short mode;
+ const unsigned *modes;
};
/**
@@ -112,12 +115,23 @@ struct intel_community {
#define PINCTRL_FEATURE_DEBOUNCE BIT(0)
#define PINCTRL_FEATURE_1K_PD BIT(1)
-#define PIN_GROUP(n, p, m) \
- { \
- .name = (n), \
- .pins = (p), \
- .npins = ARRAY_SIZE((p)), \
- .mode = (m), \
+/**
+ * PIN_GROUP - Declare a pin group
+ * @n: Name of the group
+ * @p: An array of pins this group consists
+ * @m: Mode which the pins are put when this group is active. Can be either
+ * a single integer or an array of integers in which case mode is per
+ * pin.
+ */
+#define PIN_GROUP(n, p, m) \
+ { \
+ .name = (n), \
+ .pins = (p), \
+ .npins = ARRAY_SIZE((p)), \
+ .mode = __builtin_choose_expr( \
+ __builtin_constant_p((m)), (m), 0), \
+ .modes = __builtin_choose_expr( \
+ __builtin_constant_p((m)), NULL, (m)), \
}
#define FUNCTION(n, g) \