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authorAndrew Jeffery <andrew@aj.id.au>2017-01-23 15:57:17 +1030
committerLinus Walleij <linus.walleij@linaro.org>2017-01-26 14:42:39 +0100
commit8ccb6dc6e999008bc5d50bdb5badedd636f58e1c (patch)
tree3196841360f260475671abd2e350d9cf1c0ebd58 /drivers/pinctrl/aspeed
parent7153f8ef679d5fcb2d9c69a19613399194600f5b (diff)
downloadlinux-8ccb6dc6e999008bc5d50bdb5badedd636f58e1c.tar.bz2
pinctrl: aspeed: g4: Fix mux configuration for GPIOs AA[4-7], AB[0-7]
Incorrect video output configuration bits were being tested on pins in GPIO banks AA and AB for the ROM{8,16} mux functions. The ROM{8,16} functions are the highest priority for the relevant pins and also the default function, so we require the relevant video output configuration be disabled to mux GPIO functionality. As the wrong bits were being tested a GPIO export would succeed but leave the pin in an unresponsive state (i.e. value updates were ignored). This misbehaviour was discovered as part of extending the GPIO controller's support to cover banks Y, Z, AA, AB and AC (AC in the case of the g5 SoC). Fixes: 6d329f14a75f ("pinctrl: aspeed-g4: Add mux configuration for all pins") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/aspeed')
-rw-r--r--drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c32
1 files changed, 16 insertions, 16 deletions
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
index 09b668415c56..7de596e2b9d4 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
@@ -1615,8 +1615,8 @@ MS_PIN_DECL(L19, GPIOAA3, ROMA13, VPOG3);
#define L20 212
#define L20_DESC SIG_DESC_SET(SCUA4, 28)
-SIG_EXPR_DECL(ROMA14, ROM8, L20_DESC, VPO_24_OFF);
-SIG_EXPR_DECL(ROMA14, ROM16, L20_DESC, VPO_24_OFF);
+SIG_EXPR_DECL(ROMA14, ROM8, L20_DESC, VPO_OFF_12);
+SIG_EXPR_DECL(ROMA14, ROM16, L20_DESC, VPO_OFF_12);
SIG_EXPR_LIST_DECL_DUAL(ROMA14, ROM8, ROM16);
SIG_EXPR_DECL(VPOG4, VPO24, L20_DESC, VPO24_DESC);
SIG_EXPR_DECL(VPOG4, VPOOFF1, L20_DESC, VPOOFF1_DESC);
@@ -1625,8 +1625,8 @@ MS_PIN_DECL(L20, GPIOAA4, ROMA14, VPOG4);
#define L21 213
#define L21_DESC SIG_DESC_SET(SCUA4, 29)
-SIG_EXPR_DECL(ROMA15, ROM8, L21_DESC, VPO_24_OFF);
-SIG_EXPR_DECL(ROMA15, ROM16, L21_DESC, VPO_24_OFF);
+SIG_EXPR_DECL(ROMA15, ROM8, L21_DESC, VPO_OFF_12);
+SIG_EXPR_DECL(ROMA15, ROM16, L21_DESC, VPO_OFF_12);
SIG_EXPR_LIST_DECL_DUAL(ROMA15, ROM8, ROM16);
SIG_EXPR_DECL(VPOG5, VPO24, L21_DESC, VPO24_DESC);
SIG_EXPR_DECL(VPOG5, VPOOFF1, L21_DESC, VPOOFF1_DESC);
@@ -1635,8 +1635,8 @@ MS_PIN_DECL(L21, GPIOAA5, ROMA15, VPOG5);
#define T18 214
#define T18_DESC SIG_DESC_SET(SCUA4, 30)
-SIG_EXPR_DECL(ROMA16, ROM8, T18_DESC, VPO_24_OFF);
-SIG_EXPR_DECL(ROMA16, ROM16, T18_DESC, VPO_24_OFF);
+SIG_EXPR_DECL(ROMA16, ROM8, T18_DESC, VPO_OFF_12);
+SIG_EXPR_DECL(ROMA16, ROM16, T18_DESC, VPO_OFF_12);
SIG_EXPR_LIST_DECL_DUAL(ROMA16, ROM8, ROM16);
SIG_EXPR_DECL(VPOG6, VPO24, T18_DESC, VPO24_DESC);
SIG_EXPR_DECL(VPOG6, VPOOFF1, T18_DESC, VPOOFF1_DESC);
@@ -1645,8 +1645,8 @@ MS_PIN_DECL(T18, GPIOAA6, ROMA16, VPOG6);
#define N18 215
#define N18_DESC SIG_DESC_SET(SCUA4, 31)
-SIG_EXPR_DECL(ROMA17, ROM8, N18_DESC, VPO_24_OFF);
-SIG_EXPR_DECL(ROMA17, ROM16, N18_DESC, VPO_24_OFF);
+SIG_EXPR_DECL(ROMA17, ROM8, N18_DESC, VPO_OFF_12);
+SIG_EXPR_DECL(ROMA17, ROM16, N18_DESC, VPO_OFF_12);
SIG_EXPR_LIST_DECL_DUAL(ROMA17, ROM8, ROM16);
SIG_EXPR_DECL(VPOG7, VPO24, N18_DESC, VPO24_DESC);
SIG_EXPR_DECL(VPOG7, VPOOFF1, N18_DESC, VPOOFF1_DESC);
@@ -1655,8 +1655,8 @@ MS_PIN_DECL(N18, GPIOAA7, ROMA17, VPOG7);
#define N19 216
#define N19_DESC SIG_DESC_SET(SCUA8, 0)
-SIG_EXPR_DECL(ROMA18, ROM8, N19_DESC, VPO_24_OFF);
-SIG_EXPR_DECL(ROMA18, ROM16, N19_DESC, VPO_24_OFF);
+SIG_EXPR_DECL(ROMA18, ROM8, N19_DESC, VPO_OFF_12);
+SIG_EXPR_DECL(ROMA18, ROM16, N19_DESC, VPO_OFF_12);
SIG_EXPR_LIST_DECL_DUAL(ROMA18, ROM8, ROM16);
SIG_EXPR_DECL(VPOR0, VPO24, N19_DESC, VPO24_DESC);
SIG_EXPR_DECL(VPOR0, VPOOFF1, N19_DESC, VPOOFF1_DESC);
@@ -1665,8 +1665,8 @@ MS_PIN_DECL(N19, GPIOAB0, ROMA18, VPOR0);
#define M18 217
#define M18_DESC SIG_DESC_SET(SCUA8, 1)
-SIG_EXPR_DECL(ROMA19, ROM8, M18_DESC, VPO_24_OFF);
-SIG_EXPR_DECL(ROMA19, ROM16, M18_DESC, VPO_24_OFF);
+SIG_EXPR_DECL(ROMA19, ROM8, M18_DESC, VPO_OFF_12);
+SIG_EXPR_DECL(ROMA19, ROM16, M18_DESC, VPO_OFF_12);
SIG_EXPR_LIST_DECL_DUAL(ROMA19, ROM8, ROM16);
SIG_EXPR_DECL(VPOR1, VPO24, M18_DESC, VPO24_DESC);
SIG_EXPR_DECL(VPOR1, VPOOFF1, M18_DESC, VPOOFF1_DESC);
@@ -1675,8 +1675,8 @@ MS_PIN_DECL(M18, GPIOAB1, ROMA19, VPOR1);
#define N22 218
#define N22_DESC SIG_DESC_SET(SCUA8, 2)
-SIG_EXPR_DECL(ROMA20, ROM8, N22_DESC, VPO_24_OFF);
-SIG_EXPR_DECL(ROMA20, ROM16, N22_DESC, VPO_24_OFF);
+SIG_EXPR_DECL(ROMA20, ROM8, N22_DESC, VPO_OFF_12);
+SIG_EXPR_DECL(ROMA20, ROM16, N22_DESC, VPO_OFF_12);
SIG_EXPR_LIST_DECL_DUAL(ROMA20, ROM8, ROM16);
SIG_EXPR_DECL(VPOR2, VPO24, N22_DESC, VPO24_DESC);
SIG_EXPR_DECL(VPOR2, VPOOFF1, N22_DESC, VPOOFF1_DESC);
@@ -1685,8 +1685,8 @@ MS_PIN_DECL(N22, GPIOAB2, ROMA20, VPOR2);
#define N20 219
#define N20_DESC SIG_DESC_SET(SCUA8, 3)
-SIG_EXPR_DECL(ROMA21, ROM8, N20_DESC, VPO_24_OFF);
-SIG_EXPR_DECL(ROMA21, ROM16, N20_DESC, VPO_24_OFF);
+SIG_EXPR_DECL(ROMA21, ROM8, N20_DESC, VPO_OFF_12);
+SIG_EXPR_DECL(ROMA21, ROM16, N20_DESC, VPO_OFF_12);
SIG_EXPR_LIST_DECL_DUAL(ROMA21, ROM8, ROM16);
SIG_EXPR_DECL(VPOR3, VPO24, N20_DESC, VPO24_DESC);
SIG_EXPR_DECL(VPOR3, VPOOFF1, N20_DESC, VPOOFF1_DESC);