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authorWill Deacon <will.deacon@arm.com>2017-06-26 10:54:27 +0100
committerWill Deacon <will.deacon@arm.com>2017-06-26 10:54:27 +0100
commit3edb1dd13ce6f6480c1f2bffc47a49cf959fa9cb (patch)
tree81e5823a1c84a0131dc110f711f3c1416b4df985 /drivers/perf
parent9ad95c46c18ba828dfcf467024a45eb5b43ce769 (diff)
parent77b246b32b2c4bc21e352dcb8b53a8aba81ee5a4 (diff)
downloadlinux-3edb1dd13ce6f6480c1f2bffc47a49cf959fa9cb.tar.bz2
Merge branch 'aarch64/for-next/ras-apei' into aarch64/for-next/core
Merge in arm64 ACPI RAS support (APEI/GHES) from Tyler Baicar.
Diffstat (limited to 'drivers/perf')
-rw-r--r--drivers/perf/arm_pmu_acpi.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/perf/arm_pmu_acpi.c b/drivers/perf/arm_pmu_acpi.c
index 34c862f213c7..0a9b78705ee8 100644
--- a/drivers/perf/arm_pmu_acpi.c
+++ b/drivers/perf/arm_pmu_acpi.c
@@ -29,6 +29,17 @@ static int arm_pmu_acpi_register_irq(int cpu)
return -EINVAL;
gsi = gicc->performance_interrupt;
+
+ /*
+ * Per the ACPI spec, the MADT cannot describe a PMU that doesn't
+ * have an interrupt. QEMU advertises this by using a GSI of zero,
+ * which is not known to be valid on any hardware despite being
+ * valid per the spec. Take the pragmatic approach and reject a
+ * GSI of zero for now.
+ */
+ if (!gsi)
+ return 0;
+
if (gicc->flags & ACPI_MADT_PERFORMANCE_IRQ_MODE)
trigger = ACPI_EDGE_SENSITIVE;
else